Commit 4429a42f authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@798 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent e459f9ba
This diff is collapsed.
This diff is collapsed.
-- The IQDemod entity takes a stream of I, Q, -I, -Q data at 80 MSPS and produces
-- two streams of 40 MSPS each. One contains I, I, I, ... data and the other one
-- contains Q, Q, Q, ... data. To do this, IQDemod relies on the IQCount value output
-- by IQCounter for sequencing.
-- It then negates (2's complement) every other sample and demultiplexes the result to
-- separate I from Q.
-- Input and outputs are all clocked.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IQDemodCW is
Port ( DataInA : in std_logic_vector(13 downto 0);
Clk80In : in std_logic;
CorrectOn: in std_logic;
IQCount : in std_logic_vector(1 downto 0);
IData : out std_logic_vector(13 downto 0);
QData : out std_logic_vector(13 downto 0));
end IQDemodCW;
architecture RTL of IQDemodCW is
signal clockedData: signed(13 downto 0);
signal iqCount0, iqCount1, demuxCtrl: std_logic;
signal convertedData, dataToDemux: signed(13 downto 0);
signal offsetI, offsetQ: signed(13 downto 0);
signal offsetIAux, offsetQAux, correctedData: signed(13 downto 0);
signal plusI, plusQ, minusI, minusQ: signed(13 downto 0);
begin
iqCount0 <= IQCount(0); -- for convenience
iqCount1 <= IQCount(1); -- for convenience
demuxCtrl <= iqCount0 xor iqCount1;
-- Process ClockData clocks the 14 bits coming from the ADC in the FPGA.
-- The flip-flops used here should be of the IFD type for best performance.
-- This process is also used to clock any other signals that need it inside the design.
ClockData: process(Clk80In)
begin
if Clk80In'event and Clk80In='1' then
clockedData <= signed(DataInA);
dataToDemux <= convertedData;
end if;
end process ClockData;
-- Process SignConversion translates the stream of i, q, -i, -q, ...
-- into a stream of i, q, i, q, ...
SignConversion: process(iqCount0, correctedData)
begin
if iqCount0='0' then
convertedData <= -correctedData;
else convertedData <= correctedData;
end if;
end process SignConversion;
-- The Demux process divides an 80 MSPS stream of i, q, i, q, ...
-- into two 40 MSPS streams of i, i, i, ... and q, q, q, ...
Demux: process(Clk80In)
begin
if Clk80In'event and Clk80In='1' then
if demuxCtrl = '1' then
QData <= std_logic_vector(dataToDemux);
else IData <= std_logic_vector(dataToDemux);
end if;
end if;
end process Demux;
Compensator: process(Clk80In)
begin
if Clk80In'event and Clk80In='1' then
case IQCount is
when "00" =>
minusQ <= clockedData;
when "01" =>
plusI <= clockedData;
when "11" =>
plusQ <= clockedData;
when "10" =>
minusI <= clockedData;
end case;
offsetIAux <= plusI + minusI;
offsetQAux <= plusQ + minusQ;
end if;
end process Compensator;
offsetI <= offsetIAux(13) & offsetIAux(13 downto 1);
offsetQ <= offsetQAux(13) & offsetQAux(13 downto 1);
correctedData <= clockedData;
end RTL;
JDF G
// Created by Project Navigator ver 1.0
PROJECT RFControl
DESIGN rfcontrolv3
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v2000
DEVICETIME 315558000
DEVPKG fg676
DEVPKGTIME 315558000
DEVSPEED -4
DEVSPEEDTIME 315558000
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL Synplify (VHDL)
SYNTHESISTOOLTIME 1088520530
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ..\sources\mul2x2.vhd
SOURCE ..\sources\ClockManager.vhd
SOURCE ..\sources\LedsTest.vhd
SOURCE ..\sources\SineCosine.vhd
SOURCE ..\sources\iqdemod.vhd
SOURCE ..\sources\ResControl.vhd
SOURCE ..\sources\VmeIntfce.vhd
SOURCE ..\sources\IQModulator.vhd
SOURCE ..\sources\IrqControl.vhd
SOURCE ..\sources\IQCounter.vhd
SOURCE ..\sources\RegistersMap.vhd
SOURCE ..\sources\VMEDecoder.vhd
SOURCE ..\sources\Commands.vhd
SOURCE ..\sources\RAMManager.vhd
SOURCE ..\sources\SetPoints.vhd
SOURCE ..\sources\PIController.vhd
SOURCE ..\sources\Snapshots.vhd
SOURCE ..\sources\FeedForward.vhd
SOURCE ..\sources\Diagnostics.vhd
SOURCE ..\sources\SatControl.vhd
SOURCE ..\sources\OneShot.vhd
SOURCE ..\sources\PIControllerCW.vhd
SOURCE ..\sources\SatControlCW.vhd
SOURCE ..\sources\iqdemodcw.vhd
SOURCE ..\sources\CavityControlCWV3.vhd
DEPASSOC ledstest ..\sources\ledsconstraints.ucf
DEPASSOC cavitycontrolcwv3 ..\sources\cavityconstraintsV3.ucf
[Normal]
p_AutoGenFile=synvhd, virtex2, Implementation.t_genImpactFile, 1068747285, True
p_ChainDescFile=synvhd, virtex2, Implementation.t_genImpactFile, 1087824130,
xilxMapCoverMode=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1070037511, Speed
xilxMapPackRegInto=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1051284026, For Inputs and Outputs
xilxMapReportDetail=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1070037511, False
xilxMapTimingDrivenPacking=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1088672628, False
xilxPAReffortLevel=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1049383307, Medium
_SynthFrequency=synvhd, virtex2, Synthesis.t_synthesize, 1049879617, 40
_SynthResourceSharing=synvhd, virtex2, Synthesis.t_synthesize, 1070036051, True
[STATUS-ALL]
cavitycontrolcwv3.ncdFile=WARNINGS,1105627070
cavitycontrolcwv3.ngdFile=WARNINGS,1105627041
[STRATEGY-LIST]
Normal=True
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment