Commit 553de2b7 authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@1244 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent 2bc4f51d
......@@ -535,6 +535,7 @@ COMPONENT setpoints
WriteFromRM : IN std_logic;
RFONFalling : IN std_logic;
RFONRising : IN std_logic;
PresentCycle: in std_logic_vector(4 downto 0);
ConfigMode : IN std_logic;
RAMData : INOUT std_logic_vector(15 downto 0);
DataToRM : OUT std_logic_vector(15 downto 0);
......@@ -666,9 +667,9 @@ begin
antiWindUp <= not registers(CONTROLR)(2);
-- VHDL date registers: 8 June 2008
registers(VHDLVERHR) <= X"484B";
registers(VHDLVERLR) <= X"BDA5";
-- VHDL date registers: 19 June 2008
registers(VHDLVERHR) <= X"485A";
registers(VHDLVERLR) <= X"1B4D";
RAM1Addr <= ram1AddrAux;
RAM1OEN <= ram1OEAux;
......@@ -819,6 +820,7 @@ U0_setpoints: setpoints PORT MAP(
DataToRMValid => spDataValid,
RFONFalling => rfOnFalling,
RFONRising => rfOnRising,
PresentCycle => registers(PRESENTCYCLER)(4 downto 0),
ConfigMode => configMode,
IDataToProcess => spIDataToPI,
QDataToProcess => spQDataToPI,
......@@ -841,6 +843,7 @@ U1_setpoints: setpoints PORT MAP(
DataToRMValid => ffDataValid,
RFONFalling => rfOnFalling,
RFONRising => rfOnRising,
PresentCycle => registers(PRESENTCYCLER)(4 downto 0),
ConfigMode => configMode,
IDataToProcess => ffIDataToLoop,
QDataToProcess => ffQDataToLoop,
......
......@@ -160,12 +160,12 @@ begin
rfOnIRQSource <= '0';
startCycleIRQSource <= '0';
elsif Clk'event and Clk='1' then
if rfOnFallingOut='1' then
if rfOnFallingOut='1' and IrqEnable='1' then
rfOnIRQSource <= '1';
elsif ReadIRQSRCR='1' then
rfOnIRQSource <= '0';
end if;
if startCycleRising='1' then
if startCycleRising='1' and IrqEnable='1' then
startCycleIRQSource <= '1';
elsif ReadIRQSRCR='1' then
startCycleIRQSource <= '0';
......
......@@ -16,6 +16,7 @@ entity SetPoints is
RFONFalling: in std_logic;
RFONRising: in std_logic;
PresentCycle: in std_logic_vector(4 downto 0);
ConfigMode: in std_logic;
IDataToProcess: out std_logic_vector(15 downto 0);
......@@ -31,7 +32,7 @@ end SetPoints;
architecture RTL of SetPoints is
type StateType is (Idle, rmRead, rmReadWaiting, rmReadWaiting2, rmDataValid, rmWrite, rmWriteDone, rfOnRead);
type StateType is (Idle, rmRead, rmReadWaiting, rmReadWaiting2, rmReadWaiting3, rmDataValid, rmWrite, rmWriteDone, rfOnRead);
signal currentState, nextState: StateType;
signal ramDataIn, ramDataInC, ramDataOut: std_logic_vector(15 downto 0);
......@@ -42,12 +43,15 @@ signal rmPendingWrite, rmPendingRead: std_logic;
signal ramAddrAux: unsigned(17 downto 0);
signal spCounter: unsigned(4 downto 0);
signal signedSPCounter: signed(13 downto 0);
signal iAuxH, iAuxL, qAuxH, qAuxL: std_logic_vector(15 downto 0);
signal iAuxn, qAuxn, iAuxnp1, qAuxnp1: signed(13 downto 0); -- I(n), Q(n), I(n+1), Q(n+1)
signal iCurrent, qCurrent: signed(13 downto 0);
signal bigStepI, bigStepQ: signed(13 downto 0);
signal smallStepI, smallStepQ: signed(13 downto 0);
signal incrementI, incrementQ: signed(13 downto 0);
signal iOutAux, qOutAux: signed(13 downto 0);
signal presCycleAux: std_logic_vector(4 downto 0);
signal xn, xnAux: unsigned(15 downto 0);
begin
......@@ -56,10 +60,10 @@ ramDataIn <= RAMData;
-- RAMCS <= '0';
RAMAddress <= std_logic_vector(ramAddrAux);
smallStepI <= bigStepI(13) & bigStepI(13) & bigStepI(13) & bigStepI(13)
& bigStepI(13) & bigStepI(13 downto 5);
smallStepQ <= bigStepQ(13) & bigStepQ(13) & bigStepQ(13) & bigStepQ(13)
& bigStepQ(13) & bigStepQ(13 downto 5);
smallStepI <= bigStepI(13) & bigStepI(13) & bigStepI(13) &
bigStepI(13) & bigStepI(13) & bigStepI(13 downto 5);
smallStepQ <= bigStepQ(13) & bigStepQ(13) & bigStepQ(13) &
bigStepQ(13) & bigStepQ(13) & bigStepQ(13 downto 5);
signedSPCounter <= signed("000000000" & spCounter);
incrementI <= (signedSPCounter * smallStepI) (13 downto 0);
incrementQ <= (signedSPCounter * smallStepQ) (13 downto 0);
......@@ -88,6 +92,17 @@ begin
end if;
end process PendingRM;
clockCycle: process(Clk40)
begin
if Clk40'event and Clk40='1' then
if SyncReset = '1' then
presCycleAux <= (others=>'0');
else
presCycleAux <= PresentCycle;
end if;
end if;
end process clockCycle;
CounterProcess: process(Clk40)
begin
if Clk40'event and Clk40='1' then
......@@ -128,6 +143,8 @@ begin
when rmReadWaiting =>
nextState <= rmReadWaiting2;
when rmReadWaiting2 =>
nextState <= rmReadWaiting3;
when rmReadWaiting3 =>
nextState <= rmDataValid;
when rmDataValid =>
nextState <= Idle;
......@@ -162,6 +179,12 @@ begin
bigStepQ <= (others=>'0');
iOutAux <= (others=>'0');
qOutAux <= (others=>'0');
xn <= (others=>'0');
xnAux <= (others=>'1');
iAuxH <= (others=>'0');
iAuxL <= (others=>'0');
qAuxH <= (others=>'0');
qAuxL <= (others=>'0');
if configMode='0' and RFONRising='1' then
RAMOE <= '0';
RAMCS <= '0';
......@@ -182,7 +205,7 @@ begin
when rmReadWaiting2 =>
RAMOE <= '0';
when rmDataValid =>
DataToRM <= ramDataIn;
DataToRM <= ramDataInC;
DataToRMValid <= '1';
when rmWrite =>
ramAddrAux <= unsigned(rmPendingAddr);
......@@ -197,23 +220,43 @@ begin
DataToProcessValid <= '1';
iOutAux <= iCurrent + incrementI;
qOutAux <= qCurrent + incrementQ;
if spCounter=to_unsigned(10, spCounter'length) or
spCounter=to_unsigned(20, spCounter'length) then
ramAddrAux <= ramAddrAux + 1;
end if;
if spCounter=to_unsigned(5, spCounter'length) then
iAuxnp1 <= signed(ramDataInC(13 downto 0));
iAuxn <= iAuxnp1;
end if;
if spCounter=to_unsigned(15, spCounter'length) then
qAuxnp1 <= signed(ramDataInC(13 downto 0));
qAuxn <= qAuxnp1;
if xn=to_unsigned(0, xn'length) and
(spCounter=to_unsigned(5, spCounter'length) or
spCounter=to_unsigned(10, spCounter'length) or
spCounter=to_unsigned(15, spCounter'length) or
spCounter=to_unsigned(20, spCounter'length) or
spCounter=to_unsigned(25, spCounter'length)) then
ramAddrAux <= (unsigned(presCycleAux)) & ((ramAddrAux + 1)(12 downto 0));
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(6, spCounter'length) then
xnAux <= unsigned(ramDataInC);
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(11, spCounter'length) then
iAuxH <= ramDataInC;
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(16, spCounter'length) then
iAuxL <= ramDataInC;
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(21, spCounter'length) then
qAuxH <= ramDataInC;
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(26, spCounter'length) then
qAuxL <= ramDataInC;
end if;
if spCounter=to_unsigned(31, spCounter'length) then
iCurrent <= iAuxn;
qCurrent <= qAuxn;
bigStepI <= iAuxnp1 - iAuxn;
bigStepQ <= qAuxnp1 - qAuxn;
if xn=to_unsigned(0, xn'length) then
xn <= xnAux - 1;
else
xn <= xn - 1;
end if;
iAuxn <= signed(iAuxH(13 downto 0));
qAuxn <= signed(qAuxH(13 downto 0));
iCurrent <= iCurrent + iAuxn;
qCurrent <= qCurrent + qAuxn;
bigStepI <= signed(iAuxH(13 downto 0));
bigStepQ <= signed(qAuxH(13 downto 0));
end if;
when others =>
writing <= '0';
......
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