Commit 65b3eaba authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@714 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent 3249347e
......@@ -337,6 +337,7 @@ COMPONENT picontroller
KI : OUT std_logic_vector(15 downto 0);
PropOut : OUT std_logic_vector(13 downto 0);
IntOut : OUT std_logic_vector(13 downto 0);
LongIntOut: out std_logic_vector(17 downto 0);
ErrorOut : OUT std_logic_vector(13 downto 0)
);
END COMPONENT;
......@@ -569,6 +570,7 @@ signal saturated, badlySaturated: std_logic;
signal cavIFixed, cavQFixed: std_logic_vector(13 downto 0);
signal cavIToMod, cavQToMod: std_logic_vector(13 downto 0);
signal satDisabled: std_logic;
signal cavILongInt, cavQLongInt: std_logic_vector(17 downto 0);
begin
......@@ -1015,6 +1017,7 @@ I_picontroller: picontroller PORT MAP(
KI => registers(KIR),
PropOut => cavIProp,
IntOut => cavIInt,
LongIntOut => cavILongInt,
ErrorOut => cavIErr
);
......@@ -1036,6 +1039,7 @@ Q_picontroller: picontroller PORT MAP(
KI => open,
PropOut => cavQProp,
IntOut => cavQInt,
LongIntOut => cavQLongInt,
ErrorOut => cavQErr
);
......@@ -1096,10 +1100,10 @@ U2_oneshot: oneshot PORT MAP(
PulseOut => RefLed
);
badlySaturated <= '1' when (cavISat="01111111111111" or
cavISat="10000000000000" or
cavQSat="01111111111111" or
cavQSat="10000000000000") else '0';
badlySaturated <= '1' when (cavILongInt="011111111111111111" or
cavILongInt="100000000000000000" or
cavQLongInt="011111111111111111" or
cavQLongInt="100000000000000000") else '0';
SwControl <= registers(SWCTRLR)(2) & registers(SWCTRLR)(1) &
registers(SWCTRLR)(0) & registers(SWCTRLR)(3);
......
......@@ -20,6 +20,7 @@ entity PIController is
KI : out std_logic_vector(15 downto 0);
PropOut : out std_logic_vector(13 downto 0);
IntOut : out std_logic_vector(13 downto 0);
LongIntOut: out std_logic_vector(17 downto 0);
ErrorOut : out std_logic_vector(13 downto 0));
end PIController;
......@@ -30,30 +31,35 @@ signal kpSigned, kiSigned: signed(13 downto 0);
signal currentSP, dataInSigned: signed(13 downto 0);
signal error15: signed(14 downto 0);
signal kiError, kpError: signed(27 downto 0);
signal kiErrorLong: signed(31 downto 0);
signal integral14: signed(13 downto 0);
signal integral15: signed(14 downto 0);
signal integral27: signed(26 downto 0);
signal integral28: signed(27 downto 0);
signal integral18: signed(17 downto 0);
signal integral19: signed(18 downto 0);
signal integrateOn: std_logic;
signal propOutAux, intOutAux, dataOutAux14, error14, kiErrorSat: signed(13 downto 0);
signal dataOutAux15: signed(14 downto 0);
signal dataSatAux: signed(27 downto 0);
signal dataSatAux: signed(19 downto 0);
signal intOutLongAux: signed(18 downto 0);
begin
KP <= kpAux;
KI <= kiAux;
LongIntOut <= std_logic_vector(integral18);
dataInSigned <= signed(DataIn);
error15 <= (resize(currentSP, error15'length) - resize(dataInSigned, error15'length))
when integrateOn='1' else (others=>'0');
-- propOutAux <= kpError(27 downto 14);
intOutAux <= kiErrorSat;
intOutLongAux <= kiErrorLong(31 downto 13);
dataOutAux15 <= resize(intOutAux, dataOutAux15'length) +
resize(propOutAux, dataOutAux15'length);
dataSatAux <= resize(integral27, dataSatAux'length) +
dataSatAux <= resize(intOutLongAux, dataSatAux'length) +
resize(propOutAux, dataSatAux'length);
DataOut <= std_logic_vector(dataOutAux14);
......@@ -114,6 +120,7 @@ Integrator: process(Clk40)
begin
if Clk40'event and Clk40='1' then
kiError <= kiSigned * integral14;
kiErrorLong <= kiSigned * integral18;
if ConfigMode='0' and RFONRising='1' then
integrateOn <= '1';
elsif RFOnFalling='1' then
......@@ -121,12 +128,12 @@ begin
end if;
if SyncReset='1' or RFOnFalling='1' then
integral15 <= (others=>'0');
integral28 <= (others=>'0');
integral19 <= (others=>'0');
elsif integrateOn='1' then
integral15 <= resize(integral14, integral15'length) +
resize(error14, integral15'length);
integral28 <= resize(integral27, integral28'length) +
resize(error14, integral28'length);
integral19 <= resize(integral18, integral19'length) +
resize(error14, integral19'length);
end if;
end if;
end process Integrator;
......@@ -142,14 +149,14 @@ begin
end if;
end process IntSaturation;
LongIntSaturation: process(integral28)
LongIntSaturation: process(integral19)
begin
if integral28 >= to_signed(67108863, integral28'length) then -- 2^26 - 1
integral27 <= to_signed(67108863, integral27'length);
elsif integral28 <= to_signed(-67108864, integral28'length) then -- -2^26
integral27 <= to_signed(-67108864, integral27'length);
if integral19 >= to_signed(131071, integral19'length) then -- 2^17 - 1
integral18 <= to_signed(131071, integral18'length);
elsif integral19 <= to_signed(-131072, integral19'length) then -- -2^17
integral18 <= to_signed(-131072, integral18'length);
else -- no saturation
integral27 <= integral28(26 downto 0);
integral18 <= integral19(17 downto 0);
end if;
end process LongIntSaturation;
......@@ -177,13 +184,7 @@ end process Sum;
SatSum: process(Clk40)
begin
if Clk40'event and Clk40='1' then
if dataSatAux >= to_signed(8388607, dataSatAux'length) then -- 2^23 - 1
DataOutSat <= std_logic_vector(to_signed(8191, DataOutSat'length));
elsif dataSatAux <= to_signed(-8388608, dataSatAux'length) then -- -2^23
DataOutSat <= std_logic_vector(to_signed(-8192, dataOutAux14'length));
else
DataOutSat <= std_logic_vector(dataSatAux(23 downto 10));
end if;
DataOutSat <= std_logic_vector(dataSatAux(19 downto 6));
end if;
end process SatSum;
......
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