Commit 6faf82e6 authored by Pablo Alvarez's avatar Pablo Alvarez Committed by Dimitris Lampridis
Browse files

Some reports added to svn

git-svn-id: https://www.ohwr.org/svn/lrfsc/trunk@3 6473569e-ccbe-4206-bb48-f381304e9851
parent 786f29c2
Release 10.1.02 par K.37 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
PCBE13042:: Tue Nov 16 16:28:51 2010
par -w -intstyle ise -ol med -t 1 CavityControlCWV3_map.ncd
CavityControlCWV3.ncd CavityControlCWV3.pcf
Constraints file: CavityControlCWV3.pcf.
Loading device for application Rf_Device from file '2v2000.nph' in environment C:\Xilinx\10.1\ISE.
"CavityControlCWV3" is an NCD, version 3.2, device xc2v2000, package fg676, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.121 2008-05-01".
Device Utilization Summary:
Number of BUFGMUXs 3 out of 16 18%
Number of DCMs 1 out of 8 12%
Number of External IOBs 438 out of 456 96%
Number of LOCed IOBs 438 out of 438 100%
Number of MULT18X18s 26 out of 56 46%
Number of SLICEs 3280 out of 10752 30%
Overall effort level (-ol): Medium
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Medium
WARNING:Par:288 - The signal VMEAM(2)_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ADSwitch(0)_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ADSwitch(1)_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ADSwitch(2)_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal ADSwitch(3)_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VMESysClk_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal CavDry_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal FwdDry_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal RefDry_IBUF has no load. PAR will not attempt to route this signal.
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:bb3710) REAL time: 5 secs
Phase 2.7
Phase 2.7 (Checksum:bb3710) REAL time: 5 secs
Phase 3.31
Phase 3.31 (Checksum:bb3710) REAL time: 5 secs
Phase 4.2
.
Phase 4.2 (Checksum:bbc6d2) REAL time: 6 secs
Phase 5.30
Phase 5.30 (Checksum:bbc6d2) REAL time: 6 secs
Phase 6.3
Phase 6.3 (Checksum:bbc6d2) REAL time: 6 secs
Phase 7.5
Phase 7.5 (Checksum:bbc6d2) REAL time: 6 secs
Phase 8.8
......................
....
..
......
..
..
Phase 8.8 (Checksum:36431d0) REAL time: 21 secs
Phase 9.5
Phase 9.5 (Checksum:36431d0) REAL time: 21 secs
Phase 10.18
Phase 10.18 (Checksum:366ba6f) REAL time: 31 secs
Phase 11.5
Phase 11.5 (Checksum:366ba6f) REAL time: 31 secs
Phase 12.27
Phase 12.27 (Checksum:366ba6f) REAL time: 32 secs
Phase 13.24
Phase 13.24 (Checksum:366ba6f) REAL time: 33 secs
REAL time consumed by placer: 33 secs
CPU time consumed by placer: 33 secs
Writing design to file CavityControlCWV3.ncd
Total REAL time to Placer completion: 33 secs
Total CPU time to Placer completion: 34 secs
Starting Router
Phase 1: 22659 unrouted; REAL time: 38 secs
Phase 2: 20234 unrouted; REAL time: 44 secs
Phase 3: 5687 unrouted; REAL time: 47 secs
Phase 4: 5687 unrouted; (812210) REAL time: 47 secs
Phase 5: 5848 unrouted; (3039) REAL time: 50 secs
Phase 6: 0 unrouted; (31004) REAL time: 56 secs
Phase 7: 0 unrouted; (31004) REAL time: 58 secs
Phase 8: 0 unrouted; (31004) REAL time: 58 secs
Phase 9: 0 unrouted; (20018) REAL time: 1 mins 2 secs
Phase 10: 0 unrouted; (19576) REAL time: 1 mins 6 secs
Phase 11: 0 unrouted; (19525) REAL time: 1 mins 9 secs
Phase 12: 0 unrouted; (19525) REAL time: 1 mins 16 secs
Phase 13: 0 unrouted; (19525) REAL time: 1 mins 16 secs
Phase 14: 0 unrouted; (19020) REAL time: 1 mins 18 secs
Total REAL time to Router completion: 1 mins 19 secs
Total CPU time to Router completion: 1 mins 20 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk80N | BUFGMUX2S| No | 108 | 0.172 | 1.490 |
+---------------------+--------------+------+------+------------+-------------+
| clk80 | BUFGMUX1P| No | 112 | 0.312 | 1.517 |
+---------------------+--------------+------+------+------------+-------------+
| clk40 | BUFGMUX0S| No | 1884 | 0.323 | 1.528 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0
INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the
post Place and Route timing report.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 17.840ns| N/A| 0
40 | HOLD | 1.214ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 6.680ns| N/A| 0
80N | HOLD | 1.391ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 14.675ns| N/A| 0
80 | HOLD | 1.356ns| | 0| 0
------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 9 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 24 secs
Total CPU time to PAR completion: 1 mins 25 secs
Peak Memory Usage: 308 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 12
Number of info messages: 3
Writing design to file CavityControlCWV3.ncd
PAR done!
vhdl work "../sources/SineCosine.vhd"
vhdl work "../sources/RegistersMap.vhd"
vhdl work "../sources/VmeIntfce.vhd"
vhdl work "../sources/VMEDecoder.vhd"
vhdl work "../sources/TimingManager.vhd"
vhdl work "../sources/Snapshots.vhd"
vhdl work "../sources/SetPoints.vhd"
vhdl work "../sources/SatControlCW.vhd"
vhdl work "../sources/ResControl.vhd"
vhdl work "../sources/RAMManager.vhd"
vhdl work "../sources/PIControllerCW.vhd"
vhdl work "../sources/OneShot.vhd"
vhdl work "../sources/mul2x2.vhd"
vhdl work "../sources/IrqControl.vhd"
vhdl work "../sources/IQModulator.vhd"
vhdl work "../sources/iqdemodcw.vhd"
vhdl work "../sources/IQCounter.vhd"
vhdl work "../sources/FeedForward.vhd"
vhdl work "../sources/Diagnostics.vhd"
vhdl work "../sources/Commands.vhd"
vhdl work "../sources/ClockManager.vhd"
vhdl work "../sources/CavityControlCWV3.vhd"
Release 10.1.02 Map K.37 (nt)
Xilinx Map Application Log File for Design 'CavityControlCWV3'
Design Information
------------------
Command Line : map -ise E:/ohr/lrfsc/trunk/hdl/ise/RFControlV4.ise -intstyle
ise -p xc2v2000-fg676-4 -cm speed -ignore_keep_hierarchy -pr b -k 4 -c 100 -tx
off -o CavityControlCWV3_map.ncd CavityControlCWV3.ngd CavityControlCWV3.pcf
Target Device : xc2v2000
Target Package : fg676
Target Speed : -4
Mapper Version : virtex2 -- $Revision: 1.46.12.2 $
Mapped Date : Tue Nov 16 16:28:37 2010
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 11
Logic Utilization:
Number of Slice Flip Flops: 3,125 out of 21,504 14%
Number of 4 input LUTs: 4,626 out of 21,504 21%
Logic Distribution:
Number of occupied Slices: 3,280 out of 10,752 30%
Number of Slices containing only related logic: 3,280 out of 3,280 100%
Number of Slices containing unrelated logic: 0 out of 3,280 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 4,849 out of 21,504 22%
Number used as logic: 4,624
Number used as a route-thru: 223
Number used as Shift registers: 2
Number of bonded IOBs: 438 out of 456 96%
IOB Flip Flops: 234
Number of MULT18X18s: 26 out of 56 46%
Number of BUFGMUXs: 3 out of 16 18%
Number of DCMs: 1 out of 8 12%
Peak Memory Usage: 240 MB
Total REAL time to MAP completion: 8 secs
Total CPU time to MAP completion: 8 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "CavityControlCWV3_map.mrp" for details.
This diff is collapsed.
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD COLSPAN='4'><B>RFControlV4 Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>RFControlV4.ise</TD>
<TD BGCOLOR='#FFFF99'><B>Current State:</B></TD>
<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>CavityControlCWV3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc2v2000-4fg676</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>575 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD>ISE 10.1.02 - Foundation Simulator</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='CavityControlCWV3.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='CavityControlCWV3.par?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD>Xilinx Default (unlocked)</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0&nbsp;<A HREF_DISABLED='CavityControlCWV3.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TBODY><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER width=90% COLSPAN='4'><B>RFControlV4 Partition Summary</B></TD><TD ALIGN=RIGHT width=10% COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PartitionSummary"><B>[-]</B></a></TD></TR></TBODY></TD></TR>
<TR BGCOLOR='#FFFF99'><TD COLSPAN='5'><B>No partition information was found.</B></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TBODY><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER width=90% COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT width=10% COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR></TBODY></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>3,125</TD>
<TD ALIGN=RIGHT>21,504</TD>
<TD ALIGN=RIGHT>14%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>4,626</TD>
<TD ALIGN=RIGHT>21,504</TD>
<TD ALIGN=RIGHT>21%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>3,280</TD>
<TD ALIGN=RIGHT>10,752</TD>
<TD ALIGN=RIGHT>30%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>3,280</TD>
<TD ALIGN=RIGHT>3,280</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>3,280</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number of 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>4,849</TD>
<TD ALIGN=RIGHT>21,504</TD>
<TD ALIGN=RIGHT>22%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>4,624</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as a route-thru</TD>
<TD ALIGN=RIGHT>223</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift registers</TD>
<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='CavityControlCWV3_map.mrp?&DataKey=IOBProperties'>IOBs</A></TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded </TD>
<TD ALIGN=RIGHT>438</TD>
<TD ALIGN=RIGHT>456</TD>
<TD ALIGN=RIGHT>96%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
<TD ALIGN=RIGHT>234</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MULT18X18s</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>56</TD>
<TD ALIGN=RIGHT>46%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>18%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCMs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>12%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TBODY><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER width=90% COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT width=10% COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR></TBODY></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='CavityControlCWV3.pad?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD>
<TD>
<A HREF_DISABLED='CavityControlCWV3.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='CavityControlCWV3.par?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='CavityControlCWV3.par?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TBODY><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER width=90% COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT width=10% COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR></TBODY></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:28:26 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>418 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/xst.xmsgs'>127 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:28:34 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/ngdbuild.xmsgs'>134 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:28:49 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>11 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/map.xmsgs'>112 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:30:17 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>12 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/par.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:30:25 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/trce.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:30:50 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>9 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>1 Info</A></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 11/16/2010 - 16:39:47</center>
</BODY></HTML>
\ No newline at end of file
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\SineCosine.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\RegistersMap.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\VmeIntfce.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\VMEDecoder.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\TimingManager.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\Snapshots.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\SetPoints.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\SatControlCW.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\ResControl.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\RAMManager.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\PIControllerCW.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\OneShot.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\mul2x2.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\IrqControl.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\IQModulator.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\iqdemodcw.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\IQCounter.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\FeedForward.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\Diagnostics.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\Commands.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\ClockManager.vhd"
vhdl work "E:\ohr\lrfsc\trunk\hdl\sources\CavityControlCWV3.vhd"
No preview for this file type
......@@ -412,7 +412,7 @@ proc set_process_props {} {
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
project set "Keep Hierarchy" "Yes" -process "Synthesize - XST"
project set "Register Balancing" "No" -process "Synthesize - XST"
project set "Register Duplication" "true" -process "Synthesize - XST"
project set "Register Duplication" "false" -process "Synthesize - XST"
project set "Tri-state Buffer Transformation Mode" "Off" -process "Map"
project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
......@@ -420,7 +420,7 @@ proc set_process_props {} {
project set "Bus Delimiter" "()" -process "Synthesize - XST"
project set "Case" "Maintain" -process "Synthesize - XST"
project set "Cores Search Directories" "" -process "Synthesize - XST"
project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
project set "Cross Clock Analysis" "true" -process "Synthesize - XST"
project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
project set "FSM Style" "LUT" -process "Synthesize - XST"
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
......@@ -455,9 +455,9 @@ proc set_process_props {} {
project set "RAM Style" "Auto" -process "Synthesize - XST"
project set "Encrypt Bitstream" "false" -process "Generate Programming File"
project set "Timing Mode" "Non Timing Driven" -process "Map"
project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
project set "Generate Clock Region Report" "false" -process "Place & Route"
project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
project set "Generate Asynchronous Delay Report" "true" -process "Place & Route"
project set "Generate Clock Region Report" "true" -process "Place & Route"
project set "Generate Post-Place & Route Simulation Model" "true" -process "Place & Route"
project set "Generate Post-Place & Route Static Timing Report" "true" -process "Place & Route"
project set "Nodelist File (Unix Only)" "" -process "Place & Route"
project set "Number of PAR Iterations (0-100)" "3" -process "Place & Route"
......
WARNING:PhysDesignRules:367 - The signal <VMEAM(2)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ADSwitch(0)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ADSwitch(1)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ADSwitch(2)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ADSwitch(3)_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VMESysClk_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <CavDry_IBUF> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <FwdDry_IBUF> is incomplete. The signal
does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <RefDry_IBUF> is incomplete. The signal
does not drive any load pins in the design.
DRC detected 0 errors and 9 warnings. Please see the previously displayed
individual error or warning messages for more details.
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