Commit 842eb0c6 authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@1245 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent 553de2b7
......@@ -42,16 +42,16 @@ signal rmPendingData: std_logic_vector(15 downto 0);
signal rmPendingWrite, rmPendingRead: std_logic;
signal ramAddrAux: unsigned(17 downto 0);
signal spCounter: unsigned(4 downto 0);
signal signedSPCounter: signed(13 downto 0);
signal iAuxH, iAuxL, qAuxH, qAuxL: std_logic_vector(15 downto 0);
signal iAuxn, qAuxn, iAuxnp1, qAuxnp1: signed(13 downto 0); -- I(n), Q(n), I(n+1), Q(n+1)
signal iCurrent, qCurrent: signed(13 downto 0);
signal bigStepI, bigStepQ: signed(13 downto 0);
signal smallStepI, smallStepQ: signed(13 downto 0);
signal incrementI, incrementQ: signed(13 downto 0);
signal iOutAux, qOutAux: signed(13 downto 0);
signal iAuxn, qAuxn: signed(29 downto 0);
signal iCurrent, qCurrent: signed(29 downto 0);
signal bigStepI, bigStepQ: signed(29 downto 0);
signal smallStepI, smallStepQ: signed(29 downto 0);
signal incrementI, incrementQ: signed(29 downto 0);
signal iOutAux, qOutAux: signed(29 downto 0);
signal presCycleAux: std_logic_vector(4 downto 0);
signal xn, xnAux: unsigned(15 downto 0);
signal nextAddr: std_logic_vector(12 downto 0);
begin
......@@ -60,16 +60,26 @@ ramDataIn <= RAMData;
-- RAMCS <= '0';
RAMAddress <= std_logic_vector(ramAddrAux);
smallStepI <= bigStepI(13) & bigStepI(13) & bigStepI(13) &
bigStepI(13) & bigStepI(13) & bigStepI(13 downto 5);
smallStepQ <= bigStepQ(13) & bigStepQ(13) & bigStepQ(13) &
bigStepQ(13) & bigStepQ(13) & bigStepQ(13 downto 5);
signedSPCounter <= signed("000000000" & spCounter);
incrementI <= (signedSPCounter * smallStepI) (13 downto 0);
incrementQ <= (signedSPCounter * smallStepQ) (13 downto 0);
smallStepI <= bigStepI(29) & bigStepI(29) & bigStepI(29) &
bigStepI(29) & bigStepI(29) & bigStepI(29 downto 5);
smallStepQ <= bigStepQ(29) & bigStepQ(29) & bigStepQ(29) &
bigStepQ(29) & bigStepQ(29) & bigStepQ(29 downto 5);
IDataToProcess <= std_logic_vector(iOutAux(13) & iOutAux(13) & iOutAux);
QDataToProcess <= std_logic_vector(qOutAux(13) & qOutAux(13) & qOutAux);
incProcess: process(Clk40)
begin
if Clk40'event and Clk40='1' then
if spCounter=to_unsigned(31, spCounter'length) then
incrementI <= (others=>'0');
incrementQ <= (others=>'0');
else
incrementI <= incrementI + smallStepI;
incrementQ <= incrementQ + smallStepQ;
end if;
end if;
end process incProcess;
IDataToProcess <= std_logic_vector(iOutAux(29) & iOutAux(29) & iOutAux(29 downto 16));
QDataToProcess <= std_logic_vector(qOutAux(29) & qOutAux(29) & qOutAux(29 downto 16));
PendingRM: process(Clk40)
......@@ -171,8 +181,6 @@ begin
writing <= '0';
iAuxn <= (others=>'0');
qAuxn <= (others=>'0');
iAuxnp1 <= (others=>'0');
qAuxnp1 <= (others=>'0');
iCurrent <= (others=>'0');
qCurrent <= (others=>'0');
bigStepI <= (others=>'0');
......@@ -185,6 +193,7 @@ begin
iAuxL <= (others=>'0');
qAuxH <= (others=>'0');
qAuxL <= (others=>'0');
nextAddr <= (others=>'0');
if configMode='0' and RFONRising='1' then
RAMOE <= '0';
RAMCS <= '0';
......@@ -220,43 +229,50 @@ begin
DataToProcessValid <= '1';
iOutAux <= iCurrent + incrementI;
qOutAux <= qCurrent + incrementQ;
if xn=to_unsigned(0, xn'length) and
(spCounter=to_unsigned(5, spCounter'length) or
spCounter=to_unsigned(10, spCounter'length) or
spCounter=to_unsigned(15, spCounter'length) or
spCounter=to_unsigned(20, spCounter'length) or
spCounter=to_unsigned(25, spCounter'length)) then
ramAddrAux <= (unsigned(presCycleAux)) & ((ramAddrAux + 1)(12 downto 0));
if xn=to_unsigned(0, xn'length) then
if
(spCounter=to_unsigned(4, spCounter'length) or
spCounter=to_unsigned(8, spCounter'length) or
spCounter=to_unsigned(12, spCounter'length) or
spCounter=to_unsigned(16, spCounter'length) or
spCounter=to_unsigned(22, spCounter'length)) then
ramAddrAux <= (unsigned(presCycleAux)) & ((ramAddrAux + 1)(12 downto 0));
elsif spCounter=to_unsigned(26, spCounter'length) then
ramAddrAux <= unsigned(presCycleAux & nextAddr);
end if;
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(6, spCounter'length) then
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(6, spCounter'length) then
nextAddr <= ramDataInC(12 downto 0);
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(10, spCounter'length) then
xnAux <= unsigned(ramDataInC);
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(11, spCounter'length) then
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(14, spCounter'length) then
iAuxH <= ramDataInC;
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(16, spCounter'length) then
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(18, spCounter'length) then
iAuxL <= ramDataInC;
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(21, spCounter'length) then
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(24, spCounter'length) then
qAuxH <= ramDataInC;
end if;
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(26, spCounter'length) then
if xn=to_unsigned(0, xn'length) and spCounter=to_unsigned(28, spCounter'length) then
qAuxL <= ramDataInC;
end if;
if spCounter=to_unsigned(31, spCounter'length) then
if xn=to_unsigned(0, xn'length) then
xn <= xnAux - 1;
else
xn <= xn - 1;
end if;
iAuxn <= signed(iAuxH(13 downto 0));
qAuxn <= signed(qAuxH(13 downto 0));
iAuxn <= signed(iAuxH(13 downto 0) & iAuxL);
qAuxn <= signed(qAuxH(13 downto 0) & qAuxL);
iCurrent <= iCurrent + iAuxn;
qCurrent <= qCurrent + qAuxn;
bigStepI <= signed(iAuxH(13 downto 0));
bigStepQ <= signed(qAuxH(13 downto 0));
bigStepI <= signed(iAuxH(13 downto 0) & iAuxL);
bigStepQ <= signed(qAuxH(13 downto 0) & qAuxL);
end if;
when others =>
writing <= '0';
......
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