Commit 8d0cf41c authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@748 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent 0ec6853f
......@@ -328,17 +328,18 @@ COMPONENT picontrollercw
RFONRising : IN std_logic;
RFONFalling : IN std_logic;
CWMode: in std_logic;
AntiWindUp: in std_logic;
ConfigMode : IN std_logic;
DataIn : IN std_logic_vector(13 downto 0);
SetPoints : IN std_logic_vector(13 downto 0);
SetPointsValid : IN std_logic;
DataOut : OUT std_logic_vector(13 downto 0);
DataOutSat: out std_logic_vector(13 downto 0);
DataOutSat: out std_logic_vector(28 downto 0);
KP : OUT std_logic_vector(15 downto 0);
KI : OUT std_logic_vector(15 downto 0);
PropOut : OUT std_logic_vector(13 downto 0);
IntOut : OUT std_logic_vector(13 downto 0);
LongIntOut: out std_logic_vector(17 downto 0);
LongIntOut: out std_logic_vector(26 downto 0);
ErrorOut : OUT std_logic_vector(13 downto 0)
);
END COMPONENT;
......@@ -506,13 +507,13 @@ COMPONENT commands
);
END COMPONENT;
COMPONENT satcontrol
COMPONENT satcontrolcw
PORT(
Clk : IN std_logic;
IDataIn : IN std_logic_vector(13 downto 0);
QDataIn : IN std_logic_vector(13 downto 0);
ISatIn : IN std_logic_vector(13 downto 0);
QSatIn : IN std_logic_vector(13 downto 0);
ISatIn : IN std_logic_vector(28 downto 0);
QSatIn : IN std_logic_vector(28 downto 0);
Saturated : OUT std_logic;
Iout : OUT std_logic_vector(13 downto 0);
Qout : OUT std_logic_vector(13 downto 0)
......@@ -536,7 +537,8 @@ signal lock40Int : std_logic;
signal iqCount: std_logic_vector(1 downto 0);
signal refI, refQ, fwdI, fwdQ, cavI, cavQ: std_logic_vector(13 downto 0);
signal refIR, refQR, fwdIR, fwdQR, cavIR, cavQR: std_logic_vector(13 downto 0);
signal cavIC, cavQC, cavISat, cavQSat: std_logic_vector(13 downto 0);
signal cavIC, cavQC: std_logic_vector(13 downto 0);
signal cavISat, cavQSat: std_logic_vector(28 downto 0);
signal resetA: std_logic;
signal vmeIntReqAux: std_logic_vector(7 downto 1);
signal vmeAMAux: std_logic_vector(4 downto 0);
......@@ -571,12 +573,13 @@ signal saturated, badlySaturated: std_logic;
signal cavIFixed, cavQFixed: std_logic_vector(13 downto 0);
signal cavIToMod, cavQToMod: std_logic_vector(13 downto 0);
signal satDisabled: std_logic;
signal cavILongInt, cavQLongInt: std_logic_vector(17 downto 0);
signal cwMode: std_logic;
signal cavILongInt, cavQLongInt: std_logic_vector(26 downto 0);
signal cwMode, antiWindUp: std_logic;
begin
cwMode <= ADSwitch(0);
antiWindUp <= ADSwitch(1);
RAM1Addr <= ram1AddrAux;
RAM1OE <= ram1OEAux;
......@@ -1012,6 +1015,7 @@ I_picontroller: picontrollercw PORT MAP(
RFONRising => rfOnRising,
RFONFalling => rfOnFalling,
CWMode => cwMode,
AntiWindUp => antiWindUp,
ConfigMode => configMode,
DataIn => cavIR,
SetPoints => spIDataToPI(13 downto 0),
......@@ -1035,6 +1039,7 @@ Q_picontroller: picontrollercw PORT MAP(
RFONRising => rfOnRising,
RFONFalling => rfOnFalling,
CWMode => cwMode,
AntiWindUp => antiWindUp,
ConfigMode => configMode,
DataIn => cavQR,
SetPoints => spQDataToPI(13 downto 0),
......@@ -1049,7 +1054,7 @@ Q_picontroller: picontrollercw PORT MAP(
ErrorOut => cavQErr
);
U0_satcontrol: satcontrol PORT MAP(
U0_satcontrol: satcontrolcw PORT MAP(
Clk => clk40,
IDataIn => cavIC,
QDataIn => cavQC,
......@@ -1106,10 +1111,10 @@ U2_oneshot: oneshot PORT MAP(
PulseOut => RefLed
);
badlySaturated <= '1' when (cavILongInt="011111111111111111" or
cavILongInt="100000000000000000" or
cavQLongInt="011111111111111111" or
cavQLongInt="100000000000000000") else '0';
badlySaturated <= '1' when (cavILongInt="011111111111111111111111111" or
cavILongInt="100000000000000000000000000" or
cavQLongInt="011111111111111111111111111" or
cavQLongInt="100000000000000000000000000") else '0';
SwControl <= registers(SWCTRLR)(2) & registers(SWCTRLR)(1) &
registers(SWCTRLR)(0) & registers(SWCTRLR)(3);
......
......@@ -11,6 +11,7 @@ entity PIControllerCW is
RFONRising : in std_logic;
RFONFalling : in std_logic;
CWMode: in std_logic;
AntiWindUp: in std_logic;
ConfigMode : in std_logic;
DataIn : in std_logic_vector(13 downto 0);
SetPoints : in std_logic_vector(13 downto 0);
......@@ -46,6 +47,7 @@ signal dataSatAux: signed(28 downto 0);
signal intOutLongAux: signed(27 downto 0);
signal propOutLongAux: signed(21 downto 0);
signal intHigh, intLow: signed(13 downto 0);
signal intSaturated: std_logic;
begin
......@@ -75,6 +77,10 @@ dataSatAux <= resize(intOutLongAux, dataSatAux'length) +
DataOut <= std_logic_vector(dataOutAux14);
integral14 <= integral27(26 downto 13);
intSaturated <= '1' when ((kiErrorSat = to_signed(8191, kiErrorSat'length) and error14(13)='0') or
(kiErrorSat = to_signed(-8192, kiErrorSat'length) and error14(13)='1'))
else '0';
PropOutProcess: process(kpError)
begin
if kpError >= to_signed(524287, kpError'length) then
......@@ -143,7 +149,8 @@ begin
if SyncReset='1' or (RFOnFalling='1' and CWMode='0') then
integral28 <= (others=>'0');
integral19 <= (others=>'0');
elsif integrateOn='1' then
elsif (integrateOn='1' and AntiWindUp='0') or
(integrateOn='1' and AntiWindUp='1' and intSaturated='0')then
integral28 <= resize(integral27, integral28'length) +
resize(error14, integral28'length);
integral19 <= resize(integral18, integral19'length) +
......
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SatControlCW is
Port ( Clk : in std_logic;
IDataIn : in std_logic_vector(13 downto 0);
QDataIn : in std_logic_vector(13 downto 0);
ISatIn : in std_logic_vector(28 downto 0);
QSatIn : in std_logic_vector(28 downto 0);
Saturated : out std_logic;
Iout : out std_logic_vector(13 downto 0);
Qout : out std_logic_vector(13 downto 0));
end SatControlCW;
architecture RTL of SatControlCW is
signal iSquared, qSquared: signed(27 downto 0);
signal moduleSquared: signed(28 downto 0);
signal iSatAbs, qSatAbs: signed(28 downto 0);
signal ix1, ix2, ix3, ix8: signed(31 downto 0);
signal ix3Aux: signed(57 downto 0);
signal qx1, qx2, qx3, qx8: signed(31 downto 0);
signal qx3Aux: signed(57 downto 0);
signal iOutAux, qOutAux: signed(13 downto 0);
signal iSign, qSign: std_logic;
begin
iSquared <= signed(IDataIn) * signed(IDataIn);
qSquared <= signed(QDataIn) * signed(QDataIn);
iSatAbs <= -signed(ISatIn) when ISatIn(28)='1' else signed(ISatIn);
qSatAbs <= -signed(QSatIn) when QSatIn(28)='1' else signed(QSatIn);
ix3Aux <= iSatAbs * to_signed(3, iSatAbs'length);
qx3Aux <= qSatAbs * to_signed(3, qSatAbs'length);
Iout <= std_logic_vector(iOutAux);
Qout <= std_logic_vector(qOutAux);
FirstStage: process(Clk)
begin
if Clk'event and Clk='1' then
moduleSquared <= resize(iSquared, moduleSquared'length) + resize(qSquared, moduleSquared'length);
ix1 <= "000" & iSatAbs;
ix2 <= "00" & iSatAbs & "0";
ix3 <= ix3Aux(31 downto 0);
ix8 <= iSatAbs & "000";
qx1 <= "000" & qSatAbs;
qx2 <= "00" & qSatAbs & "0";
qx3 <= qx3Aux(31 downto 0);
qx8 <= qSatAbs & "000";
iSign <= ISatIn(28);
qSign <= QSatIn(28);
end if;
end process FirstStage;
SecondStage: process(Clk)
begin
if Clk'event and Clk='1' then
if (ix1 > to_signed(8191, ix1'length)) or (qx1 > to_signed(8191, ix1'length)) then
Saturated <= '1';
else
Saturated <= '0';
end if;
if (ix1 >= qx8) then
if iSign='0' then
iOutAux <= to_signed(8191, iOutAux'length);
else
iOutAux <= to_signed(-8191, iOutAux'length);
end if;
qOutAux <= (others=>'0');
elsif (qx8 > ix1) and (ix1 >= qx3) then
if iSign='0' then
iOutAux <= to_signed(7946, iOutAux'length);
else
iOutAux <= to_signed(-7946, iOutAux'length);
end if;
if qSign='0' then
qOutAux <= to_signed(1986, iOutAux'length);
else
qOutAux <= to_signed(-1986, iOutAux'length);
end if;
elsif (qx3 > ix1) and (ix2 >= qx3) then
if iSign='0' then
iOutAux <= to_signed(7326, iOutAux'length);
else
iOutAux <= to_signed(-7326, iOutAux'length);
end if;
if qSign='0' then
qOutAux <= to_signed(3663, iOutAux'length);
else
qOutAux <= to_signed(-3663, iOutAux'length);
end if;
elsif (qx3 > ix2) and (ix3 >= qx2) then
if iSign='0' then
iOutAux <= to_signed(5791, iOutAux'length);
else
iOutAux <= to_signed(-5791, iOutAux'length);
end if;
if qSign='0' then
qOutAux <= to_signed(5791, iOutAux'length);
else
qOutAux <= to_signed(-5791, iOutAux'length);
end if;
elsif (qx2 > ix3) and (ix3 >= qx1) then
if iSign='0' then
iOutAux <= to_signed(3663, iOutAux'length);
else
iOutAux <= to_signed(-3663, iOutAux'length);
end if;
if qSign='0' then
qOutAux <= to_signed(7326, iOutAux'length);
else
qOutAux <= to_signed(-7326, iOutAux'length);
end if;
elsif (qx1 > ix3) and (ix8 >= qx1) then
if iSign='0' then
iOutAux <= to_signed(1986, iOutAux'length);
else
iOutAux <= to_signed(-1986, iOutAux'length);
end if;
if qSign='0' then
qOutAux <= to_signed(7946, iOutAux'length);
else
qOutAux <= to_signed(-7946, iOutAux'length);
end if;
else -- (qx1 > ix8)
iOutAux <= (others=>'0');
if qSign='0' then
qOutAux <= to_signed(8191, iOutAux'length);
else
qOutAux <= to_signed(-8191, iOutAux'length);
end if;
end if;
end if;
end process SecondStage;
end RTL;
......@@ -40,19 +40,23 @@ SOURCE ..\sources\FeedForward.vhd
SOURCE ..\sources\Diagnostics.vhd
SOURCE ..\sources\SatControl.vhd
SOURCE ..\sources\OneShot.vhd
SOURCE ..\sources\CavityControlCW.vhd
SOURCE ..\sources\PIControllerCW.vhd
SOURCE ..\sources\SatControlCW.vhd
DEPASSOC ledstest ..\sources\ledsconstraints.ucf
DEPASSOC cavitycontrol ..\sources\cavityconstraints.ucf
DEPASSOC cavitycontrolcw ..\sources\cavityCWconstraints.ucf
[Normal]
p_AutoGenFile=synvhd, virtex2, VHDL.t_genImpactFile, 1068747285, True
p_ChainDescFile=synvhd, virtex2, VHDL.t_genImpactFile, 1068747285, C:\FPGADesigns\RFControl\xilinx\llcc.cdf
xilxMapCoverMode=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1070037511, Speed
xilxMapPackRegInto=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1051284026, For Inputs and Outputs
xilxMapReportDetail=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1070037511, False
xilxPAReffortLevel=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1049383307, Medium
p_AutoGenFile=synvhd, virtex2, Implementation.t_genImpactFile, 1068747285, True
p_ChainDescFile=synvhd, virtex2, Implementation.t_genImpactFile, 1087824130,
xilxMapCoverMode=synvhd, virtex2, Implementation.t_map, 1070037511, Speed
xilxMapPackRegInto=synvhd, virtex2, Implementation.t_map, 1051284026, For Inputs and Outputs
xilxMapReportDetail=synvhd, virtex2, Implementation.t_map, 1070037511, False
xilxPAReffortLevel=synvhd, virtex2, Implementation.t_par, 1049383307, Medium
_SynthFrequency=synvhd, virtex2, Synthesis.t_synthesize, 1049879617, 40
_SynthResourceSharing=synvhd, virtex2, Synthesis.t_synthesize, 1070036051, True
[STATUS-ALL]
cavitycontrol.ncdFile=WARNINGS,1078926644
cavitycontrol.ngdFile=WARNINGS,1078926574
cavitycontrolcw.ncdFile=WARNINGS,1088154539
cavitycontrolcw.ngdFile=WARNINGS,1088154450
[STRATEGY-LIST]
Normal=True
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