Commit c9ba7192 authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@825 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent e4422017
......@@ -581,12 +581,14 @@ signal cavIToMod, cavQToMod: std_logic_vector(13 downto 0);
signal satDisabled: std_logic;
signal cavILongInt, cavQLongInt: std_logic_vector(26 downto 0);
signal cwMode, antiWindUp, correctOn: std_logic;
signal irqReset: std_logic;
begin
cwMode <= ADSwitch(0);
antiWindUp <= ADSwitch(1);
correctOn <= ADSwitch(2);
irqReset <= resetA or syncReset;
RAM1Addr <= ram1AddrAux;
RAM1OE <= ram1OEAux;
......@@ -849,7 +851,7 @@ U0_irqcontrol: irqcontrol PORT MAP(
Clk => clk40,
IrqEnable => not configMode,
RFOn => RfOn,
Reset => resetA or syncReset,
Reset => irqReset,
WriteVMEIRQR => writeRegs(VMEIRQR),
DataFromDecoder => dataFromDecoder,
VMEIRQR => registers(VMEIRQR),
......@@ -975,7 +977,7 @@ Ref_mul2x2: mul2x2 PORT MAP(
QFactorB => registers(REFMATRIXDR),
DataFromDecoder => dataFromDecoder,
Clk40 => clk40,
Reset => resetA or syncReset,
Reset => irqReset,
IDataOut => refIR,
QDataOut => refQR
);
......@@ -993,7 +995,7 @@ Fwd_mul2x2: mul2x2 PORT MAP(
QFactorB => registers(FWDMATRIXDR),
DataFromDecoder => dataFromDecoder,
Clk40 => clk40,
Reset => resetA or syncReset,
Reset => irqReset,
IDataOut => fwdIR,
QDataOut => fwdQR
);
......@@ -1011,7 +1013,7 @@ Cav_mul2x2: mul2x2 PORT MAP(
QFactorB => registers(CAVMATRIXDR),
DataFromDecoder => dataFromDecoder,
Clk40 => clk40,
Reset => resetA or syncReset,
Reset => irqReset,
IDataOut => cavIR,
QDataOut => cavQR
);
......@@ -1091,7 +1093,7 @@ U0_iqmodulator: iqmodulator PORT MAP(
);
U0_rescontrol: rescontrol PORT MAP(
Reset => resetA or syncReset,
Reset => irqReset,
Clk40 => clk40,
WriteResCtrl => writeRegs(RESCTRLR),
DataFromDecoder => dataFromDecoder,
......
......@@ -90,7 +90,7 @@ attribute CLK_FEEDBACK of U0_DCM: label is "1X";
attribute STARTUP_WAIT of U0_DCM: label is "FALSE";
--attribute CLKFX_MULTIPLY of U0_DCM: label is 3;
--attribute CLKFX_DIVIDE of U0_DCM: label is 1;
attribute CLKIN_PERIOD of U0_DCM: label is "25 ns";
attribute CLKIN_PERIOD of U0_DCM: label is "25";
--
......
......@@ -60,7 +60,7 @@ end Diagnostics;
architecture RTL of Diagnostics is
type StateType is (Idle, ReadRAM, ReadRAMDone, ReadyForPulse, IToDAC, QToDac);
type StateType is (Idle, ReadRAM, ReadRAMWaiting, ReadRAMDone, ReadyForPulse, IToDAC, QToDac);
signal currentState, nextState: StateType;
signal diag1SelAux, diag2SelAux, diag3SelAux, diag4SelAux: std_logic_vector(15 downto 0);
......@@ -77,7 +77,6 @@ signal ramWE: std_logic;
signal ramAddrAux: unsigned(17 downto 0);
signal rmPendingAddr: std_logic_vector(17 downto 0);
signal pendingRead1, pendingRead2, pendingRead3, pendingRead4: std_logic;
signal counter: unsigned(1 downto 0);
signal iqSel1Aux, iqSel2Aux, iqSel3Aux, iqSel4Aux: std_logic;
attribute syn_keep : boolean;signal and_out, keep1, keep2: bit;attribute syn_keep of keep1, keep2 : signal is true;
......@@ -166,6 +165,8 @@ begin
nextState <= Idle;
end if;
when ReadRAM =>
nextState <= ReadRAMWaiting;
when ReadRAMWaiting =>
nextState <= ReadRAMDone;
when ReadRAMDone =>
nextState <= Idle;
......@@ -211,7 +212,6 @@ begin
dataToRAM2Aux <= X"0200";
dataToRAM3Aux <= X"0200";
dataToRAM4Aux <= X"0200";
counter <= (others=>'0');
when ReadRAM =>
writing <= '0';
ramAddrAux <= unsigned(rmPendingAddr);
......@@ -243,34 +243,16 @@ begin
dataToRAM2Aux <= "000000" & not(diag2I(13)) & diag2I(12 downto 4);
dataToRAM3Aux <= "000000" & not(diag3I(13)) & diag3I(12 downto 4);
dataToRAM4Aux <= "000000" & not(diag4I(13)) & diag4I(12 downto 4);
if counter="10" then
counter <= "00";
ramAddrAux <= ramAddrAux + 1;
else
counter <= counter + 1;
end if;
if counter="00" then
ramWE <= '0';
else
ramWE <= '1';
end if;
ramAddrAux <= ramAddrAux + 1;
ramWE <= '0';
when QToDAC =>
iqSelAux <= '1';
dataToRAM1Aux <= "000000" & not(diag1Q(13)) & diag1Q(12 downto 4);
dataToRAM2Aux <= "000000" & not(diag2Q(13)) & diag2Q(12 downto 4);
dataToRAM3Aux <= "000000" & not(diag3Q(13)) & diag3Q(12 downto 4);
dataToRAM4Aux <= "000000" & not(diag4Q(13)) & diag4Q(12 downto 4);
if counter="10" then
counter <= "00";
ramAddrAux <= ramAddrAux + 1;
else
counter <= counter + 1;
end if;
if counter="00" then
ramWE <= '0';
else
ramWE <= '1';
end if;
ramAddrAux <= ramAddrAux + 1;
ramWE <= '0';
when others =>
writing <= '0';
ramWE <= '1';
......
......@@ -31,7 +31,7 @@ end SetPoints;
architecture RTL of SetPoints is
type StateType is (Idle, rmRead, rmDataValid, rmWrite, rmWriteDone, rfOnRead);
type StateType is (Idle, rmRead, rmReadWaiting, rmDataValid, rmWrite, rmWriteDone, rfOnRead);
signal currentState, nextState: StateType;
signal ramDataIn, ramDataInC, ramDataOut: std_logic_vector(15 downto 0);
......@@ -45,7 +45,7 @@ begin
RAMData <= ramDataOut when writing='1' else (others=>'Z');
ramDataIn <= RAMData;
RAMCS <= '0';
-- RAMCS <= '0';
RAMAddress <= std_logic_vector(ramAddrAux);
PendingRM: process(Clk40)
......@@ -93,6 +93,8 @@ begin
nextState <= Idle;
end if;
when rmRead =>
nextState <= rmReadWaiting;
when rmReadWaiting =>
nextState <= rmDataValid;
when rmDataValid =>
nextState <= Idle;
......@@ -119,8 +121,10 @@ begin
writing <= '0';
if configMode='0' and RFONRising='1' then
RAMOE <= '0';
RAMCS <= '0';
else
RAMOE <= '1';
RAMCS <= '1';
end if;
RAMWE <= '1';
DataToRMValid <= '0';
......@@ -131,6 +135,7 @@ begin
when rmRead =>
ramAddrAux <= unsigned(rmPendingAddr);
RAMOE <= '0';
RAMCS <= '0';
when rmDataValid =>
DataToRM <= ramDataIn;
DataToRMValid <= '1';
......@@ -139,8 +144,10 @@ begin
ramDataOut <= rmPendingData;
writing <= '1';
RAMWE <= '0';
RAMCS <= '0';
when rmWriteDone =>
RAMWE <= '1';
RAMCS <= '1';
when rfOnRead =>
ramAddrAux <= ramAddrAux + 1;
if ramAddrAux(0)='1' then
......@@ -158,6 +165,7 @@ begin
writing <= '0';
RAMOE <= '1';
RAMWE <= '1';
RAMCS <= '1';
DataToRMValid <= '0';
end case;
ramDataInC <= ramDataIn;
......
......@@ -157,13 +157,13 @@ INST "RFDAC2(10)" TNM = "RFDACPads";
INST "RFDAC2(11)" TNM = "RFDACPads";
INST "RFDAC2(12)" TNM = "RFDACPads";
INST "RFDAC2(13)" TNM = "RFDACPads";
TIMEGRP "RFDACPads" OFFSET = OUT 1 ns AFTER "Clk40In" ;
TIMEGRP "RFDACPads" OFFSET = OUT 1.25 ns AFTER "Clk40In" ;
NET "ADSwitch(2)" LOC = "R26";
NET "ADSwitch(3)" LOC = "R25";
NET "VMESysClk" LOC = "H14";
TIMESPEC "TS_InputSetup" = FROM "InPads" TO "InFFs" 1.5 ns;
INST "Clk20In" TNM = "Clk20InPad";
TIMEGRP "Clk20InPad" OFFSET = IN 1 ns BEFORE "Clk40In" ;
TIMEGRP "Clk20InPad" OFFSET = IN 2 ns BEFORE "Clk40In" ;
INST "RAM7Data(0)" TNM = "RAMDataPads";
INST "RAM7Data(1)" TNM = "RAMDataPads";
INST "RAM7Data(2)" TNM = "RAMDataPads";
......
JedecChain;
FileRevision(JESDxxA);
/* NoviceMode */
/* Active Mode PFF */
/* Mode BS */
/* Mode SS */
/* Mode SM */
/* Mode BSFILE */
/* Mode HW140 */
/* Supermode FileMode */
/* ConfigDevice PFF "xcf08p" 0 0 */
/* PromDevice "xcf08p" 1048576 */
/* Serial */
/* ConfigDevicePath ("c:\fpgadesigns\rfcontrol\xilinx/") */
/* Format mcs */
/* FillValue FF */
/* BitSwap FALSE */
/* LoadDirection UP */
/* Collection "cavitycontrolcwv3" */
/* Version 0 "0" */
/* ConcurrentChain 0 */
P ActionCode(Cfg)
Device
PartName(xc2v2000)
File("C:\FPGADesigns\RFControl\xilinx\cavitycontrolcwv3.bit")
;
ChainEnd;
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