Commit cfafe302 authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@833 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent c9ba7192
......@@ -6,10 +6,10 @@
library IEEE;
use IEEE.std_logic_1164.all;
--
-- synopsys translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synopsys translate_on
-- bla synopsys translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- bla synopsys translate_on
--
entity ClockManager is
port (
......@@ -26,71 +26,71 @@ architecture RTL of ClockManager is
--
-- Components Declarations:
--
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
--component BUFG
-- port (
-- I : in std_logic;
-- O : out std_logic
-- );
--end component;
--
component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
--component IBUFG
-- port (
-- I : in std_logic;
-- O : out std_logic
-- );
--end component;
--
component DCM
--component DCM
-- synopsys translate_off
generic (
DLL_FREQUENCY_MODE : string := "LOW";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
CLK_FEEDBACK : string := "2X";
CLKFX_MULTIPLY : integer := 5 ;
CLKFX_DIVIDE : integer := 2;
STARTUP_WAIT : boolean := FALSE
-- generic (
-- DLL_FREQUENCY_MODE : string := "LOW";
-- DUTY_CYCLE_CORRECTION : boolean := TRUE;
-- CLK_FEEDBACK : string := "2X";
-- CLKFX_MULTIPLY : integer := 5 ;
-- CLKFX_DIVIDE : integer := 2;
-- STARTUP_WAIT : boolean := FALSE
);
-- synopsys translate_on
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector(7 downto 0)
);
end component;
--
-- port ( CLKIN : in std_logic;
-- CLKFB : in std_logic;
-- DSSEN : in std_logic;
-- PSINCDEC : in std_logic;
-- PSEN : in std_logic;
-- PSCLK : in std_logic;
-- RST : in std_logic;
-- CLK0 : out std_logic;
-- CLK90 : out std_logic;
-- CLK180 : out std_logic;
-- CLK270 : out std_logic;
-- CLK2X : out std_logic;
-- CLK2X180 : out std_logic;
-- CLKDV : out std_logic;
-- CLKFX : out std_logic;
-- CLKFX180 : out std_logic;
-- LOCKED : out std_logic;
-- PSDONE : out std_logic;
-- STATUS : out std_logic_vector(7 downto 0)
-- );
--end component;
--
-- Attributes
attribute DLL_FREQUENCY_MODE : string;
attribute DUTY_CYCLE_CORRECTION : string;
attribute CLK_FEEDBACK : string;
attribute STARTUP_WAIT : string;
attribute CLKFX_MULTIPLY : integer;
attribute CLKFX_DIVIDE : integer;
attribute CLKIN_PERIOD: string;
attribute DLL_FREQUENCY_MODE of U0_DCM: label is "LOW";
attribute DUTY_CYCLE_CORRECTION of U0_DCM: label is "TRUE";
attribute CLK_FEEDBACK of U0_DCM: label is "1X";
attribute STARTUP_WAIT of U0_DCM: label is "FALSE";
--attribute DLL_FREQUENCY_MODE : string;
--attribute DUTY_CYCLE_CORRECTION : string;
--attribute CLK_FEEDBACK : string;
--attribute STARTUP_WAIT : string;
--attribute CLKFX_MULTIPLY : integer;
--attribute CLKFX_DIVIDE : integer;
--attribute CLKIN_PERIOD: string;
--attribute DLL_FREQUENCY_MODE of U0_DCM: label is "LOW";
--attribute DUTY_CYCLE_CORRECTION of U0_DCM: label is "TRUE";
--attribute CLK_FEEDBACK of U0_DCM: label is "1X";
--attribute STARTUP_WAIT of U0_DCM: label is "FALSE";
--attribute CLKFX_MULTIPLY of U0_DCM: label is 3;
--attribute CLKFX_DIVIDE of U0_DCM: label is 1;
attribute CLKIN_PERIOD of U0_DCM: label is "25";
--attribute CLKIN_PERIOD of U0_DCM: label is "25";
--
......@@ -117,24 +117,61 @@ Clk80Int <= clk80IntAux;
clk40Aux <= Clk40;
U0_DCM : DCM
generic map (
-- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
-- CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
-- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 25.0, -- Specify period of input clock
-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
-- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
-- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-- FACTORY_JF => X"C080", -- FACTORY JF Values
-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => clk40IntAux, -- 0 degree DCM CLK ouptput
-- CLK180 => CLK180, -- 180 degree DCM CLK output
-- CLK270 => CLK270, -- 270 degree DCM CLK output
CLK2X => clk40x2, -- 2X DCM CLK output
CLK2X180 => clk80IntNAux, -- 2X, 180 degree DCM CLK out
-- CLK90 => CLK90, -- 90 degree DCM CLK output
-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
-- CLKFX => CLKFX, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
LOCKED => Lock40Int, -- DCM LOCK status output
-- PSDONE => PSDONE, -- Dynamic phase adjust done output
-- STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => clk40FBAux, -- DCM clock feedback
CLKIN => clk40Aux, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => GND, -- Dynamic phase adjust clock input
PSEN => GND, -- Dynamic phase adjust enable input
PSINCDEC => GND, -- Dynamic phase adjust increment/decrement
RST => Reset -- DCM asynchronous reset input
);
--
-- DCM Instantiation for internal deskew of Clk40
U0_DCM: DCM
port map (
CLKIN => clk40Aux,
CLKFB => clk40FBAux,
CLK0 => clk40IntAux,
DSSEN => GND,
PSINCDEC => GND,
PSEN => GND,
PSCLK => GND,
RST => Reset,
CLK2X => clk40x2,
CLK2X180=> clk80IntNAux,
LOCKED => Lock40Int
);
--U0_DCM: DCM
-- port map (
-- CLKIN => clk40Aux,
-- CLKFB => clk40FBAux,
-- CLK0 => clk40IntAux,
-- DSSEN => GND,
-- PSINCDEC => GND,
-- PSEN => GND,
-- PSCLK => GND,
-- RST => Reset,
-- CLK2X => clk40x2,
-- CLK2X180=> clk80IntNAux,
-- LOCKED => Lock40Int
-- );
-- BUFG Instantiation for Clk80Int
......
......@@ -60,7 +60,7 @@ end Diagnostics;
architecture RTL of Diagnostics is
type StateType is (Idle, ReadRAM, ReadRAMWaiting, ReadRAMDone, ReadyForPulse, IToDAC, QToDac);
type StateType is (Idle, ReadRAM, ReadRAMWaiting, ReadRAMWaiting2, ReadRAMDone, ReadyForPulse, IToDAC, QToDac);
signal currentState, nextState: StateType;
signal diag1SelAux, diag2SelAux, diag3SelAux, diag4SelAux: std_logic_vector(15 downto 0);
......@@ -167,6 +167,8 @@ begin
when ReadRAM =>
nextState <= ReadRAMWaiting;
when ReadRAMWaiting =>
nextState <= ReadRAMWaiting2;
when ReadRAMWaiting2 =>
nextState <= ReadRAMDone;
when ReadRAMDone =>
nextState <= Idle;
......@@ -224,6 +226,26 @@ begin
elsif pendingRead4='1' then
RAM4OE <= '0';
end if;
when ReadRAMWaiting =>
if pendingRead1='1' then
RAM1OE <= '0';
elsif pendingRead2='1' then
RAM2OE <= '0';
elsif pendingRead3='1' then
RAM3OE <= '0';
elsif pendingRead4='1' then
RAM4OE <= '0';
end if;
when ReadRAMWaiting2 =>
if pendingRead1='1' then
RAM1OE <= '0';
elsif pendingRead2='1' then
RAM2OE <= '0';
elsif pendingRead3='1' then
RAM3OE <= '0';
elsif pendingRead4='1' then
RAM4OE <= '0';
end if;
when ReadRAMDone =>
if pendingRead1='1' then
DataToRM <= dataFromRAM1;
......
......@@ -15,18 +15,31 @@ end IQCounter;
architecture RTL of IQCounter is
signal iqCount0, iqCount1: std_logic; -- for readback
signal clk20d1, clk20d2, clk20Rising: std_logic;
signal iqCountAux: std_logic_vector(1 downto 0);
begin
IQCount(0) <= iqCount0;
IQCount(1) <= iqCount1;
IQCount <= iqCountAux;
clk20Rising <= clk20d1 and not clk20d2;
ClockedProcess: process(Clk80)
begin
if Clk80'event and Clk80='1' then
iqCount0 <= Clk20;
iqCount1 <= iqCount0;
clk20d1 <= Clk20;
clk20d2 <= clk20d1;
if clk20Rising='1' then
iqCountAux <= "11";
elsif iqCountAux = "11" then
iqCountAux <= "10";
elsif iqCountAux = "10" then
iqCountAux <= "00";
elsif iqCountAux = "00" then
iqCountAux <= "01";
elsif iqCountAux = "01" then
iqCountAux <= "11";
end if;
end if;
end process ClockedProcess;
......
......@@ -31,7 +31,7 @@ end SetPoints;
architecture RTL of SetPoints is
type StateType is (Idle, rmRead, rmReadWaiting, rmDataValid, rmWrite, rmWriteDone, rfOnRead);
type StateType is (Idle, rmRead, rmReadWaiting, rmReadWaiting2, rmDataValid, rmWrite, rmWriteDone, rfOnRead);
signal currentState, nextState: StateType;
signal ramDataIn, ramDataInC, ramDataOut: std_logic_vector(15 downto 0);
......@@ -95,6 +95,8 @@ begin
when rmRead =>
nextState <= rmReadWaiting;
when rmReadWaiting =>
nextState <= rmReadWaiting2;
when rmReadWaiting2 =>
nextState <= rmDataValid;
when rmDataValid =>
nextState <= Idle;
......@@ -136,6 +138,10 @@ begin
ramAddrAux <= unsigned(rmPendingAddr);
RAMOE <= '0';
RAMCS <= '0';
when rmReadWaiting =>
RAMOE <= '0';
when rmReadWaiting2 =>
RAMOE <= '0';
when rmDataValid =>
DataToRM <= ramDataIn;
DataToRMValid <= '1';
......
NET "clk40in" TNM_NET = "clk40in";
TIMESPEC "TS_clk40in" = PERIOD "clk40in" 45 MHz HIGH 50 %;
#NET "clk40in" TNM_NET = "clk40in";
#TIMESPEC "TS_clk40in" = PERIOD "clk40in" 45 MHz HIGH 50 %;
NET "Clk40In" TNM_NET = "Clk40In";
NET "CavDry" LOC = "B8";
NET "FwdDry" LOC = "D1";
......
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