Commit dcf2f523 authored by Javier Serrano's avatar Javier Serrano Committed by Dimitris Lampridis
Browse files

Using Pablo's anti-glitch VME interface now.


git-svn-id: https://www.ohwr.org/svn/lrfsc/trunk@6 6473569e-ccbe-4206-bb48-f381304e9851
parent 2d3041be
Release 10.1.02 par K.37 (nt)
Release 10.1.03 par K.39 (lin)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
PCBE13042:: Tue Nov 16 16:28:51 2010
pcbe13133:: Mon Jun 13 15:17:39 2011
par -w -intstyle ise -ol med -t 1 CavityControlCWV3_map.ncd
par -w -intstyle ise -ol med -t 1 CavityControlCWV3_map.ncd
CavityControlCWV3.ncd CavityControlCWV3.pcf
Constraints file: CavityControlCWV3.pcf.
Loading device for application Rf_Device from file '2v2000.nph' in environment C:\Xilinx\10.1\ISE.
Loading device for application Rf_Device from file '2v2000.nph' in environment /opt/Xilinx/10.1/ISE.
"CavityControlCWV3" is an NCD, version 3.2, device xc2v2000, package fg676, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.121 2008-05-01".
Device speed data version: "PRODUCTION 1.121 2008-07-25".
Device Utilization Summary:
......@@ -31,7 +31,7 @@ Device Utilization Summary:
Number of LOCed IOBs 438 out of 438 100%
Number of MULT18X18s 26 out of 56 46%
Number of SLICEs 3280 out of 10752 30%
Number of SLICEs 3296 out of 10752 30%
Overall effort level (-ol): Medium
......@@ -52,93 +52,89 @@ WARNING:Par:288 - The signal RefDry_IBUF has no load. PAR will not attempt to r
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:bb3710) REAL time: 5 secs
Phase 1.1 (Checksum:bc21c8) REAL time: 5 secs
Phase 2.7
Phase 2.7 (Checksum:bb3710) REAL time: 5 secs
Phase 2.7 (Checksum:bc21c8) REAL time: 5 secs
Phase 3.31
Phase 3.31 (Checksum:bb3710) REAL time: 5 secs
Phase 3.31 (Checksum:bc21c8) REAL time: 5 secs
Phase 4.2
.
Phase 4.2 (Checksum:bbc6d2) REAL time: 6 secs
Phase 4.2 (Checksum:bcb18a) REAL time: 6 secs
Phase 5.30
Phase 5.30 (Checksum:bbc6d2) REAL time: 6 secs
Phase 5.30 (Checksum:bcb18a) REAL time: 6 secs
Phase 6.3
Phase 6.3 (Checksum:bbc6d2) REAL time: 6 secs
Phase 6.3 (Checksum:bcb18a) REAL time: 6 secs
Phase 7.5
Phase 7.5 (Checksum:bbc6d2) REAL time: 6 secs
Phase 7.5 (Checksum:bcb18a) REAL time: 6 secs
Phase 8.8
......................
....
.........................
.......
..
......
.......
..
..
Phase 8.8 (Checksum:36431d0) REAL time: 21 secs
...
Phase 8.8 (Checksum:36c003f) REAL time: 22 secs
Phase 9.5
Phase 9.5 (Checksum:36431d0) REAL time: 21 secs
Phase 9.5 (Checksum:36c003f) REAL time: 23 secs
Phase 10.18
Phase 10.18 (Checksum:366ba6f) REAL time: 31 secs
Phase 10.18 (Checksum:36e49ab) REAL time: 34 secs
Phase 11.5
Phase 11.5 (Checksum:366ba6f) REAL time: 31 secs
Phase 11.5 (Checksum:36e49ab) REAL time: 34 secs
Phase 12.27
Phase 12.27 (Checksum:366ba6f) REAL time: 32 secs
Phase 12.27 (Checksum:36e49ab) REAL time: 35 secs
Phase 13.24
Phase 13.24 (Checksum:366ba6f) REAL time: 33 secs
Phase 13.24 (Checksum:36e49ab) REAL time: 35 secs
REAL time consumed by placer: 33 secs
CPU time consumed by placer: 33 secs
REAL time consumed by placer: 35 secs
CPU time consumed by placer: 35 secs
Writing design to file CavityControlCWV3.ncd
Total REAL time to Placer completion: 33 secs
Total CPU time to Placer completion: 34 secs
Total REAL time to Placer completion: 36 secs
Total CPU time to Placer completion: 35 secs
Starting Router
Phase 1: 22659 unrouted; REAL time: 38 secs
Phase 2: 20234 unrouted; REAL time: 44 secs
Phase 3: 5687 unrouted; REAL time: 47 secs
Phase 1: 22687 unrouted; REAL time: 41 secs
Phase 4: 5687 unrouted; (812210) REAL time: 47 secs
Phase 2: 19984 unrouted; REAL time: 46 secs
Phase 5: 5848 unrouted; (3039) REAL time: 50 secs
Phase 3: 5629 unrouted; REAL time: 48 secs
Phase 6: 0 unrouted; (31004) REAL time: 56 secs
Phase 4: 5629 unrouted; (797978) REAL time: 48 secs
Phase 7: 0 unrouted; (31004) REAL time: 58 secs
Phase 5: 5839 unrouted; (12214) REAL time: 50 secs
Phase 8: 0 unrouted; (31004) REAL time: 58 secs
Phase 6: 0 unrouted; (48617) REAL time: 56 secs
Phase 9: 0 unrouted; (20018) REAL time: 1 mins 2 secs
Phase 7: 0 unrouted; (48617) REAL time: 58 secs
Phase 10: 0 unrouted; (19576) REAL time: 1 mins 6 secs
Phase 8: 0 unrouted; (48617) REAL time: 58 secs
Phase 11: 0 unrouted; (19525) REAL time: 1 mins 9 secs
Phase 9: 0 unrouted; (34297) REAL time: 1 mins 1 secs
Phase 12: 0 unrouted; (19525) REAL time: 1 mins 16 secs
Phase 10: 0 unrouted; (34297) REAL time: 1 mins 12 secs
Phase 13: 0 unrouted; (19525) REAL time: 1 mins 16 secs
Phase 11: 0 unrouted; (34297) REAL time: 1 mins 12 secs
Phase 14: 0 unrouted; (19020) REAL time: 1 mins 18 secs
Phase 12: 0 unrouted; (32081) REAL time: 1 mins 14 secs
Total REAL time to Router completion: 1 mins 19 secs
Total CPU time to Router completion: 1 mins 20 secs
Total REAL time to Router completion: 1 mins 15 secs
Total CPU time to Router completion: 1 mins 14 secs
Partition Implementation Status
-------------------------------
......@@ -156,11 +152,11 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk80N | BUFGMUX2S| No | 108 | 0.172 | 1.490 |
| clk80N | BUFGMUX2S| No | 108 | 0.188 | 1.506 |
+---------------------+--------------+------+------+------------+-------------+
| clk80 | BUFGMUX1P| No | 112 | 0.312 | 1.517 |
+---------------------+--------------+------+------+------------+-------------+
| clk40 | BUFGMUX0S| No | 1884 | 0.323 | 1.528 |
| clk40 | BUFGMUX0S| No | 1894 | 0.311 | 1.516 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -170,9 +166,9 @@ the minimum and maximum path delays which includes logic delays.
Timing Score: 0
INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the
INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the
post Place and Route timing report.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
requested value.
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
......@@ -184,14 +180,14 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 17.840ns| N/A| 0
40 | HOLD | 1.214ns| | 0| 0
Autotimespec constraint for clock net clk | SETUP | N/A| 17.680ns| N/A| 0
40 | HOLD | 0.999ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 6.680ns| N/A| 0
80N | HOLD | 1.391ns| | 0| 0
Autotimespec constraint for clock net clk | SETUP | N/A| 6.550ns| N/A| 0
80N | HOLD | 1.429ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 14.675ns| N/A| 0
80 | HOLD | 1.356ns| | 0| 0
Autotimespec constraint for clock net clk | SETUP | N/A| 14.080ns| N/A| 0
80 | HOLD | 1.622ns| | 0| 0
------------------------------------------------------------------------------------------------------
......@@ -206,10 +202,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 9 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 24 secs
Total CPU time to PAR completion: 1 mins 25 secs
Total REAL time to PAR completion: 1 mins 21 secs
Total CPU time to PAR completion: 1 mins 20 secs
Peak Memory Usage: 308 MB
Peak Memory Usage: 275 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
......
vhdl work "../sources/SineCosine.vhd"
vhdl work "../sources/RegistersMap.vhd"
vhdl work "../sources/VmeIntfce.vhd"
vhdl work "../sources/VMEDecoder.vhd"
vhdl work "../sources/TimingManager.vhd"
vhdl work "../sources/Snapshots.vhd"
vhdl work "../sources/SetPoints.vhd"
vhdl work "../sources/SatControlCW.vhd"
vhdl work "../sources/ResControl.vhd"
vhdl work "../sources/RAMManager.vhd"
vhdl work "../sources/PIControllerCW.vhd"
vhdl work "../sources/OneShot.vhd"
vhdl work "../sources/mul2x2.vhd"
vhdl work "../sources/IrqControl.vhd"
vhdl work "../sources/IQModulator.vhd"
vhdl work "../sources/iqdemodcw.vhd"
vhdl work "../sources/IQCounter.vhd"
vhdl work "../sources/FeedForward.vhd"
vhdl work "../sources/Diagnostics.vhd"
vhdl work "../sources/Commands.vhd"
vhdl work "../sources/ClockManager.vhd"
vhdl work "../sources/CavityControlCWV3.vhd"
vhdl work "../sources/SineCosine.vhd"
vhdl work "../sources/RegistersMap.vhd"
vhdl work "../sources/VMEDecoder.vhd"
vhdl work "../sources/TimingManager.vhd"
vhdl work "../sources/Snapshots.vhd"
vhdl work "../sources/SetPoints.vhd"
vhdl work "../sources/SatControlCW.vhd"
vhdl work "../sources/ResControl.vhd"
vhdl work "../sources/RAMManager.vhd"
vhdl work "../sources/PIControllerCW.vhd"
vhdl work "../sources/OneShot.vhd"
vhdl work "../sources/mul2x2.vhd"
vhdl work "../sources/IrqControl.vhd"
vhdl work "../sources/IQModulator.vhd"
vhdl work "../sources/iqdemodcw.vhd"
vhdl work "../sources/IQCounter.vhd"
vhdl work "../sources/FeedForward.vhd"
vhdl work "../sources/Diagnostics.vhd"
vhdl work "../sources/Commands.vhd"
vhdl work "../sources/ClockManager.vhd"
vhdl work "../sources/AntiGlitchVmeIntfce.vhd"
vhdl work "../sources/CavityControlCWV3.vhd"
Release 10.1.02 Map K.37 (nt)
Release 10.1.03 Map K.39 (lin)
Xilinx Map Application Log File for Design 'CavityControlCWV3'
Design Information
------------------
Command Line : map -ise E:/ohr/lrfsc/trunk/hdl/ise/RFControlV4.ise -intstyle
ise -p xc2v2000-fg676-4 -cm speed -ignore_keep_hierarchy -pr b -k 4 -c 100 -tx
off -o CavityControlCWV3_map.ncd CavityControlCWV3.ngd CavityControlCWV3.pcf
Command Line : map -ise
/home/serrano/temp/llrf_linac3/lrfsc/trunk/hdl/ise/RFControlV4.ise -intstyle ise
-p xc2v2000-fg676-4 -cm speed -ignore_keep_hierarchy -pr b -k 4 -c 100 -tx off
-o CavityControlCWV3_map.ncd CavityControlCWV3.ngd CavityControlCWV3.pcf
Target Device : xc2v2000
Target Package : fg676
Target Speed : -4
Mapper Version : virtex2 -- $Revision: 1.46.12.2 $
Mapped Date : Tue Nov 16 16:28:37 2010
Mapped Date : Mon Jun 13 15:17:24 2011
Mapping design into LUTs...
Running directed packing...
......@@ -24,25 +25,25 @@ Design Summary:
Number of errors: 0
Number of warnings: 11
Logic Utilization:
Number of Slice Flip Flops: 3,125 out of 21,504 14%
Number of 4 input LUTs: 4,626 out of 21,504 21%
Number of Slice Flip Flops: 3,194 out of 21,504 14%
Number of 4 input LUTs: 4,601 out of 21,504 21%
Logic Distribution:
Number of occupied Slices: 3,280 out of 10,752 30%
Number of Slices containing only related logic: 3,280 out of 3,280 100%
Number of Slices containing unrelated logic: 0 out of 3,280 0%
Number of occupied Slices: 3,296 out of 10,752 30%
Number of Slices containing only related logic: 3,296 out of 3,296 100%
Number of Slices containing unrelated logic: 0 out of 3,296 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 4,849 out of 21,504 22%
Number used as logic: 4,624
Number used as a route-thru: 223
Number used as Shift registers: 2
Total Number of 4 input LUTs: 4,806 out of 21,504 22%
Number used as logic: 4,544
Number used as a route-thru: 205
Number used as Shift registers: 57
Number of bonded IOBs: 438 out of 456 96%
IOB Flip Flops: 234
IOB Flip Flops: 218
Number of MULT18X18s: 26 out of 56 46%
Number of BUFGMUXs: 3 out of 16 18%
Number of DCMs: 1 out of 8 12%
Peak Memory Usage: 240 MB
Total REAL time to MAP completion: 8 secs
Peak Memory Usage: 217 MB
Total REAL time to MAP completion: 9 secs
Total CPU time to MAP completion: 8 secs
NOTES:
......
This diff is collapsed.
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD COLSPAN='4'><B>RFControlV4 Project Status</B></TD></TR>
<TD COLSPAN='4'><B>RFControlV4 Project Status (06/13/2011 - 15:19:28)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>RFControlV4.ise</TD>
......@@ -20,11 +20,11 @@ No Errors</TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc2v2000-4fg676</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>575 Warnings</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/*.xmsgs'>549 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
<TD>ISE 10.1.02 - Foundation Simulator</TD>
<TD>ISE 10.1.03 - Foundation Simulator</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='CavityControlCWV3.unroutes'>All Signals Completely Routed</A></TD>
......@@ -59,13 +59,13 @@ No Errors</TD>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>3,125</TD>
<TD ALIGN=RIGHT>3,194</TD>
<TD ALIGN=RIGHT>21,504</TD>
<TD ALIGN=RIGHT>14%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>4,626</TD>
<TD ALIGN=RIGHT>4,601</TD>
<TD ALIGN=RIGHT>21,504</TD>
<TD ALIGN=RIGHT>21%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -74,43 +74,43 @@ No Errors</TD>
<TD ALIGN=LEFT><B>Logic Distribution </B></TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>3,280</TD>
<TD ALIGN=RIGHT>3,296</TD>
<TD ALIGN=RIGHT>10,752</TD>
<TD ALIGN=RIGHT>30%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>3,280</TD>
<TD ALIGN=RIGHT>3,280</TD>
<TD ALIGN=RIGHT>3,296</TD>
<TD ALIGN=RIGHT>3,296</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>3,280</TD>
<TD ALIGN=RIGHT>3,296</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number of 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>4,849</TD>
<TD ALIGN=RIGHT>4,806</TD>
<TD ALIGN=RIGHT>21,504</TD>
<TD ALIGN=RIGHT>22%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>4,624</TD>
<TD ALIGN=RIGHT>4,544</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as a route-thru</TD>
<TD ALIGN=RIGHT>223</TD>
<TD ALIGN=RIGHT>205</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift registers</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>57</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -123,7 +123,7 @@ No Errors</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;IOB Flip Flops</TD>
<TD ALIGN=RIGHT>234</TD>
<TD ALIGN=RIGHT>218</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -179,14 +179,14 @@ No Errors</TD>
<TBODY><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER width=90% COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT width=10% COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR></TBODY></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:28:26 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>418 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/xst.xmsgs'>127 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:28:34 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/ngdbuild.xmsgs'>134 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:28:49 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>11 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/map.xmsgs'>112 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:30:17 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>12 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/par.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:30:25 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/trce.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Tue 16. Nov 16:30:50 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>9 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>1 Info</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Jun 13 15:17:05 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/xst.xmsgs'>392 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/xst.xmsgs'>122 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon Jun 13 15:17:21 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/ngdbuild.xmsgs'>134 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Jun 13 15:17:36 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/map.xmsgs'>11 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/map.xmsgs'>80 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Jun 13 15:19:01 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/par.xmsgs'>12 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/par.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.twr'>Static Timing Report</A></TD><TD>Current</TD><TD>Mon Jun 13 15:19:08 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/trce.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='CavityControlCWV3.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon Jun 13 15:19:27 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>9 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='_xmsgs/bitgen.xmsgs'>1 Info</A></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 11/16/2010 - 16:39:47</center>
<br><center><b>Date Generated:</b> 06/13/2011 - 15:19:28</center>
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......@@ -163,21 +163,22 @@ COMPONENT vme_intfce
generic ( AddrWidth : integer:=24;
BaseAddrWidth : integer:=4;
DataWidth : integer:=16;
DirSamePolarity : std_logic:='0';
UnalignDataWidth : integer:=8;
InterruptEn : std_logic:='1');
--DirSamePolarity : std_logic:='0';
--UnalignDataWidth : integer:=8;
InterruptEn : std_logic:='1';
WatchDogTop : integer := 80);
port (
ResetNA : in std_logic;
RstN : in std_logic;
Clk : in std_logic;
VmeAddrA : in std_logic_vector(AddrWidth-1 downto 1 );
VmeAsNA : in std_logic;
VmeDs1NA : in std_logic;
VmeDs0NA : in std_logic;
VmeData : inout std_logic_vector(DataWidth-1 downto 0 );
VmeDataUnAlign: inout std_logic_vector(UnalignDataWidth-1 downto 0);
--VmeDataUnAlign: inout std_logic_vector(UnalignDataWidth-1 downto 0);
VmeDir : out std_logic;
VmeDirFloat : out std_logic;
--VmeDirFloat : out std_logic;
VmeBufOeN : out std_logic;
VmeWriteNA : in std_logic;
VmeLwordNA : in std_logic;
......@@ -192,16 +193,18 @@ COMPONENT vme_intfce
AddrMem : out std_logic_vector(AddrWidth-BaseAddrWidth-1 downto 0 );
ReadMem : out std_logic;
WriteMem : out std_logic;
DataFromMemValid : in std_logic;
--DataFromMemValid : in std_logic;
DataReadDone : in std_logic;
DataWriteDone : in std_logic;
DataFromMem : in std_logic_vector(DataWidth-1 downto 0 );
DataToMem : out std_logic_vector(DataWidth-1 downto 0 );
IntProcessed : out std_logic;
UserIntReqN : in std_logic;
UserBlocks : in std_logic;
OpFinishedOut : out std_logic;
--UserBlocks : in std_logic;
--OpFinishedOut : out std_logic;
IRQLevelReg : in std_logic_vector (3 downto 1);
IRQStatusIDReg: in std_logic_vector (DataWidth-1 downto 0);
VmeState : out std_logic_vector (3 downto 0));
IRQStatusIDReg: in std_logic_vector (DataWidth-1 downto 0));
--VmeState : out std_logic_vector (3 downto 0));
END COMPONENT;
COMPONENT irqcontrol
......@@ -719,11 +722,12 @@ U0_vme_intfce: vme_intfce
AddrWidth => 24,
BaseAddrWidth => 4,
DataWidth => 16,
DirSamePolarity => '0',
InterruptEn => '1')
--DirSamePolarity => '0',
InterruptEn => '1',
WatchDogTop => 80)
PORT MAP(
resetna => ResetNA,
rstn => ResetNA,
clk => clk40,
vmeaddra => VMEAddress,
vmeasna => VMEASNA,
......@@ -746,16 +750,17 @@ PORT MAP(
addrmem => vmeAddrInt,
readmem => readFromVME,
writemem => writeFromVME,
datafrommemvalid => dataToVMEValid,
datareaddone => dataToVMEValid,
datawritedone => '1',
datafrommem => dataToVME,
datatomem => dataFromVME,
intprocessed => intProcessed,
userintreqn => irqToVMEN,
userblocks => '0',
opfinishedout => open,
--userblocks => '0',
--opfinishedout => open,
irqlevelreg => "010",
irqstatusidreg => registers(VMEIRQR),
vmestate => open
irqstatusidreg => registers(VMEIRQR)
--vmestate => open
);
......
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