Commit e4174e98 authored by Javier Serrano's avatar Javier Serrano
Browse files

First changes for new version.


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@1232 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent 59e2f83f
This diff is collapsed.
----------------------------------------------------
--
-- Unit Name : ClockManager
--
-- Description:
--
-- The ClockManager entity generates all the internal clocks for the design.
-- The master clock is the 40 MHz coming from outside of the card
-- We then generate a 40 MHz , an 80 MHz, an 80 MHz negated, a 100 MHz and an on-chip
-- internal 200 MHz. The lock signals are also available for debugging.
-- We then generate a 40 MHz, 80 MHz, and 80 MHz negated.
-- The lock signals are also available for debugging.
--
-- Author : Javier Serrano
-- Group: AB/CO
--
-- Revisions:
-- 1.1. (24 September 2003) Initial release
-- 1.5. (2 June 2008) Clean-up and comments.
--
--
-- For any bug or comment, please send an e-mail to Javier.Serrano@cern.ch
library IEEE;
use IEEE.std_logic_1164.all;
--
-- bla synopsys translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- bla synopsys translate_on
--
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockManager is
port (
Reset : in std_logic;
......@@ -21,81 +36,9 @@ entity ClockManager is
Lock40Int : out std_logic
);
end ClockManager;
--
architecture RTL of ClockManager is
--
-- Components Declarations:
--
--component BUFG
-- port (
-- I : in std_logic;
-- O : out std_logic
-- );
--end component;
--
--component IBUFG
-- port (
-- I : in std_logic;
-- O : out std_logic
-- );
--end component;
--
--component DCM
-- synopsys translate_off
-- generic (
-- DLL_FREQUENCY_MODE : string := "LOW";
-- DUTY_CYCLE_CORRECTION : boolean := TRUE;
-- CLK_FEEDBACK : string := "2X";
-- CLKFX_MULTIPLY : integer := 5 ;
-- CLKFX_DIVIDE : integer := 2;
-- STARTUP_WAIT : boolean := FALSE
);
-- synopsys translate_on
--
-- port ( CLKIN : in std_logic;
-- CLKFB : in std_logic;
-- DSSEN : in std_logic;
-- PSINCDEC : in std_logic;
-- PSEN : in std_logic;
-- PSCLK : in std_logic;
-- RST : in std_logic;
-- CLK0 : out std_logic;
-- CLK90 : out std_logic;
-- CLK180 : out std_logic;
-- CLK270 : out std_logic;
-- CLK2X : out std_logic;
-- CLK2X180 : out std_logic;
-- CLKDV : out std_logic;
-- CLKFX : out std_logic;
-- CLKFX180 : out std_logic;
-- LOCKED : out std_logic;
-- PSDONE : out std_logic;
-- STATUS : out std_logic_vector(7 downto 0)
-- );
--end component;
--
-- Attributes
--attribute DLL_FREQUENCY_MODE : string;
--attribute DUTY_CYCLE_CORRECTION : string;
--attribute CLK_FEEDBACK : string;
--attribute STARTUP_WAIT : string;
--attribute CLKFX_MULTIPLY : integer;
--attribute CLKFX_DIVIDE : integer;
--attribute CLKIN_PERIOD: string;
--attribute DLL_FREQUENCY_MODE of U0_DCM: label is "LOW";
--attribute DUTY_CYCLE_CORRECTION of U0_DCM: label is "TRUE";
--attribute CLK_FEEDBACK of U0_DCM: label is "1X";
--attribute STARTUP_WAIT of U0_DCM: label is "FALSE";
--attribute CLKFX_MULTIPLY of U0_DCM: label is 3;
--attribute CLKFX_DIVIDE of U0_DCM: label is 1;
--attribute CLKIN_PERIOD of U0_DCM: label is "25";
--
-----------------------------------------------------------------------
--
-- Signal Declarations:
signal GND : std_logic;
--
......@@ -119,35 +62,16 @@ clk40Aux <= Clk40;
U0_DCM : DCM
generic map (
-- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-- CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
-- CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
-- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 25.0, -- Specify period of input clock
-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
-- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
-- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-- FACTORY_JF => X"C080", -- FACTORY JF Values
-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLK0 => clk40IntAux, -- 0 degree DCM CLK ouptput
-- CLK180 => CLK180, -- 180 degree DCM CLK output
-- CLK270 => CLK270, -- 270 degree DCM CLK output
CLK2X => clk40x2, -- 2X DCM CLK output
CLK2X180 => clk80IntNAux, -- 2X, 180 degree DCM CLK out
-- CLK90 => CLK90, -- 90 degree DCM CLK output
-- CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
-- CLKFX => CLKFX, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
LOCKED => Lock40Int, -- DCM LOCK status output
-- PSDONE => PSDONE, -- Dynamic phase adjust done output
-- STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => clk40FBAux, -- DCM clock feedback
CLKIN => clk40Aux, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => GND, -- Dynamic phase adjust clock input
......@@ -156,24 +80,6 @@ U0_DCM : DCM
RST => Reset -- DCM asynchronous reset input
);
--
-- DCM Instantiation for internal deskew of Clk40
--U0_DCM: DCM
-- port map (
-- CLKIN => clk40Aux,
-- CLKFB => clk40FBAux,
-- CLK0 => clk40IntAux,
-- DSSEN => GND,
-- PSINCDEC => GND,
-- PSEN => GND,
-- PSCLK => GND,
-- RST => Reset,
-- CLK2X => clk40x2,
-- CLK2X180=> clk80IntNAux,
-- LOCKED => Lock40Int
-- );
-- BUFG Instantiation for Clk80Int
U0_BUFG: BUFG
port map (
......
----------------------------------------------------
--
-- Unit Name : Commands
--
-- Description:
--
-- Implements commands support.
--
-- Author : Javier Serrano
-- Group : AB/CO
--
-- Revisions:
-- 1.1. (17 November 2003) Initial release
-- 1.7. (4 June 2008) Clean-up and comments.
-- TO DO: status register
--
-- For any bug or comment, please send an e-mail to Javier.Serrano@cern.ch
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
......@@ -5,13 +23,21 @@ use IEEE.NUMERIC_STD.ALL;
entity Commands is
Port ( Clk40 : in std_logic;
ResetNA : in std_logic;
IQAlarm: in std_logic;
CavOvr: in std_logic;
FwdOvr: in std_logic;
RefOvr: in std_logic;
RFOnRising: in std_logic;
RFOnFalling: in std_logic;
FProtect: in std_logic;
WriteCONTROLR : in std_logic;
WriteSWITCHCTRLR : in std_logic;
WriteSOFTSWITCHR: in std_logic;
WriteSTATER: in std_logic;
WriteRFONMAXLENGTHR: in std_logic;
ReadStatus: in std_logic;
TimeTracker: in std_logic_vector(15 downto 0);
DataFromDecoder : in std_logic_vector(15 downto 0);
SyncReset : out std_logic;
CavSwitch : out std_logic;
RefSwitch : out std_logic;
FwdSwitch : out std_logic;
......@@ -20,16 +46,27 @@ entity Commands is
SatDisabled: out std_logic;
DoAcquisition: out std_logic; -- Check the state of this signal at RFOnRising time to decide whether to make acquisition or not.
ConfigMode: out std_logic;
ProdLocalMode: out std_logic;
ProdRemoteMode: out std_logic;
CWMode: out std_logic;
CONTROLR : out std_logic_vector(15 downto 0);
STATUSR : out std_logic_vector(15 downto 0);
STATER: out std_logic_vector(15 downto 0);
RFONMAXLENGTHR: out std_logic_vector(15 downto 0);
SWITCHCTRLR : out std_logic_vector(15 downto 0);
SOFTSWITCHR : out std_logic_vector(15 downto 0));
end Commands;
architecture RTL of Commands is
signal switchCtrlAux, softSwitchAux, controlAux: std_logic_vector(15 downto 0);
signal rfOnToggle: std_logic;
type StateType is (Idle, WaitingRFRising, WaitingRFFalling);
signal currentState, nextState: StateType;
signal switchCtrlAux, softSwitchAux, controlAux, stateAux: std_logic_vector(15 downto 0);
signal configAux, prodLocalAux, prodRemoteAux: std_logic;
signal rfOnToggle, aqnPending, satDisabledAux, cwModeAux: std_logic;
signal maxLengthAux: std_logic_vector(15 downto 0);
signal cavOvrAux, fwdOvrAux, refOvrAux: std_logic;
signal lengthAlarm, iqAlarmAux: std_logic;
begin
......@@ -40,21 +77,70 @@ OutSwitch <= switchCtrlAux(3);
MainLoopSwitch <= softSwitchAux(0);
SWITCHCTRLR <= switchCtrlAux;
SOFTSWITCHR <= softSwitchAux;
CONTROLR <= controlAux;
SatDisabled <= controlAux(3);
ConfigMode <= not controlAux(0);
STATUSR <= X"000" & '0' & rfOnToggle & FProtect & controlAux(0);
STATER <= stateAux;
CONTROLR <= controlAux(15 downto 1) & aqnPending;
SatDisabled <= satDisabledAux;
STATUSR <= "0000000000" & iqAlarmAux & FProtect & lengthAlarm & cavOvrAux & fwdOvrAux & refOvrAux;
configAux <= '1' when stateAux(1 downto 0)="00" else '0';
prodLocalAux <= '1' when stateAux(1 downto 0)="01" else '0';
prodRemoteAux <= '1' when stateAux(1 downto 0)="10" else '0';
ConfigMode <= configAux;
ProdLocalMode <= prodLocalAux;
ProdRemoteMode <= prodRemoteAux;
DoAcquisition <= controlAux(0) and prodRemoteAux;
RFONMAXLENGTHR <= maxLengthAux;
stateTransitions: process(ResetNA, Clk40)
begin
if ResetNA='0' then
currentState <= Idle;
elsif Clk40'event and Clk40='1' then
currentState <= nextState;
end if;
end process stateTransitions;
FSM: process(currentState, aqnPending, prodRemoteAux, RFOnRising, RFOnFalling)
begin
case currentState is
when Idle =>
if aqnPending='1' and prodRemoteAux='1' then
nextState <= WaitingRFRising;
else nextState <= Idle;
end if;
when WaitingRFRising =>
if RFOnRising='1' then
nextState <= WaitingRFFalling;
else nextState <= WaitingRFRising;
end if;
when WaitingRFFalling =>
if RFOnFalling='1' then
nextState <= Idle;
else nextState <= WaitingRFFalling;
end if;
when others =>
nextState <= Idle;
end case;
end process FSM;
Decoder: process(ResetNA, Clk40)
begin
if ResetNA='0' then
SyncReset <= '0';
controlAux <= (others=>'0');
switchCtrlAux <= (others=>'0');
softSwitchAux <= (others=>'0');
stateAux <= (others=>'0');
controlAux <= (others=>'0');
rfOnToggle <= '0';
DoAcquisition <= '1';
aqnPending <= '0';
satDisabledAux <= '0';
cwModeAux <= '0';
cavOvrAux <= '0';
fwdOvrAux <= '0';
refOvrAux <= '0';
lengthAlarm <= '0';
iqAlarmAux <= '0';
elsif Clk40'event and Clk40='1' then
if RfOnFalling='1' then
......@@ -63,27 +149,63 @@ begin
if WriteCONTROLR='1' then
controlAux <= DataFromDecoder;
if DataFromDecoder(1)='1' then
SyncReset <= '1';
else
SyncReset <= '0';
end if;
else
SyncReset <= '0';
end if; -- writeCONTROLR='1'
if WriteCONTROLR='1' then
DoAcquisition <= DataFromDecoder(2);
aqnPending <= DataFromDecoder(0);
cwModeAux <= DataFromDecoder(1);
satDisabledAux <= DataFromDecoder(3);
elsif currentState=WaitingRFFalling and nextState=Idle then
aqnPending <= '0';
end if;
if WriteSWITCHCTRLR='1' then
switchCtrlAux <= DataFromDecoder;
end if;
if WriteRFONMAXLENGTHR='1' then
maxLengthAux <= DataFromDecoder;
end if;
if WriteSTATER='1' then
stateAux <= DataFromDecoder;
end if;
if WriteSOFTSWITCHR='1' then
softSwitchAux <= DataFromDecoder;
end if;
if cavOvr='1' then
cavOvrAux <= '1';
elsif ReadStatus='1' then
cavOvrAux <= '0';
end if;
if fwdOvr='1' then
fwdOvrAux <= '1';
elsif ReadStatus='1' then
fwdOvrAux <= '0';
end if;
if refOvr='1' then
refOvrAux <= '1';
elsif ReadStatus='1' then
refOvrAux <= '0';
end if;
if RFOnFalling='1' then
if unsigned(maxLengthAux) < unsigned(TimeTracker) then
lengthAlarm <= '1';
elsif ReadStatus='1' then
lengthAlarm <= '0';
end if;
elsif ReadStatus='1' then
lengthAlarm <= '0';
end if;
if IQAlarm='1' then
iqAlarmAux <= '1';
elsif ReadStatus='1' then
iqAlarmAux <= '0';
end if;
end if; -- clk event
end process Decoder;
......
......@@ -10,6 +10,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity IQCounter is
Port ( Clk20 : in std_logic;
Clk80 : in std_logic;
Alarm : out std_logic;
IQCount : out std_logic_vector(1 downto 0));
end IQCounter;
......@@ -43,5 +44,17 @@ begin
end if;
end process ClockedProcess;
AlarmProcess: process(Clk80)
begin
if Clk80'event and Clk80='1' then
if iqCountAux = "01" then
if clk20Rising='0' then
Alarm <= '1';
else
Alarm <= '0';
end if;
end if;
end if;
end process AlarmProcess;
end RTL;
......@@ -9,6 +9,7 @@ use IEEE.NUMERIC_STD.ALL;
entity IQModulator is
Port ( ResetNA : in std_logic;
ConfigMode: in std_logic;
Clk : in std_logic;
I : in std_logic_vector(13 downto 0);
Q : in std_logic_vector(13 downto 0);
......@@ -41,6 +42,7 @@ signal yAux1, yAux2, yAux3, yAux4: signed (27 downto 0);
--signal yAux1, yAux2: signed(14 downto 0);
signal wave1Aux, wave2Aux: signed (28 downto 0);
signal wave1, wave2: signed (26 downto 0);
signal resetA: std_logic;
attribute syn_multstyle : string;
attribute syn_multstyle of yAux1 : signal is "block_mult";
......@@ -54,18 +56,22 @@ sine1 <= signed(sine1Aux);
cosine1 <= signed(cosine1Aux);
sine2 <= signed(sine2Aux);
cosine2 <= signed(cosine2Aux);
resetA <= ConfigMode or (not ResetNA);
--WaveOut1 <= std_logic_vector(yAux1(13 downto 0));
--WaveOut2 <= std_logic_vector(yAux2(13 downto 0));
sync100: process(Clk)
sync1: process(resetA, Clk)
begin
if Clk'event and Clk='1' then
if resetA='1' then
i100 <= (others=>'0');
q100 <= (others=>'0');
elsif Clk'event and Clk='1' then
i100 <= signed(I);
q100 <= signed(Q);
end if;
end process sync1;
sync2: process(Clk)
begin
if Clk'event and Clk='1' then
--yAux1 <= resize(cosine1,15) + to_signed(8192, 15);
--yAux2 <= resize(cosine2,15) + to_signed(8192, 15);
yAux1 <= i100 * cosine1;
......@@ -94,7 +100,7 @@ begin
wave2 <= not(wave2Aux(26)) & wave2Aux(25 downto 0);
end if;
end if;
end process sync100;
end process sync2;
wave1Aux <= resize(yAux1,wave1Aux'length) +
resize(yAux2, wave1Aux'length);
......
----------------------------------------------------
--
-- Unit Name : IrqControl
--
-- Description:
--
-- The IrqControl entity contains all the logic related to VME interrupt generation.
-- It hosts the IRQ vector and IRQ sources registers, and it produces the (debounced) RFOnFalling and
-- RFOnRising signals for every other block to use. The interrupter is of the ROACK (Release on Acknowledge)
-- type. When the ISR comes and reads the IQR source register, it is cleared on read. There is a risk that
-- the ISR read clears a bit for which it was not invoked. The only side effect of this is that the next
-- invocation of the ISR will find an empty source register. This should be taken into account when writing
-- the ISR.
--
-- Author : Javier Serrano
-- Group : AB/CO
--
-- Revisions:
-- 1.1. (24 September 2003) Initial release
-- 1.4. (7 June 2008) Clean-up and comments.
--
--
-- For any bug or comment, please send an e-mail to Javier.Serrano@cern.ch
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
......@@ -7,13 +31,17 @@ entity IrqControl is
Port ( Clk : in std_logic;
IrqEnable : in std_logic;
RFOn : in std_logic;
StartCycleA: in std_logic;
Reset : in std_logic;
WriteVMEIRQR: in std_logic;
ReadIRQSRCR: in std_logic;
DataFromDecoder: in std_logic_vector(15 downto 0);
VMEIRQR: out std_logic_vector(15 downto 0);
IRQSRCR: out std_logic_vector(15 downto 0);
IntProcessed : in std_logic;
RFOnRising: out std_logic;
RFOnFalling: out std_logic;
StartCycle: out std_logic;
StateOut: out std_logic_vector(2 downto 0);
IrqN : out std_logic);
end IrqControl;
......@@ -22,23 +50,32 @@ architecture RTL of IrqControl is
type StateType is (Idle, Interrupting);
type DebounceStateType is (Idle, WaitingRFON, TempON, WaitingRFOFF, TempOFF);
type DebounceStateType2 is (Idle, Blocked);
attribute syn_enum_encoding : string;
attribute syn_enum_encoding of StateType : type is "sequential";
attribute syn_enum_encoding of DebounceStateType : type is "sequential";
signal rfOnFallingAux, rfOnRisingAux, rfOnD1, rfOnD2: std_logic;
signal rfOnFallingAux, rfOnRisingAux, rfOnD1, rfOnD2, rfOnD3: std_logic;
signal rfOnFallingOut, rfOnRisingOut: std_logic;
signal state, nextState: StateType;
signal debounceCurrent, debounceNext: DebounceStateType;
signal counter: unsigned(9 downto 0);
signal startDebounceCurrent, startDebounceNext: DebounceStateType2;
signal counter, counter2: unsigned(9 downto 0);
signal startCycleD1, startCycleD2, startCycleD3, startCycleRisingAux: std_logic;
signal startCycleRising: std_logic;
signal rfOnIRQSource, startCycleIRQSource: std_logic;
begin
rfOnFallingAux <= rfOnD2 and (not rfOnD1);
rfOnRisingAux <= rfOnD1 and (not rfOnD2);
rfOnFallingAux <= rfOnD3 and (not rfOnD2);
rfOnRisingAux <= rfOnD2 and (not rfOnD3);
startCycleRisingAux <= startCycleD2 and (not startCycleD3);
startCycleRising <= startCycleRisingAux when startDebounceCurrent=Idle else '0';
RFOnFalling <= rfOnFallingOut;
RFOnRising <= rfOnRisingOut;
IRQSRCR <= "00000000000000" & startCycleIRQSource & rfOnIRQSource;
StartCycle <= startCycleRising;
process(debounceCurrent)
begin
......@@ -58,13 +95,23 @@ begin
end case;
end process;
rfFalling: process(Clk)
rfOnClocking: process(Clk)
begin
if Clk'event and Clk='1' then
rfOnD1 <= RFOn;
rfOnD2 <= rfOnD1;
rfOnD3 <= rfOnD2;
end if;
end process rfOnClocking;
startCycleClocking: process(Clk)
begin
if Clk'event and Clk='1' then
startCycleD1 <= StartCycleA;
startCycleD2 <= startCycleD1;
startCycleD3 <= startCycleD2;
end if;
end process rfFalling;
end process startCycleClocking;
stateTransitions: process(Reset, Clk)
begin
......@@ -80,7 +127,7 @@ begin
case state is
when Idle =>
IrqN <= '1';
if rfOnFallingOut='1' and IrqEnable='1' then
if (rfOnFallingOut='1' or startCycleRising='1') and IrqEnable='1' then
nextState <= Interrupting;
else nextState <= Idle;
end if;
......@@ -107,6 +154,25 @@ begin
end if;
end process regProcess;
IRQSources: process(Reset, Clk)
begin
if Reset='1' then
rfOnIRQSource <= '0';
startCycleIRQSource <= '0';
elsif Clk'event and Clk='1' then
if rfOnFallingOut='1' then
rfOnIRQSource <= '1';
elsif ReadIRQSRCR='1' then
rfOnIRQSource <= '0';
end if;
if startCycleRising='1' then
startCycleIRQSource <= '1';
elsif ReadIRQSRCR='1' then
startCycleIRQSource <= '0';