Commit e4422017 authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@799 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent 4429a42f
......@@ -18,7 +18,8 @@ entity CavityControlCWV3 is
RefIn : in std_logic_vector(13 downto 0);
FwdIn : in std_logic_vector(13 downto 0);
CavIn : in std_logic_vector(13 downto 0);
ResCtrlDAC : out std_logic_vector(11 downto 0);
ResCtrlD : out std_logic;
ResSClk : out std_logic;
ResLDAC : out std_logic;
RFDAC1 : out std_logic_vector(13 downto 0);
RFDAC2 : out std_logic_vector(13 downto 0);
......@@ -103,6 +104,9 @@ entity CavityControlCWV3 is
RAM8OE : out std_logic;
RAM8WE : out std_logic;
RAMZZ : out std_logic_vector(8 downto 1);
DIAGZZ : out std_logic_vector(4 downto 1);
CavLed : out std_logic;
RefLed : out std_logic;
FProtectLed : out std_logic;
......@@ -303,7 +307,8 @@ COMPONENT rescontrol
DataFromDecoder : IN std_logic_vector(15 downto 0);
RESCTRL : OUT std_logic_vector(15 downto 0);
LDAC : OUT std_logic;
DataToDAC : OUT std_logic_vector(11 downto 0)
ResCtrlD: out std_logic;
ResSClk: out std_logic
);
END COMPONENT;
......@@ -1092,7 +1097,8 @@ U0_rescontrol: rescontrol PORT MAP(
DataFromDecoder => dataFromDecoder,
RESCTRL => registers(RESCTRLR),
LDAC => ResLDAC,
DataToDAC => ResCtrlDAC
ResCtrlD => ResCtrlD,
ResSClk => ResSClk
);
U0_oneshot: oneshot PORT MAP(
......@@ -1144,4 +1150,8 @@ FProtectLed <= not XProtectIn;
--CavLed <= CavOvr;
OutLed <= not configMode;
-- Dummy
RAMZZ <= (others=>'0');
DIAGZZ <= (others=>'0');
end RTL;
......@@ -9,7 +9,9 @@ entity ResControl is
DataFromDecoder: in std_logic_vector(15 downto 0);
RESCTRL: out std_logic_vector(15 downto 0);
LDAC: out std_logic;
DataToDAC : out std_logic_vector(11 downto 0));
ResCTRLD: out std_logic;
ResSClk: out std_logic
);
end ResControl;
architecture RTL of ResControl is
......@@ -20,9 +22,16 @@ signal counter: unsigned(5 downto 0);
begin
DataToDAC <= resCtrlAux(11 downto 0);
--DataToDAC <= resCtrlAux(11 downto 0);
RESCTRL <= resCtrlAux;
-- Dummy
ResCTRLD <= '0';
ResSClk <= '0';
-- End of dummy
RegProcess: process(Clk40)
begin
if Clk40'event and Clk40='1' then
......
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......@@ -56,7 +56,7 @@ xilxPAReffortLevel=synvhd, virtex2, Implementation.t_placeAndRouteDes, 104938330
_SynthFrequency=synvhd, virtex2, Synthesis.t_synthesize, 1049879617, 40
_SynthResourceSharing=synvhd, virtex2, Synthesis.t_synthesize, 1070036051, True
[STATUS-ALL]
cavitycontrolcwv3.ncdFile=WARNINGS,1105627070
cavitycontrolcwv3.ngdFile=WARNINGS,1105627041
cavitycontrolcwv3.ncdFile=WARNINGS,1105695454
cavitycontrolcwv3.ngdFile=WARNINGS,1105695435
[STRATEGY-LIST]
Normal=True
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