Commit e459f9ba authored by Javier Serrano's avatar Javier Serrano
Browse files

*** empty log message ***


git-svn-id: svn+ssh://svn.cern.ch/reps/acc-fpga/trunk2@762 0a99fbf0-06a5-4c52-8a11-fe70044ee989
parent 8d0cf41c
......@@ -202,10 +202,11 @@ COMPONENT iqcounter
);
END COMPONENT;
COMPONENT iqdemod
COMPONENT iqdemodcw
PORT(
DataInA : IN std_logic_vector(13 downto 0);
Clk80In : IN std_logic;
CorrectOn: in std_logic;
IQCount : IN std_logic_vector(1 downto 0);
IData : OUT std_logic_vector(13 downto 0);
QData : OUT std_logic_vector(13 downto 0)
......@@ -574,12 +575,13 @@ signal cavIFixed, cavQFixed: std_logic_vector(13 downto 0);
signal cavIToMod, cavQToMod: std_logic_vector(13 downto 0);
signal satDisabled: std_logic;
signal cavILongInt, cavQLongInt: std_logic_vector(26 downto 0);
signal cwMode, antiWindUp: std_logic;
signal cwMode, antiWindUp, correctOn: std_logic;
begin
cwMode <= ADSwitch(0);
antiWindUp <= ADSwitch(1);
correctOn <= ADSwitch(2);
RAM1Addr <= ram1AddrAux;
RAM1OE <= ram1OEAux;
......@@ -928,25 +930,28 @@ U0_iqcounter: iqcounter PORT MAP(
IQCount => iqCount
);
RefIQDemod: iqdemod PORT MAP(
RefIQDemod: iqdemodcw PORT MAP(
DataInA => RefIn,
Clk80In => clk80N,
CorrectOn => correctOn,
IQCount => iqCount,
IData => refI,
QData => refQ
);
FwdIQDemod: iqdemod PORT MAP(
FwdIQDemod: iqdemodcw PORT MAP(
DataInA => FwdIn,
Clk80In => clk80N,
CorrectOn => correctOn,
IQCount => iqCount,
IData => fwdI,
QData => fwdQ
);
CavIQDemod: iqdemod PORT MAP(
CavIQDemod: iqdemodcw PORT MAP(
DataInA => CavIn,
Clk80In => clk80N,
CorrectOn => correctOn,
IQCount => iqCount,
IData => cavI,
QData => cavQ
......
This diff is collapsed.
......@@ -13,7 +13,7 @@ DEVSPEEDTIME 315558000
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL Synplify (VHDL)
SYNTHESISTOOLTIME 0
SYNTHESISTOOLTIME 1088520530
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
......@@ -43,20 +43,22 @@ SOURCE ..\sources\OneShot.vhd
SOURCE ..\sources\CavityControlCW.vhd
SOURCE ..\sources\PIControllerCW.vhd
SOURCE ..\sources\SatControlCW.vhd
SOURCE ..\sources\iqdemodcw.vhd
DEPASSOC ledstest ..\sources\ledsconstraints.ucf
DEPASSOC cavitycontrol ..\sources\cavityconstraints.ucf
DEPASSOC cavitycontrolcw ..\sources\cavityCWconstraints.ucf
[Normal]
p_AutoGenFile=synvhd, virtex2, Implementation.t_genImpactFile, 1068747285, True
p_ChainDescFile=synvhd, virtex2, Implementation.t_genImpactFile, 1087824130,
xilxMapCoverMode=synvhd, virtex2, Implementation.t_map, 1070037511, Speed
xilxMapPackRegInto=synvhd, virtex2, Implementation.t_map, 1051284026, For Inputs and Outputs
xilxMapReportDetail=synvhd, virtex2, Implementation.t_map, 1070037511, False
xilxPAReffortLevel=synvhd, virtex2, Implementation.t_par, 1049383307, Medium
xilxMapCoverMode=synvhd, virtex2, VHDL.t_map, 1070037511, Speed
xilxMapPackRegInto=synvhd, virtex2, VHDL.t_map, 1051284026, For Inputs and Outputs
xilxMapReportDetail=synvhd, virtex2, VHDL.t_map, 1070037511, False
xilxMapTimingDrivenPacking=synvhd, virtex2, VHDL.t_map, 1088672628, False
xilxPAReffortLevel=synvhd, virtex2, Implementation.t_placeAndRouteDes, 1049383307, Medium
_SynthFrequency=synvhd, virtex2, Synthesis.t_synthesize, 1049879617, 40
_SynthResourceSharing=synvhd, virtex2, Synthesis.t_synthesize, 1070036051, True
[STATUS-ALL]
cavitycontrolcw.ncdFile=WARNINGS,1088154539
cavitycontrolcw.ngdFile=WARNINGS,1088154450
cavitycontrolcw.ncdFile=WARNINGS,1089114860
cavitycontrolcw.ngdFile=WARNINGS,1089107262
[STRATEGY-LIST]
Normal=True
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