VfcHdApplication.v 8.92 KB
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`timescale 1ns/100ps 

module VfcHdApplication   
#(parameter g_ApplicationVersion_b8	     = 8'h01,
            g_ApplicationReleaseDay_b8 	 = 8'h18, 
            g_ApplicationReleaseMonth_b8 = 8'h07, 
            g_ApplicationReleaseYear_b8  = 8'h16)   
(	
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
   input         BstSfpRx_i, // Comment: Differential signal
   output        BstSfpTx_o, // Comment: Differential signal
   input         EthSfpRx_i, // Comment: Differential signal
   output        EthSfpTx_o, // Comment: Differential signal
   // SFP Gbit:
   input  [ 4:1] AppSfpRx_ib4, // Comment: Differential signal
   output [ 4:1] AppSfpTx_ob4, // Comment: Differential signal
   // DDR3 SO-DIMM:
   output [ 2:0] DdrBa_ob3,
   output [ 7:0] DdrDm_ob8,
   inout  [ 7:0] DdrDqs_iob8, // Comment: Differential signal
   inout  [63:0] DdrDq_iob64,
   output [15:0] DdrA_ob16,
   output [ 1:0] DdrCk_okb2,  // Comment: Differential signal
   output [ 1:0] DdrCkE_ohb2,
   output        DdrReset_orn, 
   output        DdrRas_on,
   output        DdrCas_on,
   output        DdrWe_on,
   output [ 1:0] DdrCs_onb2,
   output [ 1:0] DdrOdt_ob2,
   input         DdrTempEvent_in,
   output        DdrI2cScl_ok,
   inout         DdrI2cSda_io,
   // TestIo:
   inout         TestIo1_io,
   inout         TestIo2_io, 
   // FMC connector:
   inout  [33:0] FmcLaP_iob34,
   inout  [33:0] FmcLaN_iob34,
   inout  [23:0] FmcHaP_iob24,
   inout  [23:0] FmcHaN_iob24,   
   inout  [21:0] FmcHbP_iob22,
   inout  [21:0] FmcHbN_iob22,
   input         FmcPrsntM2C_in, 
   output        FmcTck_ok,
   output        FmcTms_o,
   output        FmcTdi_o,
   input         FmcTdo_i,
   output        FmcTrstL_orn,
   inout         FmcScl_iok,
   inout         FmcSda_io,
   input         FmcPgM2C_in,
   output        FmcPgC2M_on, 
   input         FmcClk0M2CCmos_ik,
   input         FmcClk1M2CCmos_ik,
   inout         FmcClk2Bidir_iok, // Comment: Differential signal
   inout         FmcClk3Bidir_iok, // Comment: Differential signal
   input         FmcClkDir_i,
   output [ 9:0] FmcDpC2M_ob10, // Comment: Differential signal
   input  [ 9:0] FmcDpM2C_ib10,
   input         FmcGbtClk0M2CLeft_ik,  // Comment: Differential signal
   input         FmcGbtClk1M2CLeft_ik,  // Comment: Differential signal
   input         FmcGbtClk0M2CRight_ik, // Comment: Differential signal
   input         FmcGbtClk1M2CRight_ik, // Comment: Differential signal  
   // Clock sources and control:
   output        OeSi57x_oe,
   input         Si57xClk_ik,
   output        ClkFb_ok,
   input         ClkFb_ik,
   input         Clk20VCOx_ik,
   output        PllDac20Sync_o,
   output        PllDac25Sync_o,
   output        PllDacSclk_ok,
   output        PllDacDin_o,  
   output        PllRefScl_ok,
   inout         PllRefSda_io,
   input         PllRefInt_i,
   output        PllSourceMuxOut_ok,
   input         PllRefClkOut_ik,   // Comment: Differential reference for the Gbit lines
   input         GbitTrxClkRefR_ik, // Comment: Differential reference for the Gbit lines ~125MHz
   // SW1:
   input  [ 1:0] Switch_ib2,
   // P2 RTM:
   inout  [19:0] P2DataP_iob20, //Comment: The 0 is a clock capable input
   inout  [19:0] P2DataN_iob20,
   // P0 Timing:
   input  [ 7:0] P0HwHighByte_ib8,
   input  [ 7:0] P0HwLowByte_ib8,
   output        DaisyChain1Cntrl_o,
   output        DaisyChain2Cntrl_o,
   input         VmeP0BunchClk_ik,
   input         VmeP0Tclk_ik,
   // GPIO:
   inout  [ 4:1] GpIo_iob4,
   // Specials:
   input         PushButtonN_in,
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@ 
   // Reset:
   input         Reset_irqp,       // Comment: Reset Synchronous with the WbClk_ik
   output        ResetRequest_oqp, // Comment: Request to issue a reset 
   // WishBone:
   output        WbClk_ok,
   input         WbSlaveCyc_i,
   input         WbSlaveStb_i,
   input  [24:0] WbSlaveAdr_ib25,
   input         WbSlaveWr_i,
   input  [31:0] WbSlaveDat_ib32,
   output [31:0] WbSlaveDat_ob32,
   output        WbSlaveAck_o,   
   output        WbMasterCyc_o,
   output        WbMasterStb_o,
   output [24:0] WbMasterAdr_ob25,
   output        WbMasterWr_o,
   output [31:0] WbMasterDat_ob32,
   input  [31:0] WbMasterDat_ib32,
   input         WbMasterAck_i,
   // LED control:
   output [ 1:0] TopLed_ob2,
   output [ 3:0] BottomLed_ob4,
   // BST input:
   input         BstOn_i,
   input         BunchClk_ik,
   input         TurnClk_ip,
   input  [ 5:0] BstByteAddress_ib5,
   input  [ 7:0] BstByte_ib8,
   // Interrupt:
   output [23:0] InterruptRequest_opb24,
   // Ethernet streamer:
   output        StreamerClk_ok,
   output [31:0] StreamerData_ob32,
   output        SreamerDav_o,
   output        StreamerPckt_o,
   input         StreamerWait_i,  
   // GPIO direction:
   output        GpIo1DirOut_o,
   output        GpIo2DirOut_o,
   output        GpIo34DirOut_o   
);

//****************************
//Declarations
//****************************

wire        Clk_k;

wire        WbStbAppReleaseId, WbAckAppReleaseId;
wire [31:0] WbDatAppReleaseId_b32;
wire        WbStbCtrlReg, WbAckCtrlReg;
wire [31:0] WbDatCtrlReg_b32;
wire        WbStbStatReg, WbAckStatReg;
wire [31:0] WbDatStatReg_b32;
wire        WbStbPllRef, WbAckPllRef;
wire [31:0] WbDatPllRef_b32;
wire [31:0] Reg0Value_b32;

//****************************
//Fixed assignments
//****************************

assign OeSi57x_oe = 1'b1;

//****************************
//Clocking
//****************************

assign Clk_k    = GbitTrxClkRefR_ik; //~125MHz
assign WbClk_ok = Clk_k;

//****************************
//WB address decoder
//****************************

AddrDecoderWBApp i_AddrDecoderWbApp( 
    .Clk_ik               (Clk_k),
    .Adr_ib21             (WbSlaveAdr_ib25[20:0]),
    .Stb_i                (WbSlaveStb_i),
    .Dat_ob32             (WbSlaveDat_ob32),
    .Ack_o                (WbSlaveAck_o),
    //--
    .DatAppReleaseId_ib32 (WbDatAppReleaseId_b32),
    .AckAppReleaseId_i    (WbAckAppReleaseId),
    .StbAppReleaseId_o    (WbStbAppReleaseId),
    //--
    .DatCtrlReg_ib32      (WbDatCtrlReg_b32),
    .AckCtrlReg_i         (WbAckCtrlReg),
    .StbCtrlReg_o         (WbStbCtrlReg),
    //--
    .DatStatReg_ib32      (WbDatStatReg_b32),
    .AckStatReg_i         (WbAckStatReg),
    .StbStatReg_o         (WbStbStatReg));    

//****************************
//Release ID
//****************************

Generic4InputRegs i_AppReleaseId(
    .Rst_irq        (Reset_irqp),
    .Clk_ik         (Clk_k),
    .Cyc_i          (WbSlaveCyc_i),
    .Stb_i          (WbStbAppReleaseId),
    .Adr_ib2        (WbSlaveAdr_ib25[1:0]),
    .Dat_oab32      (WbDatAppReleaseId_b32),
    .Ack_oa         (WbAckAppReleaseId),
    .Reg0Value_ib32 ("VFC-"),
    .Reg1Value_ib32 ("HD G"),
    .Reg2Value_ib32 ("BT  "),
    .Reg3Value_ib32 ({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));

//****************************
//Example registers
//****************************

//Control register bank:
Generic4OutputRegs  #(  
    .Reg0Default     (32'hBABEB00B), 
    .Reg0AutoClrMask (32'hFFFFFFFF), 
    .Reg1Default     (32'h00000000),
    .Reg1AutoClrMask (32'hFFFFFFFF), 
    .Reg2Default     (32'h00000000),
    .Reg2AutoClrMask (32'hFFFFFFFF), 
    .Reg3Default     (32'h00000000),
    .Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs (
    .Clk_ik          (Clk_k),
    .Rst_irq         (Reset_irqp),
    .Cyc_i           (WbSlaveCyc_i),
    .Stb_i           (WbStbCtrlReg),
    .We_i            (WbSlaveWr_i),
    .Adr_ib2         (WbSlaveAdr_ib25[1:0]),
    .Dat_ib32        (WbSlaveDat_ib32),
    .Dat_oab32       (WbDatCtrlReg_b32),
    .Ack_oa          (WbAckCtrlReg),
    //--
    .Reg0Value_ob32  (Reg0Value_b32),
    .Reg1Value_ob32  (),
    .Reg2Value_ob32  (),
    .Reg3Value_ob32  ());

//Status registers bank:
Generic4InputRegs i_StatusRegs  (
    .Clk_ik         (Clk_k),
    .Rst_irq        (Reset_irqp),
    .Cyc_i          (WbSlaveCyc_i),
    .Stb_i          (WbStbStatReg),
    .Adr_ib2        (WbSlaveAdr_ib25[1:0]),
    .Dat_oab32      (WbDatStatReg_b32),
    .Ack_oa         (WbAckStatReg),
    //--          
    .Reg0Value_ib32 (Reg0Value_b32),
    .Reg1Value_ib32 (32'hCAFEAC1D),
    .Reg2Value_ib32 (32'hACDCDEAD),
    .Reg3Value_ib32 (32'hFEEDBEEF)); 
    
//****************************
//PLL Ref (Si5338) I2C control
//****************************

I2cMasterWb #(
    .g_CycleLenght (10'd256)) 
i_I2cPllRef	(   
	.Clk_ik        (Clk_k),
	.Rst_irq       (Reset_irqp),
	.Cyc_i         (WbSlaveCyc_i),
	.Stb_i         (WbStbStatReg),
	.We_i          (WbSlaveWr_i),
	.Adr_ib2       (WbSlaveAdr_ib25[1:0]),
	.Dat_ib32      (WbSlaveDat_ib32),
	.Dat_oab32     (WbDatPllRef_b32),
	.Ack_oa        (WbAckPllRef),
    .Scl_ioz       (PllRefScl_ok),  
	.Sda_ioz       (PllRefSda_io));    
    
//****************************
// GBT-FPGA example design
//****************************    
    
    
    
    
    
    
    
    
    
    
    
    
    
    
    
    
    
    
    
endmodule