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Dimitris Lampridis
VFC-HD
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VFC-HD
Hdl
FpgaModules
SystemSpecific
AlteraPhy
wr_arria5_phy
Manifest.py
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[WR-dev] First working WR PTP core, tested with fiber between a WR switch and VFC-HD
· 736696cc
Dimitris Lampridis
authored
Aug 09, 2016
TODO: One failed message in timing analyzer, does not seem to affect basic operation
736696cc