Commit 01d06d7e authored by Manoel Barros Marin's avatar Manoel Barros Marin
Browse files

- Fixed bugs in some IOs

parent a214d8fa
......@@ -68,7 +68,7 @@ reg [ 2:0] State_qb3, NextState_ab3;
//======================================= User Logic =======================================\\
//==== Example of Secuential logic ====\\
//==== Example of Sequential logic ====\\
// Example of synchronous logic with asynchronous reset:
always @(posedge Clock_ik or negedge Reset_iran)
......
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'hb1,
g_ApplicationReleaseDay_b8 = 8'h01,
g_ApplicationReleaseMonth_b8 = 8'h03,
#(parameter g_ApplicationVersion_b8 = 8'hb2,
g_ApplicationReleaseDay_b8 = 8'h28,
g_ApplicationReleaseMonth_b8 = 8'h04,
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
......@@ -49,14 +49,14 @@ module VfcHdApplication
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,
output FmcScl_ok,
inout FmcScl_iok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
input FmcClk2Bidir_ik, //differential signal
input FmcClk3Bidir_ik, //differential signal
inout FmcClk2Bidir_iok, //differential signal
inout FmcClk3Bidir_iok, //differential signal
input FmcClkDir_i,
output [9:0] FmcDpC2M_ob10, //diff output
input [9:0] FmcDpM2C_ib10,
......
......@@ -30,7 +30,7 @@ module fmc_test_wrapper (
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,//Note!! NC
output FmcScl_ok,
inout FmcScl_iok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
......@@ -38,8 +38,8 @@ module fmc_test_wrapper (
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
input FmcClk2Bidir_ik, //differential signal
input FmcClk3Bidir_ik, //differential signal
inout FmcClk2Bidir_iok, //differential signal
inout FmcClk3Bidir_iok, //differential signal
input FmcGbtClk0M2CLeft_ik, //differential signal
input FmcGbtClk1M2CLeft_ik, //differential signal
......@@ -478,7 +478,7 @@ module fmc_test_wrapper (
.Scl_ioz(FmcSclMaster),
.Sda_ioz(FmcSdaMaster));
assign FmcScl_ok = FmcI2cOutCtrl ? FmcSclReg : FmcSclMaster;
assign FmcScl_iok = FmcI2cOutCtrl ? FmcSclReg : FmcSclMaster;
assign FmcSda_io = FmcI2cOutCtrl ? FmcSdaReg : FmcSdaMaster;
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@
......@@ -552,7 +552,7 @@ module fmc_test_wrapper (
.rd_level(PcFmcClk1M2CCmosFifoELvl_b2));
//FmcClk2Bidir:
always @(posedge FmcClk2Bidir_ik)
always @(posedge FmcClk2Bidir_iok)
if (Reset_irqp) begin
FmcClk2BidirDivider_c3 <= #1 3'b0;
end else begin
......@@ -585,7 +585,7 @@ module fmc_test_wrapper (
.rd_level(PcFmcClk2BidirFifoELvl_b2));
//FmcClk3Bidir:
always @(posedge FmcClk3Bidir_ik)
always @(posedge FmcClk3Bidir_iok)
if (Reset_irqp) begin
FmcClk3BidirDivider_c3 <= #1 3'b0;
end else begin
......@@ -764,9 +764,9 @@ module fmc_test_wrapper (
always @* begin
case (FmcClkMux_ctrl[2])
3'b100 : begin TestIo2_a = FmcClk2Bidir_ik; end
3'b100 : begin TestIo2_a = FmcClk2Bidir_iok; end
3'b101 : begin TestIo2_a = FmcGbtClk0M2CRight_ik; end
3'b110 : begin TestIo2_a = FmcClk3Bidir_ik; end
3'b110 : begin TestIo2_a = FmcClk3Bidir_iok; end
3'b111 : begin TestIo2_a = FmcGbtClk1M2CRight_ik; end
default: begin TestIo2_a = 1'b0; end
endcase
......
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'ha3,
g_ApplicationReleaseDay_b8 = 8'h18,
g_ApplicationReleaseMonth_b8 = 8'h06,
g_ApplicationReleaseYear_b8 = 8'h15)
#(parameter g_ApplicationVersion_b8 = 8'ha4,
g_ApplicationReleaseDay_b8 = 8'h28,
g_ApplicationReleaseMonth_b8 = 8'h04,
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
......@@ -49,14 +49,14 @@ module VfcHdApplication
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,
output FmcScl_ok,
inout FmcSda_io,
inout FmcScl_iok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
input FmcClk2Bidir_ik, //differential signal
input FmcClk3Bidir_ik, //differential signal
inout FmcClk2Bidir_iok, //differential signal
inout FmcClk3Bidir_iok, //differential signal
input FmcClkDir_i,
output [9:0] FmcDpC2M_ob10, //diff output
input [9:0] FmcDpM2C_ib10,
......@@ -489,15 +489,15 @@ fmc_test_wrapper i_FmcTest(
.FmcTdi_o (FmcTdi_o),
.FmcTdo_i (FmcTdo_i),
.FmcTrstL_orn (FmcTrstL_orn),
.FmcScl_ok (FmcScl_ok),
.FmcScl_iok (FmcScl_iok),
.FmcSda_io (FmcSda_io),
.FmcPgM2C_in (FmcPgM2C_in),
.FmcPgC2M_on (FmcPgC2M_on),
.FmcClkDir_i (FmcClkDir_i),
.FmcClk0M2CCmos_ik (FmcClk0M2CCmos_ik),
.FmcClk1M2CCmos_ik (FmcClk1M2CCmos_ik),
.FmcClk2Bidir_ik (FmcClk2Bidir_ik),
.FmcClk3Bidir_ik (FmcClk3Bidir_ik),
.FmcClk2Bidir_iok (FmcClk2Bidir_iok),
.FmcClk3Bidir_iok (FmcClk3Bidir_iok),
.FmcGbtClk0M2CLeft_ik (FmcGbtClk0M2CLeft_ik),
.FmcGbtClk1M2CLeft_ik (FmcGbtClk1M2CLeft_ik),
.FmcGbtClk0M2CRight_ik(FmcGbtClk0M2CRight_ik),
......
......@@ -93,14 +93,14 @@ module VfcHdTop
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,
output FmcScl_ok,
inout FmcScl_iok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
input FmcClk2Bidir_ik, //differential signal
input FmcClk3Bidir_ik, //differential signal
inout FmcClk2Bidir_iok, //differential signal
inout FmcClk3Bidir_iok, //differential signal
input FmcClkDir_i,
output [9:0] FmcDpC2M_ob10, //diff output
input [9:0] FmcDpM2C_ib10,
......@@ -314,14 +314,14 @@ VfcHdApplication i_VfcHdApplication
.FmcTdi_o(FmcTdi_o),
.FmcTdo_i(FmcTdo_i),
.FmcTrstL_orn(FmcTrstL_orn),
.FmcScl_ok(FmcScl_ok),
.FmcScl_iok(FmcScl_iok),
.FmcSda_io(FmcSda_io),
.FmcPgM2C_in(FmcPgM2C_in),
.FmcPgC2M_on(FmcPgC2M_on),
.FmcClk0M2CCmos_ik(FmcClk0M2CCmos_ik),
.FmcClk1M2CCmos_ik(FmcClk1M2CCmos_ik),
.FmcClk2Bidir_ik(FmcClk2Bidir_ik),
.FmcClk3Bidir_ik(FmcClk3Bidir_ik),
.FmcClk2Bidir_iok(FmcClk2Bidir_iok),
.FmcClk3Bidir_iok(FmcClk3Bidir_iok),
.FmcClkDir_i(FmcClkDir_i),
.FmcDpC2M_ob10(FmcDpC2M_ob10),
.FmcDpM2C_ib10(FmcDpM2C_ib10),
......
......@@ -442,8 +442,6 @@ LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
TDB_DoubleClick = Edit
TDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
......@@ -457,4 +455,4 @@ DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 10
Project_Minor_Version = 4
Project_Minor_Version = 1
......@@ -50,7 +50,7 @@ if "$no_sc == 1" {
echo "Smart compilation not possible or not enabled. Running full compilation..."
# Deleting pre-existing libraries
if {[file exists work]} {vdel -all -lib work}
# Creating and working directory:
# Creating and mapping working directory:
vlib work
vmap work work
# Maping Altera libraries:
......
......@@ -199,14 +199,14 @@ VfcHd_v2_0
.FmcTdi_o(),
.FmcTdo_i(1'b0),
.FmcTrstL_orn(),
.FmcScl_ok(),
.FmcScl_iok(),
.FmcSda_io(),
.FmcPgM2C_in(1'b0),
.FmcPgC2M_on(),
.FmcClk0M2CCmos_ik(1'b0),
.FmcClk1M2CCmos_ik(1'b0),
.FmcClk2Bidir_ik(1'b0),
.FmcClk3Bidir_ik(1'b0),
.FmcClk2Bidir_iok(),
.FmcClk3Bidir_iok(),
.FmcClkDir_i(1'b0),
.FmcDpC2M_ob10(),
.FmcDpM2C_ib10(10'h0),
......
......@@ -160,8 +160,8 @@ VfcHd_v2_0
.FmcPgC2M_on(),
.FmcClk0M2CCmos_ik(1'b0),
.FmcClk1M2CCmos_ik(1'b0),
.FmcClk2Bidir_ik(1'b0),
.FmcClk3Bidir_ik(1'b0),
.FmcClk2Bidir_iok(),
.FmcClk3Bidir_iok(),
.FmcClkDir_i(1'b0),
.FmcDpC2M_ob10(),
.FmcDpM2C_ib10(10'h0),
......
......@@ -53,20 +53,20 @@ module VfcHd_v2_0
input FmcPrsntM2C_in,
output FmcTck_ok,
output FmcTms_o,
input FmcTdi_o,
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,
inout FmcScl_ok,
inout FmcScl_iok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
inout FmcClk2Bidir_ik,
inout [9:0] FmcClk3Bidir_ik,
input [9:0] FmcClkDir_i,
output FmcDpC2M_ob10,
input FmcDpM2C_ib10,
inout FmcClk2Bidir_iok,
inout FmcClk3Bidir_iok,
input FmcClkDir_i,
output [ 9:0] FmcDpC2M_ob10,
input [ 9:0] FmcDpM2C_ib10,
input FmcGbtClk0M2CLeft_ik,
input FmcGbtClk1M2CLeft_ik,
input FmcGbtClk0M2CRight_ik,
......@@ -196,14 +196,14 @@ VfcHdTop
.FmcTdi_o(FmcTdi_o),
.FmcTdo_i(FmcTdo_i),
.FmcTrstL_orn(FmcTrstL_orn),
.FmcScl_ok(FmcScl_ok),
.FmcScl_iok(FmcScl_iok),
.FmcSda_io(FmcSda_io),
.FmcPgM2C_in(FmcPgM2C_in),
.FmcPgC2M_on(FmcPgC2M_on),
.FmcClk0M2CCmos_ik(FmcClk0M2CCmos_ik),
.FmcClk1M2CCmos_ik(FmcClk1M2CCmos_ik),
.FmcClk2Bidir_ik(FmcClk2Bidir_ik),
.FmcClk3Bidir_ik(FmcClk3Bidir_ik),
.FmcClk2Bidir_iok(FmcClk2Bidir_iok),
.FmcClk3Bidir_iok(FmcClk3Bidir_iok),
.FmcClkDir_i(FmcClkDir_i),
.FmcDpC2M_ob10(FmcDpC2M_ob10),
.FmcDpM2C_ib10(FmcDpM2C_ib10),
......
......@@ -154,14 +154,14 @@ VfcHd_v2_0
.FmcTdi_o(),
.FmcTdo_i(1'b0),
.FmcTrstL_orn(),
.FmcScl_ok(),
.FmcScl_iok(),
.FmcSda_io(),
.FmcPgM2C_in(1'b0),
.FmcPgC2M_on(),
.FmcClk0M2CCmos_ik(1'b0),
.FmcClk1M2CCmos_ik(1'b0),
.FmcClk2Bidir_ik(1'b0),
.FmcClk3Bidir_ik(1'b0),
.FmcClk2Bidir_iok(),
.FmcClk3Bidir_iok(),
.FmcClkDir_i(1'b0),
.FmcDpC2M_ob10(),
.FmcDpM2C_ib10(10'h0),
......
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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