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Commit 0717ca14 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[WR-dev] cleaned up almost all Synthesis, Fitter and TimeQuest warnings on... 

[WR-dev] cleaned up almost all Synthesis, Fitter and TimeQuest warnings on Quartus 15.1 before starting adding new modules
parent b60789e3
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Hdl/FpgaModules/ApplicationSpecific/BaseProject/VfcHdApplication.v
View file @ 0717ca14
......@@ -9,6 +9,7 @@ module VfcHdApplication
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
/* -----\/----- EXCLUDED -----\/-----
input BstSfpRx_i, //Differential
output BstSfpTx_o, //Differential
input EthSfpRx_i, //Differential
......@@ -64,8 +65,10 @@ module VfcHdApplication
input FmcGbtClk1M2CLeft_ik, //differential signal
input FmcGbtClk0M2CRight_ik, //differential signal
input FmcGbtClk1M2CRight_ik, //differential signal
-----/\----- EXCLUDED -----/\----- */
//Clock sources and control
output OeSi57x_oe,
/* -----\/----- EXCLUDED -----\/-----
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
......@@ -79,7 +82,9 @@ module VfcHdApplication
inout PllRefInt_i,
output PllSourceMuxOut_ok,
input PllRefClkOut_ik, //Differential reference for the Gbit lines
-----/\----- EXCLUDED -----/\----- */
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines ~125MHz
/* -----\/----- EXCLUDED -----\/-----
//SW1
input [1:0] Switch_ib2,
//P2 RTM
......@@ -96,12 +101,15 @@ module VfcHdApplication
inout [4:1] GpIo_iob4,
//Specials
input PushButtonN_in,
-----/\----- EXCLUDED -----/\----- */
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
//Reset
input Reset_irqp, //Reset Synchronous with the WbClk_ik
/* -----\/----- EXCLUDED -----\/-----
output ResetRequest_oqp, //Request to issue a reset
-----/\----- EXCLUDED -----/\----- */
//WishBone
output WbClk_ok,
input WbSlaveCyc_i,
......@@ -111,16 +119,20 @@ module VfcHdApplication
input [31:0] WbSlaveDat_ib32,
output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o,
/* -----\/----- EXCLUDED -----\/-----
output WbMasterCyc_o,
output WbMasterStb_o,
output [24:0] WbMasterAdr_ob25,
output WbMasterWr_o,
output [31:0] WbMasterDat_ob32,
-----/\----- EXCLUDED -----/\----- */
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
//LED control
/* -----\/----- EXCLUDED -----\/-----
output [1:0] TopLed_ob2,
output [3:0] BottomLed_ob4,
-----/\----- EXCLUDED -----/\----- */
//BST input
input BstOn_i,
input BunchClk_ik,
......@@ -128,17 +140,21 @@ module VfcHdApplication
input [5:0] BstByteAddress_ib5,
input [7:0] BstByte_ib8,
//Interrupt
/* -----\/----- EXCLUDED -----\/-----
output [23:0] InterruptRequest_opb24,
//Ethernet streamer
output StreamerClk_ok,
output [31:0] StreamerData_ob32,
output SreamerDav_o,
output StreamerPckt_o,
input StreamerWait_i,
-----/\----- EXCLUDED -----/\----- */
input StreamerWait_i
//GPIO direction
/* -----\/----- EXCLUDED -----\/-----
output GpIo1DirOut_o,
output GpIo2DirOut_o,
output GpIo34DirOut_o
-----/\----- EXCLUDED -----/\----- */
);
//****************************
......@@ -257,4 +273,4 @@ Generic4InputRegs i_StatusRegs (
.Reg2Value_ib32 (Reg2Value_b32),
.Reg3Value_ib32 (Reg3Value_b32));
endmodule
\ No newline at end of file
endmodule
Hdl/FpgaModules/GeneralPurpose/Ip_OpenCores/generic_dpram.v
View file @ 0717ca14
......@@ -106,7 +106,7 @@
module generic_dpram(
// Generic synchronous dual-port RAM interface
rclk, rrst, rce, oe, raddr, do,
rclk, rrst, rce, oe, raddr, dout,
wclk, wrst, wce, we, waddr, di
);
......@@ -125,7 +125,7 @@ module generic_dpram(
input rce; // read port chip enable, active high
input oe; // output enable, active high
input [aw-1:0] raddr; // read address
output [dw-1:0] do; // data output
output [dw-1:0] dout; // data output
// write port
input wclk; // write clock, rising edge trigger
......@@ -154,7 +154,7 @@ module generic_dpram(
if (rce)
ra <= #1 raddr;
assign do = mem[ra];
assign dout = mem[ra];
// write operation
always@(posedge wclk)
......@@ -177,7 +177,7 @@ module generic_dpram(
.ADDRA(raddr),
.DIA( {dw{1'b0}} ),
.WEA(1'b0),
.DOA(do),
.DOA(dout),
// write port
.CLKB(wclk),
......@@ -206,7 +206,7 @@ module generic_dpram(
.rdclock(rclk),
.rdclocken(rce),
.rdaddress(raddr),
.q(do),
.q(dout),
// write port
.wrclock(wclk),
......@@ -231,7 +231,7 @@ module generic_dpram(
//
art_hsdp #(dw, 1<<aw, aw) artisan_sdp(
// read port
.qa(do),
.qa(dout),
.clka(rclk),
.cena(~rce),
.wena(1'b1),
......@@ -267,7 +267,7 @@ module generic_dpram(
.ra(raddr),
.wa(waddr),
.di(di),
.do(do)
.do(dout)
);
`else
......@@ -287,7 +287,7 @@ module generic_dpram(
.DA( {dw{1'b0}} ),
.WEA(1'b0),
.OEA(oe),
.QA(do),
.QA(dout),
// write port
.CLKB(wclk),
......@@ -314,7 +314,7 @@ module generic_dpram(
//
// Data output drivers
//
assign do = (oe & rce) ? do_reg : {dw{1'bz}};
assign dout = (oe & rce) ? do_reg : {dw{1'bz}};
// read operation
always @(posedge rclk)
......
Hdl/FpgaModules/GeneralPurpose/Ip_OpenCores/generic_fifo_dc_gray.v
View file @ 0717ca14
......@@ -225,7 +225,7 @@ generic_dpram #(aw,dw) u0(
.rce( 1'b1 ),
.oe( 1'b1 ),
.raddr( rp_bin[aw-1:0] ),
.do( dout ),
.dout( dout ),
.wclk( wr_clk ),
.wrst( !wr_rst ),
.wce( 1'b1 ),
......
Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v
View file @ 0717ca14
......@@ -194,4 +194,4 @@ always @* begin
endcase
end
endmodule
\ No newline at end of file
endmodule
Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
View file @ 0717ca14
......@@ -12,8 +12,8 @@ module VfcHdSystem
// VME interface
input VmeAs_in,
input [5:0] VmeAm_ib6,
inout [31:1] VmeA_iob31,
inout VmeLWord_ion,
input [31:1] VmeA_iob31,
input VmeLWord_ion,
output VmeAOe_oen,
output VmeADir_o,
input [1:0] VmeDs_inb2,
......@@ -26,7 +26,9 @@ module VfcHdSystem
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
/* -----\/----- EXCLUDED -----\/-----
input VmeSysClk_ik,
-----/\----- EXCLUDED -----/\----- */
input VmeSysReset_irn,
//System SFPs Gbit lanes
// input BstSfpRx_i, //Differential
......@@ -42,10 +44,12 @@ module VfcHdSystem
input I2CIoExpIntApp34_in,
input I2CIoExpIntBstEth_in,
input I2CIoExpIntBlmIn_in,
/* -----\/----- EXCLUDED -----\/-----
//BST
input BstDataIn_i,
input CdrClkOut_ik,
input CdrDataOut_i,
-----/\----- EXCLUDED -----/\----- */
//ADC Voltage monitoring
input VAdcDout_i,
output VAdcDin_o,
......@@ -57,18 +61,24 @@ module VfcHdSystem
output VadjCs_o,
output VadjSclk_ok,
output VadjDin_o,
/* -----\/----- EXCLUDED -----\/-----
output VfmcEnableN_oen,
-----/\----- EXCLUDED -----/\----- */
//SW1
input [4:0] NoGa_ib5,
input UseGa_i,
/* -----\/----- EXCLUDED -----\/-----
//Pcb Revision resistor network
input [7:0] PcbRev_ib7,
-----/\----- EXCLUDED -----/\----- */
//WR PROM
inout WrPromSda_io,
output WrPromScl_ok,
//Specials
inout TempIdDq_ioz,
/* -----\/----- EXCLUDED -----\/-----
output ResetFpgaConfigN_orn,
-----/\----- EXCLUDED -----/\----- */
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
......@@ -89,17 +99,21 @@ module VfcHdSystem
input [24:0] WbSlaveAdr_ib25,
input WbSlaveWr_i,
input [31:0] WbSlaveDat_ib32,
/* -----\/----- EXCLUDED -----\/-----
output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o,
-----/\----- EXCLUDED -----/\----- */
//LED control
input [1:0] TopLed_ib2,
input [3:0] BottomLed_ib4,
/* -----\/----- EXCLUDED -----\/-----
//BST output
output BstOn_o,
output BunchClk_ok,
output TurnClk_op,
output [7:0] BstByte_ob8,
output [5:0] BstByteAddress_ob5,
-----/\----- EXCLUDED -----/\----- */
//Interrupt
input [23:0] InterruptRequest_ipb24,
//Ethernet streamer
......@@ -107,7 +121,9 @@ module VfcHdSystem
input [31:0] StreamerData_ib32,
input SreamerDav_i,
input StreamerPckt_i,
/* -----\/----- EXCLUDED -----\/-----
output StreamerWait_o,
-----/\----- EXCLUDED -----/\----- */
//GPIO direction
input GpIo1DirOut_i,
input GpIo2DirOut_i,
......@@ -291,7 +307,9 @@ SpiMasterWB i_SpiMaster(
.Adr_ib3(WbAdr_b22[2:0]),
.Dat_ib32(WbDatMoSi_b32),
.Dat_oab32(WbDatSpiMaster_b32),
.Ack_oa(WbAckSpiMaster),
.Ack_oa(WbAckSpiMaster),
.WaitingNewData_o(),
.ModuleIdle_o(),
.SClk_o(SpiClk_k),
.MoSi_o(SpiMoSi),
.MiSo_ib32(SpiMiSo_b32),
......@@ -406,4 +424,4 @@ end
endmodule
\ No newline at end of file
endmodule
Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v
View file @ 0717ca14
......@@ -100,7 +100,9 @@ generic_fifo_dc_gray #(.dw(32), .aw(g_FifoAddressWidth))
.dout(IntSourceFifoOut_b32),
.re(IntSourceFifoRead),
.full(IntSourceFifoFull),
.empty(IntSourceFifoEmpty));
.empty(IntSourceFifoEmpty),
.wr_level(),
.rd_level());
assign IntSourceToRead_o = ~IntSourceFifoEmpty;
......@@ -119,4 +121,4 @@ always @(posedge Clk_ik) begin
endcase
end
endmodule
\ No newline at end of file
endmodule
Hdl/FpgaModules/VfcHdTop.v
View file @ 0717ca14
......@@ -5,8 +5,8 @@ module VfcHdTop
//VME interface
input VmeAs_in,
input [5:0] VmeAm_ib6,
inout [31:1] VmeA_iob31,
inout VmeLWord_ion,
input [31:1] VmeA_iob31,
input VmeLWord_ion,
output VmeAOe_oen,
output VmeADir_o,
input [1:0] VmeDs_inb2,
......@@ -19,8 +19,11 @@ module VfcHdTop
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
/* -----\/----- EXCLUDED -----\/-----
input VmeSysClk_ik,
-----/\----- EXCLUDED -----/\----- */
input VmeSysReset_irn,
/* -----\/----- EXCLUDED -----\/-----
//SFP Gbit
input [4:1] AppSfpRx_ib4, //Differential
output [4:1] AppSfpTx_ob4, //Differential
......@@ -28,7 +31,9 @@ module VfcHdTop
output BstSfpTx_o, //Differential
input EthSfpRx_i, //Differential
output EthSfpTx_o, //Differential
-----/\----- EXCLUDED -----/\----- */
//DDR3
/* -----\/----- EXCLUDED -----\/-----
output [15:0] Ddr3AA_ob16,
output [2:0] Ddr3ABa_ob3,
output Ddr3ACk_ok, //differential signals
......@@ -62,6 +67,7 @@ module VfcHdTop
//TestIo
inout TestIo1_io,
inout TestIo2_io,
-----/\----- EXCLUDED -----/\----- */
//I2C Mux and IO expanders
inout I2cMuxSda_io,
output I2cMuxScl_ok,
......@@ -71,15 +77,18 @@ module VfcHdTop
input I2CIoExpIntApp34_in,
input I2CIoExpIntBstEth_in,
input I2CIoExpIntBlmIn_in,
/* -----\/----- EXCLUDED -----\/-----
//BST
input BstDataIn_i,
input CdrClkOut_ik,
input CdrDataOut_i,
-----/\----- EXCLUDED -----/\----- */
//ADC Voltage monitoring
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_o,
output VAdcSclk_ok,
/* -----\/----- EXCLUDED -----\/-----
//FMC connector
inout [33:0]FmcLaP_iob34,
inout [33:0]FmcLaN_iob34,
......@@ -108,8 +117,10 @@ module VfcHdTop
input FmcGbtClk1M2CLeft_ik, //differential signal
input FmcGbtClk0M2CRight_ik, //differential signal
input FmcGbtClk1M2CRight_ik, //differential signal
-----/\----- EXCLUDED -----/\----- */
//Clock sources and control
output OeSi57x_oe,
/* -----\/----- EXCLUDED -----\/-----
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
......@@ -123,15 +134,19 @@ module VfcHdTop
inout PllRefInt_i,
output PllSourceMuxOut_ok,
input PllRefClkOut_ik, //Differential reference for the Gbit lines
-----/\----- EXCLUDED -----/\----- */
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines
//Fmc Voltage control
output VadjCs_o,
output VadjSclk_ok,
output VadjDin_o,
/* -----\/----- EXCLUDED -----\/-----
output VfmcEnableN_oen,
-----/\----- EXCLUDED -----/\----- */
//SW1
input [4:0] NoGa_ib5,
input UseGa_i,
/* -----\/----- EXCLUDED -----\/-----
input [1:0] Switch_ib2,
//Pcb Revision resistor network
input [7:0] PcbRev_ib7,
......@@ -145,15 +160,20 @@ module VfcHdTop
output DaisyChain2Cntrl_o,
input VmeP0BunchClk_ik,
input VmeP0Tclk_ik,
-----/\----- EXCLUDED -----/\----- */
//WR PROM
inout WrPromSda_io,
output WrPromScl_ok,
/* -----\/----- EXCLUDED -----\/-----
//GPIO
inout [4:1] GpIo_iob4,
//Miscellaneous:
input PushButtonN_in,
inout TempIdDq_ioz,
-----/\----- EXCLUDED -----/\----- */
inout TempIdDq_ioz
/* -----\/----- EXCLUDED -----\/-----
output ResetFpgaConfigN_orn
-----/\----- EXCLUDED -----/\----- */
);
//@@@@@@@@@@@@@@@@@@@
......@@ -202,7 +222,9 @@ VfcHdSystem i_VfcHdSystem(
.VmeIack_in(VmeIack_in),
.VmeIackIn_in(VmeIackIn_in),
.VmeIackOut_on(VmeIackOut_on),
/* -----\/----- EXCLUDED -----\/-----
.VmeSysClk_ik(VmeSysClk_ik),
-----/\----- EXCLUDED -----/\----- */
.VmeSysReset_irn(VmeSysReset_irn),
// .BstSfpRx_i(BstSfpRx_i),
// .BstSfpTx_o(BstSfpTx_o),
......@@ -216,9 +238,11 @@ VfcHdSystem i_VfcHdSystem(
.I2CIoExpIntApp34_in(I2CIoExpIntApp34_in),
.I2CIoExpIntBstEth_in(I2CIoExpIntBstEth_in),
.I2CIoExpIntBlmIn_in(I2CIoExpIntBlmIn_in),
/* -----\/----- EXCLUDED -----\/-----
.BstDataIn_i(BstDataIn_i),
.CdrClkOut_ik(CdrClkOut_ik),
.CdrDataOut_i(CdrDataOut_i),
-----/\----- EXCLUDED -----/\----- */
.VAdcDout_i(VAdcDout_i),
.VAdcDin_o(VAdcDin_o),
.VAdcCs_o(VAdcCs_o),
......@@ -227,14 +251,20 @@ VfcHdSystem i_VfcHdSystem(
.VadjCs_o(VadjCs_o),
.VadjSclk_ok(VadjSclk_ok),
.VadjDin_o(VadjDin_o),
/* -----\/----- EXCLUDED -----\/-----
.VfmcEnableN_oen(VfmcEnableN_oen),
-----/\----- EXCLUDED -----/\----- */
.NoGa_ib5(NoGa_ib5),
.UseGa_i(UseGa_i),
/* -----\/----- EXCLUDED -----\/-----
.PcbRev_ib7(PcbRev_ib7),
-----/\----- EXCLUDED -----/\----- */
.WrPromSda_io(WrPromSda_io),
.WrPromScl_ok(WrPromScl_ok),
.TempIdDq_ioz(TempIdDq_ioz),
/* -----\/----- EXCLUDED -----\/-----
.ResetFpgaConfigN_orn(ResetFpgaConfigN_orn),
-----/\----- EXCLUDED -----/\----- */
//CONNECTIONS SYSTAM<->APPLICATION
.Reset_orqp(Reset_rqp),
.ResetRequest_iqp(ResetRequest_qp),
......@@ -251,21 +281,27 @@ VfcHdSystem i_VfcHdSystem(
.WbSlaveAdr_ib25(Wb2Adr_b25),
.WbSlaveWr_i(Wb2Wr),
.WbSlaveDat_ib32(Wb2DatMosi_b32),
/* -----\/----- EXCLUDED -----\/-----
.WbSlaveDat_ob32(Wb2DatMiso_b32),
.WbSlaveAck_o(Wb2Ack),
-----/\----- EXCLUDED -----/\----- */
.TopLed_ib2(TopLed_b2),
.BottomLed_ib4(BottomLed_b4),
/* -----\/----- EXCLUDED -----\/-----
.BstOn_o(BstOn),
.BunchClk_ok(BunchClk_k),
.TurnClk_op(TurnClk_p),
.BstByteAddress_ob5(BstByteAddress_b5),
.BstByte_ob8(BstByte_b8),
-----/\----- EXCLUDED -----/\----- */
.InterruptRequest_ipb24(InterruptRequest_pb24),
.StreamerClk_ik(StreamerClk_k),
.StreamerData_ib32(StreamerData_b32),
.SreamerDav_i(SreamerDav),
.StreamerPckt_i(StreamerPckt),
/* -----\/----- EXCLUDED -----\/-----
.StreamerWait_o(StreamerWait),
-----/\----- EXCLUDED -----/\----- */
.GpIo1DirOut_i(GpIo1DirOut),
.GpIo2DirOut_i(GpIo2DirOut),
.GpIo34DirOut_i(GpIo34DirOut));
......@@ -277,10 +313,12 @@ VfcHdSystem i_VfcHdSystem(
VfcHdApplication i_VfcHdApplication
(
//DIRECT CONNECTIONS TO THE FPGA IOs
/* -----\/----- EXCLUDED -----\/-----
.BstSfpRx_i(BstSfpRx_i),
.BstSfpTx_o(BstSfpTx_o),
.EthSfpRx_i(EthSfpRx_i),
.EthSfpTx_o(EthSfpTx_o),
-----/\----- EXCLUDED -----/\----- */
//---
/* .AppSfpRx_ib4(AppSfpRx_ib4),
.AppSfpTx_ob4(AppSfpTx_ob4),
......@@ -300,6 +338,7 @@ VfcHdApplication i_VfcHdApplication
.DdrTempEvent_in(DdrTempEvent_in),
.DdrI2cScl_ok(DdrI2cScl_ok),
.DdrI2cSda_io(DdrI2cSda_io), */
/* -----\/----- EXCLUDED -----\/-----
.TestIo1_io(TestIo1_io),
.TestIo2_io(TestIo2_io),
.FmcLaP_iob34(FmcLaP_iob34),
......@@ -329,7 +368,9 @@ VfcHdApplication i_VfcHdApplication
.FmcGbtClk1M2CLeft_ik(FmcGbtClk1M2CLeft_ik),
.FmcGbtClk0M2CRight_ik(FmcGbtClk0M2CRight_ik),
.FmcGbtClk1M2CRight_ik(FmcGbtClk1M2CRight_ik),
-----/\----- EXCLUDED -----/\----- */
.OeSi57x_oe(OeSi57x_oe),
/* -----\/----- EXCLUDED -----\/-----
.Si57xClk_ik(Si57xClk_ik),
.ClkFb_ok(ClkFb_ok),
.ClkFb_ik(ClkFb_ik),
......@@ -343,7 +384,9 @@ VfcHdApplication i_VfcHdApplication
.PllRefInt_i(PllRefInt_i),
.PllSourceMuxOut_ok(PllSourceMuxOut_ok),
.PllRefClkOut_ik(PllRefClkOut_ik),
-----/\----- EXCLUDED -----/\----- */
.GbitTrxClkRefR_ik(GbitTrxClkRefR_ik),
/* -----\/----- EXCLUDED -----\/-----
.Switch_ib2(Switch_ib2),
.P2DataP_iob20(P2DataP_iob20),
.P2DataN_iob20(P2DataN_iob20),
......@@ -355,9 +398,12 @@ VfcHdApplication i_VfcHdApplication
.VmeP0Tclk_ik(VmeP0Tclk_ik),
.GpIo_iob4(GpIo_iob4),
.PushButtonN_in(PushButtonN_in),
-----/\----- EXCLUDED -----/\----- */
//CONNECTIONS SYSTAM<->APPLICATION
.Reset_irqp(Reset_rqp),
/* -----\/----- EXCLUDED -----\/-----
.ResetRequest_oqp(ResetRequest_qp),
-----/\----- EXCLUDED -----/\----- */
.WbClk_ok(WbClk_k),
.WbSlaveCyc_i(Wb1Cyc),
.WbSlaveStb_i(Wb1Stb),
......@@ -366,29 +412,37 @@ VfcHdApplication i_VfcHdApplication
.WbSlaveDat_ib32(Wb1DatMosi_b32),
.WbSlaveDat_ob32(Wb1DatMiso_b32),
.WbSlaveAck_o(Wb1Ack),
/* -----\/----- EXCLUDED -----\/-----
.WbMasterCyc_o(Wb2Cyc),
.WbMasterStb_o(Wb2Stb),
.WbMasterAdr_ob25(Wb2Adr_b25),
.WbMasterWr_o(Wb2Wr),
.WbMasterDat_ob32(Wb2DatMosi_b32),
-----/\----- EXCLUDED -----/\----- */
.WbMasterDat_ib32(Wb2DatMiso_b32),
.WbMasterAck_i(Wb2Ack),
/* -----\/----- EXCLUDED -----\/-----
.TopLed_ob2(TopLed_b2),
.BottomLed_ob4(BottomLed_b4),
-----/\----- EXCLUDED -----/\----- */
.BstOn_i(BstOn),
.BunchClk_ik(BunchClk_k),
.TurnClk_ip(TurnClk_p),
.BstByteAddress_ib5(BstByteAddress_b5),
.BstByte_ib8(BstByte_b8),
/* -----\/----- EXCLUDED -----\/-----
.InterruptRequest_opb24(InterruptRequest_pb24),
.StreamerClk_ok(StreamerClk_k),
.StreamerData_ob32(StreamerData_b32),
.SreamerDav_o(SreamerDav),
.StreamerPckt_o(StreamerPckt),
.StreamerWait_i(StreamerWait),
-----/\----- EXCLUDED -----/\----- */
.StreamerWait_i(StreamerWait));
/* -----\/----- EXCLUDED -----\/-----
.GpIo1DirOut_o(GpIo1DirOut),
.GpIo2DirOut_o(GpIo2DirOut),
.GpIo34DirOut_o(GpIo34DirOut));
-----/\----- EXCLUDED -----/\----- */
endmodule
\ No newline at end of file
Hdl/Synthesis/BaseProject/QuartusPrj/.gitignore 0 → 100644
View file @ 0717ca14
db
incremental_db
output_files
a5_pin_model_dump.txt
VfcHd_BaseProject.qws
Hdl/Synthesis/BaseProject/Sdc/VfcHd_BaseProject.sdc
View file @ 0717ca14
## Generated SDC file "VfcHdTop.out.sdc"
## Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, the Altera Quartus II License Agreement,
## the Altera MegaCore Function License Agreement, or other
## applicable license agreement, including, without limitation,
## that your use is for the sole purpose of programming logic
## devices manufactured by Altera and sold by Altera or its
## authorized distributors. Please refer to the applicable
## agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 15.0.0 Build 145 04/22/2015 SJ Full Version"
## DATE "Mon Jun 01 17:42:10 2015"
##
## DEVICE "5AGXMB1G4F40C4"
##
#**************************************************************
# Time Information
#**************************************************************
......@@ -58,6 +29,7 @@ derive_pll_clocks
# Set Clock Uncertainty
#**************************************************************
derive_clock_uncertainty
#**************************************************************
# Set Input Delay
......@@ -82,7 +54,8 @@ set_clock_groups -asynchronous -group [get_clocks {GbitTrxClkRefR_ik}]
# Set False Path
#**************************************************************
set_false_path -from [get_ports *]