Commit 0b2e0dce authored by Manoel Barros Marin's avatar Manoel Barros Marin
Browse files

- GBT-FPGA example with 4 GBT Link Standard Mode fully operational

parent 839efd62
......@@ -80,8 +80,6 @@ library alt_av_gx_reconfctrl_x4;
--library alt_av_gx_reconfctrl_x5;
--library alt_av_gx_reconfctrl_x6;
library gx_reset_dummy;
--=================================================================================================--
--####################################### Entity ##############################################--
--=================================================================================================--
......@@ -149,22 +147,14 @@ architecture structural of mgt_std is
-- Reset controllers --
--===================--
--signal txAnalogReset_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
--signal txDigitalReset_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
--signal txReady_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
-----------------------------------------------
--signal rxAnalogReset_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
--signal rxDigitalReset_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
--signal rxReady_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
signal txAnalogReset_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
signal txDigitalReset_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
signal txReady_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
---------------------------------------------
signal rxAnalogReset_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
signal rxDigitalReset_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
signal rxReady_from_gxRstCtrl : std_logic_vector (1 to NUM_LINKS);
signal txAnalogReset_from_gxRstCtrl : std_logic_vector (3 downto 0);
signal txDigitalReset_from_gxRstCtrl : std_logic_vector (3 downto 0);
signal txReady_from_gxRstCtrl : std_logic_vector (3 downto 0);
---------------------------------------------
signal rxAnalogReset_from_gxRstCtrl : std_logic_vector (3 downto 0);
signal rxDigitalReset_from_gxRstCtrl : std_logic_vector (3 downto 0);
signal rxReady_from_gxRstCtrl : std_logic_vector (3 downto 0);
--========--
-- TX PLL --
--========--
......@@ -179,12 +169,9 @@ architecture structural of mgt_std is
-- Multi-Gigabit Transceivers (standard) --
--=======================================--
--signal rxIsLockedToData_from_gxStd : std_logic_vector (1 to NUM_LINKS);
--signal txCalBusy_from_gxStd : std_logic_vector (1 to NUM_LINKS);
--signal rxCalBusy_from_gxStd : std_logic_vector (1 to NUM_LINKS);
signal rxIsLockedToData_from_gxStd : std_logic_vector (3 downto 0);
signal txCalBusy_from_gxStd : std_logic_vector (3 downto 0);
signal rxCalBusy_from_gxStd : std_logic_vector (3 downto 0);
signal rxIsLockedToData_from_gxStd : std_logic_vector (1 to NUM_LINKS);
signal txCalBusy_from_gxStd : std_logic_vector (1 to NUM_LINKS);
signal rxCalBusy_from_gxStd : std_logic_vector (1 to NUM_LINKS);
signal reconfToXCVR : std_logic_vector ((NUM_LINKS*70)-1 downto 0);
signal XCVRToReconf : std_logic_vector ((NUM_LINKS*46)-1 downto 0);
......@@ -206,26 +193,16 @@ begin --========#### Architecture Body ####========--
commonAssign_gen: for i in 1 to NUM_LINKS generate
--MGT_O.mgtLink(i).rxWordClkReady <= rxReady_from_gxRstCtrl(i);
MGT_O.mgtLink(i).rxWordClkReady <= rxReady_from_gxRstCtrl(i-1);
--GBTRX_RXWORDCLK_READY_O(i) <= rxReady_from_gxRstCtrl(i);
GBTRX_RXWORDCLK_READY_O(i) <= rxReady_from_gxRstCtrl(i-1);
--MGT_O.mgtLink(i).txCal_busy <= txCalBusy_from_gxStd(i);
MGT_O.mgtLink(i).txCal_busy <= txCalBusy_from_gxStd(i-1);
--MGT_O.mgtLink(i).rxCal_busy <= rxCalBusy_from_gxStd(i);
MGT_O.mgtLink(i).rxCal_busy <= rxCalBusy_from_gxStd(i-1);
--MGT_O.mgtLink(i).ready <= txReady_from_gxRstCtrl(i) and rxReady_from_gxRstCtrl(i);
MGT_O.mgtLink(i).ready <= txReady_from_gxRstCtrl(i-1) and rxReady_from_gxRstCtrl(i-1);
--MGT_O.mgtLink(i).tx_ready <= txReady_from_gxRstCtrl(i);
MGT_O.mgtLink(i).tx_ready <= txReady_from_gxRstCtrl(i-1);
--MGT_O.mgtLink(i).rx_ready <= rxReady_from_gxRstCtrl(i);
MGT_O.mgtLink(i).rx_ready <= rxReady_from_gxRstCtrl(i-1);
--GBTTX_MGTTX_RDY_O(i) <= txReady_from_gxRstCtrl(i);
GBTTX_MGTTX_RDY_O(i) <= txReady_from_gxRstCtrl(i-1);
--GBTRX_MGTRX_RDY_O(i) <= rxReady_from_gxRstCtrl(i);
GBTRX_MGTRX_RDY_O(i) <= rxReady_from_gxRstCtrl(i-1);
--MGT_O.mgtLink(i).rxIsLocked_toData <= rxIsLockedToData_from_gxStd(i);
MGT_O.mgtLink(i).rxIsLocked_toData <= rxIsLockedToData_from_gxStd(i-1);
MGT_O.mgtLink(i).rxWordClkReady <= rxReady_from_gxRstCtrl(i);
GBTRX_RXWORDCLK_READY_O(i) <= rxReady_from_gxRstCtrl(i);
MGT_O.mgtLink(i).txCal_busy <= txCalBusy_from_gxStd(i);
MGT_O.mgtLink(i).rxCal_busy <= rxCalBusy_from_gxStd(i);
MGT_O.mgtLink(i).ready <= txReady_from_gxRstCtrl(i) and rxReady_from_gxRstCtrl(i);
MGT_O.mgtLink(i).tx_ready <= txReady_from_gxRstCtrl(i);
MGT_O.mgtLink(i).rx_ready <= rxReady_from_gxRstCtrl(i);
GBTTX_MGTTX_RDY_O(i) <= txReady_from_gxRstCtrl(i);
GBTRX_MGTRX_RDY_O(i) <= rxReady_from_gxRstCtrl(i);
MGT_O.mgtLink(i).rxIsLocked_toData <= rxIsLockedToData_from_gxStd(i);
end generate;
......@@ -233,59 +210,40 @@ begin --========#### Architecture Body ####========--
-- GX reset controllers --
--======================--
-- gxRstCtrl_gen: for i in 1 to NUM_LINKS generate
--
-- gxRstCtrl: entity work.alt_av_mgt_resetctrl
-- port map (
-- CLK_I => MGT_CLKS_I.mgtRefClk,
-- ---------------------
-- TX_RESET_I => MGT_I.mgtLink(1).tx_reset,--MGT_I.mgtLink(i).tx_reset,
-- RX_RESET_I => MGT_I.mgtLink(1).rx_reset,--MGT_I.mgtLink(i).rx_reset,
-- ---------------------
-- TX_ANALOGRESET_O => txAnalogReset_from_gxRstCtrl(i), --txAnalogReset_from_gxRstCtrl(1), --
-- TX_DIGITALRESET_O => txDigitalReset_from_gxRstCtrl(i), --txDigitalReset_from_gxRstCtrl(1),--
-- TX_READY_O => txReady_from_gxRstCtrl(i), --txReady_from_gxRstCtrl(1), --
-- PLL_LOCKED_I => TxPllLocked, --TxPllLocked, --
-- TX_CAL_BUSY_I => txCalBusy_from_gxStd(i), --txCalBusy_from_gxStd(1), --
-- ---------------------
-- RX_ANALOGRESET_O => rxAnalogReset_from_gxRstCtrl(i), --rxAnalogReset_from_gxRstCtrl(1), --
-- RX_DIGITALRESET_O => rxDigitalReset_from_gxRstCtrl(i),--rxDigitalReset_from_gxRstCtrl(1),--
-- RX_READY_O => rxReady_from_gxRstCtrl(i), --rxReady_from_gxRstCtrl(1), --
-- RX_IS_LOCKEDTODATA_I => rxIsLockedToData_from_gxStd(i), --rxIsLockedToData_from_gxStd(1), --
-- RX_CAL_BUSY_I => rxCalBusy_from_gxStd(i) --rxCalBusy_from_gxStd(1) --
-- );
--
-- end generate;
gxResetDummy: entity gx_reset_dummy.gx_reset_dummy
port map (
clock => MGT_CLKS_I.mgtRefClk,
reset => MGT_I.mgtLink(1).tx_reset,
tx_analogreset => txAnalogReset_from_gxRstCtrl,
tx_digitalreset => txDigitalReset_from_gxRstCtrl,
tx_ready => txReady_from_gxRstCtrl,
pll_locked(0) => TxPllLocked,
pll_select(0) => '0',
tx_cal_busy => txCalBusy_from_gxStd,
rx_analogreset => rxAnalogReset_from_gxRstCtrl,
rx_digitalreset => rxDigitalReset_from_gxRstCtrl,
rx_ready => rxReady_from_gxRstCtrl,
rx_is_lockedtodata => rxIsLockedToData_from_gxStd,
rx_cal_busy => rxCalBusy_from_gxStd
);
gxRstCtrl_gen: for i in 1 to NUM_LINKS generate
gxRstCtrl: entity work.alt_av_mgt_resetctrl
port map (
CLK_I => MGT_CLKS_I.mgtRefClk,
---------------------
TX_RESET_I => MGT_I.mgtLink(i).tx_reset,
RX_RESET_I => MGT_I.mgtLink(i).rx_reset,
---------------------
TX_ANALOGRESET_O => txAnalogReset_from_gxRstCtrl(i),
TX_DIGITALRESET_O => txDigitalReset_from_gxRstCtrl(i),
TX_READY_O => txReady_from_gxRstCtrl(i),
PLL_LOCKED_I => TxPllLocked,
TX_CAL_BUSY_I => txCalBusy_from_gxStd(i),
---------------------
RX_ANALOGRESET_O => rxAnalogReset_from_gxRstCtrl(i),
RX_DIGITALRESET_O => rxDigitalReset_from_gxRstCtrl(i),
RX_READY_O => rxReady_from_gxRstCtrl(i),
RX_IS_LOCKEDTODATA_I => rxIsLockedToData_from_gxStd(i),
RX_CAL_BUSY_I => rxCalBusy_from_gxStd(i)
);
end generate;
--================================================--
-- TX PLL --
-- TX PLL --
--================================================--
txPll: entity work.alt_av_mgt_txpll
port map (
RESET_I => MGT_I.mgtLink(1).tx_reset,
MGT_REFCLK_I => MGT_CLKS_I.mgtRefClk,
FEEDBACK_CLK_I => '0',
FEEDBACK_CLK_I => '0',
FEEDBACK_CLK_O => open,
EXTGXTXPLL_CLK_O => TxPll_clkout,
POWER_DOWN_O => pllPowerDown_from_txPll,
LOCKED_O => TxPllLocked,
......@@ -551,7 +509,7 @@ begin --========#### Architecture Body ####========--
-- MGT standard x4:
-------------------
-- gxStd_x4_gen: if NUM_LINKS = 4 generate
gxStd_x4_gen: if NUM_LINKS = 4 generate
reconfGxStd_x4: entity alt_av_gx_reconfctrl_x4.alt_av_gx_reconfctrl_x4
port map (
......@@ -576,14 +534,14 @@ begin --========#### Architecture Body ####========--
PLL_POWERDOWN(1) => pllPowerDown_from_txPll,
PLL_POWERDOWN(2) => pllPowerDown_from_txPll,
PLL_POWERDOWN(3) => pllPowerDown_from_txPll,
TX_ANALOGRESET(0) => txAnalogReset_from_gxRstCtrl(0),--(1),
TX_ANALOGRESET(1) => txAnalogReset_from_gxRstCtrl(1),--(2),--(1),--
TX_ANALOGRESET(2) => txAnalogReset_from_gxRstCtrl(2),--(3),--(1),--
TX_ANALOGRESET(3) => txAnalogReset_from_gxRstCtrl(3),--(4),--(1),--
TX_DIGITALRESET(0) => txDigitalReset_from_gxRstCtrl(0),--(1),
TX_DIGITALRESET(1) => txDigitalReset_from_gxRstCtrl(1),--(2),--(1),--
TX_DIGITALRESET(2) => txDigitalReset_from_gxRstCtrl(2),--(3),--(1),--
TX_DIGITALRESET(3) => txDigitalReset_from_gxRstCtrl(3),--(4),--(1),--
TX_ANALOGRESET(0) => txAnalogReset_from_gxRstCtrl(1),
TX_ANALOGRESET(1) => txAnalogReset_from_gxRstCtrl(2),
TX_ANALOGRESET(2) => txAnalogReset_from_gxRstCtrl(3),
TX_ANALOGRESET(3) => txAnalogReset_from_gxRstCtrl(4),
TX_DIGITALRESET(0) => txDigitalReset_from_gxRstCtrl(1),
TX_DIGITALRESET(1) => txDigitalReset_from_gxRstCtrl(2),
TX_DIGITALRESET(2) => txDigitalReset_from_gxRstCtrl(3),
TX_DIGITALRESET(3) => txDigitalReset_from_gxRstCtrl(4),
TX_SERIAL_DATA(0) => MGT_O.mgtLink(1).txSerialData,
TX_SERIAL_DATA(1) => MGT_O.mgtLink(2).txSerialData,
TX_SERIAL_DATA(2) => MGT_O.mgtLink(3).txSerialData,
......@@ -592,14 +550,14 @@ begin --========#### Architecture Body ####========--
EXT_PLL_CLK(1) => TxPll_clkout,
EXT_PLL_CLK(2) => TxPll_clkout,
EXT_PLL_CLK(3) => TxPll_clkout,
RX_ANALOGRESET(0) => rxAnalogReset_from_gxRstCtrl(0),--(1),
RX_ANALOGRESET(1) => rxAnalogReset_from_gxRstCtrl(1),--(2),--(1),--
RX_ANALOGRESET(2) => rxAnalogReset_from_gxRstCtrl(2),--(3),--(1),--
RX_ANALOGRESET(3) => rxAnalogReset_from_gxRstCtrl(3),--(4),--(1),--
RX_DIGITALRESET(0) => rxDigitalReset_from_gxRstCtrl(0),--(1),
RX_DIGITALRESET(1) => rxDigitalReset_from_gxRstCtrl(1),--(2),--(1),--
RX_DIGITALRESET(2) => rxDigitalReset_from_gxRstCtrl(2),--(3),--(1),--
RX_DIGITALRESET(3) => rxDigitalReset_from_gxRstCtrl(3),--(4),--(1),--
RX_ANALOGRESET(0) => rxAnalogReset_from_gxRstCtrl(1),
RX_ANALOGRESET(1) => rxAnalogReset_from_gxRstCtrl(2),
RX_ANALOGRESET(2) => rxAnalogReset_from_gxRstCtrl(3),
RX_ANALOGRESET(3) => rxAnalogReset_from_gxRstCtrl(4),
RX_DIGITALRESET(0) => rxDigitalReset_from_gxRstCtrl(1),
RX_DIGITALRESET(1) => rxDigitalReset_from_gxRstCtrl(2),
RX_DIGITALRESET(2) => rxDigitalReset_from_gxRstCtrl(3),
RX_DIGITALRESET(3) => rxDigitalReset_from_gxRstCtrl(4),
RX_CDR_REFCLK(0) => MGT_CLKS_I.mgtRefClk,
RX_SERIAL_DATA(0) => MGT_I.mgtLink(1).rxSerialData,
RX_SERIAL_DATA(1) => MGT_I.mgtLink(2).rxSerialData,
......@@ -609,15 +567,18 @@ begin --========#### Architecture Body ####========--
RX_IS_LOCKEDTOREF(1) => MGT_O.mgtLink(2).rxIsLocked_toRef,
RX_IS_LOCKEDTOREF(2) => MGT_O.mgtLink(3).rxIsLocked_toRef,
RX_IS_LOCKEDTOREF(3) => MGT_O.mgtLink(4).rxIsLocked_toRef,
RX_IS_LOCKEDTODATA(0) => rxIsLockedToData_from_gxStd(0),--(1),
RX_IS_LOCKEDTODATA(1) => rxIsLockedToData_from_gxStd(1),--(2),
RX_IS_LOCKEDTODATA(2) => rxIsLockedToData_from_gxStd(2),--(3),
RX_IS_LOCKEDTODATA(3) => rxIsLockedToData_from_gxStd(3),--(4),
RX_IS_LOCKEDTODATA(0) => rxIsLockedToData_from_gxStd(1),
RX_IS_LOCKEDTODATA(1) => rxIsLockedToData_from_gxStd(2),
RX_IS_LOCKEDTODATA(2) => rxIsLockedToData_from_gxStd(3),
RX_IS_LOCKEDTODATA(3) => rxIsLockedToData_from_gxStd(4),
RX_SERIALLPBKEN(0) => MGT_I.mgtLink(1).loopBack,
RX_SERIALLPBKEN(1) => MGT_I.mgtLink(2).loopBack,
RX_SERIALLPBKEN(2) => MGT_I.mgtLink(3).loopBack,
RX_SERIALLPBKEN(3) => MGT_I.mgtLink(4).loopBack,
TX_STD_CORECLKIN => tx_usrclk,
TX_STD_CORECLKIN(0) => tx_usrclk(1),
TX_STD_CORECLKIN(1) => tx_usrclk(1),
TX_STD_CORECLKIN(2) => tx_usrclk(1),
TX_STD_CORECLKIN(3) => tx_usrclk(1),
RX_STD_CORECLKIN => rx_usrclk,
TX_STD_CLKOUT => tx_usrclk,
RX_STD_CLKOUT => rx_usrclk,
......@@ -629,14 +590,14 @@ begin --========#### Architecture Body ####========--
RX_STD_POLINV(1) => MGT_I.mgtLink(2).rx_polarity,
RX_STD_POLINV(2) => MGT_I.mgtLink(3).rx_polarity,
RX_STD_POLINV(3) => MGT_I.mgtLink(4).rx_polarity,
TX_CAL_BUSY(0) => txCalBusy_from_gxStd(0),--(1),
TX_CAL_BUSY(1) => txCalBusy_from_gxStd(1),--(2),
TX_CAL_BUSY(2) => txCalBusy_from_gxStd(2),--(3),
TX_CAL_BUSY(3) => txCalBusy_from_gxStd(3),--(4),
RX_CAL_BUSY(0) => rxCalBusy_from_gxStd(0),--(1),
RX_CAL_BUSY(1) => rxCalBusy_from_gxStd(1),--(2),
RX_CAL_BUSY(2) => rxCalBusy_from_gxStd(2),--(3),
RX_CAL_BUSY(3) => rxCalBusy_from_gxStd(3),--(4),
TX_CAL_BUSY(0) => txCalBusy_from_gxStd(1),
TX_CAL_BUSY(1) => txCalBusy_from_gxStd(2),
TX_CAL_BUSY(2) => txCalBusy_from_gxStd(3),
TX_CAL_BUSY(3) => txCalBusy_from_gxStd(4),
RX_CAL_BUSY(0) => rxCalBusy_from_gxStd(1),
RX_CAL_BUSY(1) => rxCalBusy_from_gxStd(2),
RX_CAL_BUSY(2) => rxCalBusy_from_gxStd(3),
RX_CAL_BUSY(3) => rxCalBusy_from_gxStd(4),
RECONFIG_TO_XCVR => reconfToXCVR,
RECONFIG_FROM_XCVR => XCVRToReconf,
TX_PARALLEL_DATA( 39 downto 0) => GBTTX_WORD_I(1),
......@@ -666,7 +627,7 @@ begin --========#### Architecture Body ####========--
RX_WORDCLK_O(3) <= rx_usrclk(2);
RX_WORDCLK_O(4) <= rx_usrclk(3);
-- end generate;
end generate;
-- MGT standard x5:
-------------------
......
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
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Subscription Agreement, the Altera Quartus Prime License Agreement,
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applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
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*/
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(text "tx_ready" (rect 289 123 626 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "tx_ready" (rect 246 147 540 304)(font "Arial" (color 0 0 0)))
(text "pll_locked" (rect 71 123 202 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "pll_locked" (rect 133 147 326 304)(font "Arial" (color 0 0 0)))
(text "pll_select" (rect 74 163 208 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "pll_select" (rect 133 187 326 384)(font "Arial" (color 0 0 0)))
(text "tx_cal_busy" (rect 60 203 186 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "tx_cal_busy" (rect 133 227 332 464)(font "Arial" (color 0 0 0)))
(text "rx_analogreset" (rect 289 163 662 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "rx_analogreset" (rect 221 187 526 384)(font "Arial" (color 0 0 0)))
(text "rx_digitalreset" (rect 289 203 668 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "rx_digitalreset" (rect 224 227 538 464)(font "Arial" (color 0 0 0)))
(text "rx_ready" (rect 289 243 626 499)(font "Arial" (color 128 0 0)(font_size 9)))
(text "rx_ready" (rect 245 267 538 544)(font "Arial" (color 0 0 0)))
(text "rx_is_lockedtodata" (rect 19 243 146 499)(font "Arial" (color 128 0 0)(font_size 9)))
(text "rx_is_lockedtodata" (rect 133 267 374 544)(font "Arial" (color 0 0 0)))
(text "rx_cal_busy" (rect 59 283 184 579)(font "Arial" (color 128 0 0)(font_size 9)))
(text "rx_cal_busy" (rect 133 307 332 624)(font "Arial" (color 0 0 0)))
(text " altera_xcvr_reset_control " (rect 300 328 762 666)(font "Arial" ))
(line (pt 128 32)(pt 288 32)(line_width 1))
(line (pt 288 32)(pt 288 328)(line_width 1))
(line (pt 128 328)(pt 288 328)(line_width 1))
(line (pt 128 32)(pt 128 328)(line_width 1))
(line (pt 129 52)(pt 129 76)(line_width 1))
(line (pt 130 52)(pt 130 76)(line_width 1))
(line (pt 129 92)(pt 129 116)(line_width 1))
(line (pt 130 92)(pt 130 116)(line_width 1))
(line (pt 287 52)(pt 287 76)(line_width 1))
(line (pt 286 52)(pt 286 76)(line_width 1))
(line (pt 287 92)(pt 287 116)(line_width 1))
(line (pt 286 92)(pt 286 116)(line_width 1))
(line (pt 287 132)(pt 287 156)(line_width 1))
(line (pt 286 132)(pt 286 156)(line_width 1))
(line (pt 129 132)(pt 129 156)(line_width 1))
(line (pt 130 132)(pt 130 156)(line_width 1))
(line (pt 129 172)(pt 129 196)(line_width 1))
(line (pt 130 172)(pt 130 196)(line_width 1))
(line (pt 129 212)(pt 129 236)(line_width 1))
(line (pt 130 212)(pt 130 236)(line_width 1))
(line (pt 287 172)(pt 287 196)(line_width 1))
(line (pt 286 172)(pt 286 196)(line_width 1))
(line (pt 287 212)(pt 287 236)(line_width 1))
(line (pt 286 212)(pt 286 236)(line_width 1))
(line (pt 287 252)(pt 287 276)(line_width 1))
(line (pt 286 252)(pt 286 276)(line_width 1))
(line (pt 129 252)(pt 129 276)(line_width 1))
(line (pt 130 252)(pt 130 276)(line_width 1))
(line (pt 129 292)(pt 129 316)(line_width 1))
(line (pt 130 292)(pt 130 316)(line_width 1))
(line (pt 0 0)(pt 416 0)(line_width 1))
(line (pt 416 0)(pt 416 344)(line_width 1))
(line (pt 0 344)(pt 416 344)(line_width 1))
(line (pt 0 0)(pt 0 344)(line_width 1))
)
)
component gx_reset_dummy is
port (
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
tx_analogreset : out std_logic_vector(3 downto 0); -- tx_analogreset
tx_digitalreset : out std_logic_vector(3 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(3 downto 0); -- tx_ready
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
tx_cal_busy : in std_logic_vector(3 downto 0) := (others => 'X'); -- tx_cal_busy
rx_analogreset : out std_logic_vector(3 downto 0); -- rx_analogreset
rx_digitalreset : out std_logic_vector(3 downto 0); -- rx_digitalreset
rx_ready : out std_logic_vector(3 downto 0); -- rx_ready
rx_is_lockedtodata : in std_logic_vector(3 downto 0) := (others => 'X'); -- rx_is_lockedtodata
rx_cal_busy : in std_logic_vector(3 downto 0) := (others => 'X') -- rx_cal_busy
);
end component gx_reset_dummy;
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_TOOL_NAME "altera_xcvr_reset_control"
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_TOOL_VERSION "16.0"
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "gx_reset_dummy" -name MISC_FILE [file join $::quartus(qip_path) "gx_reset_dummy.cmp"]
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_TARGETED_DEVICE_FAMILY "Arria V"
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_GENERATED_DEVICE_FAMILY "{Arria V}"
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_QSYS_MODE "UNKNOWN"
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_COMPONENT_NAME "Z3hfcmVzZXRfZHVtbXk="
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_COMPONENT_DISPLAY_NAME "VHJhbnNjZWl2ZXIgUEhZIFJlc2V0IENvbnRyb2xsZXI="
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "gx_reset_dummy" -library "gx_reset_dummy" -name IP_COMPONENT_VERSION "MTYuMA=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_NAME "YWx0ZXJhX3hjdnJfcmVzZXRfY29udHJvbA=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_DISPLAY_NAME "VHJhbnNjZWl2ZXIgUEhZIFJlc2V0IENvbnRyb2xsZXI="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_VERSION "MTYuMA=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::QXJyaWEgVg==::ZGV2aWNlX2ZhbWlseQ=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "Q0hBTk5FTFM=::NA==::TnVtYmVyIG9mIHRyYW5zY2VpdmVyIGNoYW5uZWxz"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "UExMUw==::MQ==::TnVtYmVyIG9mIFRYIFBMTHM="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "U1lTX0NMS19JTl9NSFo=::MTIw::SW5wdXQgY2xvY2sgZnJlcXVlbmN5"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "U1lOQ0hST05JWkVfUkVTRVQ=::MQ==::U3luY2hyb25pemUgcmVzZXQgaW5wdXQ="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "UkVEVUNFRF9TSU1fVElNRQ==::MQ==::VXNlIGZhc3QgcmVzZXQgZm9yIHNpbXVsYXRpb24="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "Z3VpX3NwbGl0X2ludGVyZmFjZXM=::MA==::U2VwYXJhdGUgaW50ZXJmYWNlIHBlciBjaGFubmVsL1BMTA=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "VFhfUExMX0VOQUJMRQ==::MA==::RW5hYmxlIFRYIFBMTCByZXNldCBjb250cm9s"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "VFhfRU5BQkxF::MQ==::RW5hYmxlIFRYIGNoYW5uZWwgcmVzZXQgY29udHJvbA=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "VFhfUEVSX0NIQU5ORUw=::MA==::VXNlIHNlcGFyYXRlIFRYIHJlc2V0IHBlciBjaGFubmVs"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "Z3VpX3R4X2F1dG9fcmVzZXQ=::MA==::VFggZGlnaXRhbCByZXNldCBtb2Rl"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "VF9UWF9BTkFMT0dSRVNFVA==::MA==::dHhfYW5hbG9ncmVzZXQgZHVyYXRpb24="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "VF9UWF9ESUdJVEFMUkVTRVQ=::NTA=::dHhfZGlnaXRhbHJlc2V0IGR1cmF0aW9u"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "VF9QTExfTE9DS19IWVNU::MA==::cGxsX2xvY2tlZCBpbnB1dCBoeXN0ZXJlc2lz"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9jYWxfYnVzeQ==::MA==::RW5hYmxlIHBsbF9jYWxfYnVzeSBpbnB1dCBwb3J0"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "RU5fUExMX0NBTF9CVVNZ::MA==::RU5fUExMX0NBTF9CVVNZ"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "UlhfRU5BQkxF::MQ==::RW5hYmxlIFJYIGNoYW5uZWwgcmVzZXQgY29udHJvbA=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "UlhfUEVSX0NIQU5ORUw=::MA==::VXNlIHNlcGFyYXRlIFJYIHJlc2V0IHBlciBjaGFubmVs"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "Z3VpX3J4X2F1dG9fcmVzZXQ=::MA==::UlggZGlnaXRhbCByZXNldCBtb2Rl"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "VF9SWF9BTkFMT0dSRVNFVA==::NTA=::cnhfYW5hbG9ncmVzZXQgZHVyYXRpb24="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "VF9SWF9ESUdJVEFMUkVTRVQ=::NDAwMA==::cnhfZGlnaXRhbHJlc2V0IGR1cmF0aW9u"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF90ZXJtaW5hdGVfcGxs::MQ==::bF90ZXJtaW5hdGVfcGxs"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF90ZXJtaW5hdGVfdHg=::MA==::bF90ZXJtaW5hdGVfdHg="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF90ZXJtaW5hdGVfcng=::MA==::bF90ZXJtaW5hdGVfcng="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF90ZXJtaW5hdGVfdHhfbWFudWFs::MQ==::bF90ZXJtaW5hdGVfdHhfbWFudWFs"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF90ZXJtaW5hdGVfcnhfbWFudWFs::MQ==::bF90ZXJtaW5hdGVfcnhfbWFudWFs"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF90eF9tYW51YWxfdGVybQ==::MA==::bF90eF9tYW51YWxfdGVybQ=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF9yeF9tYW51YWxfdGVybQ==::MA==::bF9yeF9tYW51YWxfdGVybQ=="
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF9wbGxfc2VsZWN0X3NwbGl0::MA==::bF9wbGxfc2VsZWN0X3NwbGl0"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF9wbGxfc2VsZWN0X3dpZHRo::MQ==::bF9wbGxfc2VsZWN0X3dpZHRo"
set_global_assignment -entity "altera_xcvr_reset_control" -library "gx_reset_dummy" -name IP_COMPONENT_PARAMETER "bF9wbGxfc2VsZWN0X2Jhc2U=::MQ==::bF9wbGxfc2VsZWN0X2Jhc2U="
set_global_assignment -library "gx_reset_dummy" -name VHDL_FILE [file join $::quartus(qip_path) "gx_reset_dummy.vhd"]
set_global_assignment -library "gx_reset_dummy" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "gx_reset_dummy/altera_xcvr_functions.sv"]
set_global_assignment -library "gx_reset_dummy" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "gx_reset_dummy/alt_xcvr_resync.sv"]
set_global_assignment -library "gx_reset_dummy" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "gx_reset_dummy/altera_xcvr_reset_control.sv"]
set_global_assignment -library "gx_reset_dummy" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "gx_reset_dummy/alt_xcvr_reset_counter.sv"]
set_global_assignment -library "gx_reset_dummy" -name SOURCE_FILE [file join $::quartus(qip_path) "gx_reset_dummy/plain_files.txt"]