Commit 0b2e0dce authored by Manoel Barros Marin's avatar Manoel Barros Marin
Browse files

- GBT-FPGA example with 4 GBT Link Standard Mode fully operational

parent 839efd62
......@@ -289,12 +289,12 @@ AddrDecoderWBApp i_AddrDecoderWbApp(
.AckPllRef_i (WbAckPllRef),
.StbPllRef_o (WbStbPllRef),
//--
.DatGbtCtrlReg_ib32 (32'h0),//WbDatGbtCtrlReg_b32),
.AckGbtCtrlReg_i ( 1'b0),//WbAckGbtCtrlReg),
.DatGbtCtrlReg_ib32 (WbDatGbtCtrlReg_b32),
.AckGbtCtrlReg_i (WbAckGbtCtrlReg),
.StbGbtCtrlReg_o (WbStbGbtCtrlReg),
//--
.DatGbtStatReg_ib32 (32'h0),//WbDatGbtStatReg_b32),
.AckGbtStatReg_i ( 1'b0),//WbAckGbtStatReg),
.DatGbtStatReg_ib32 (WbDatGbtStatReg_b32),
.AckGbtStatReg_i (WbAckGbtStatReg),
.StbGbtStatReg_o (WbStbGbtStatReg));
//****************************
......@@ -382,559 +382,309 @@ i_I2cPllRef (
// Clocks forwarding:
assign TestIo1_io = PllRefClkOut_ik;
assign TestIo2_io = GbtTxFrameClk40Mhz_k;
//****************************
// Dummy MGT test
// GBT-FPGA example design
//****************************
// GBT-FPGA Example Deging (Features 4 GBT Link):
alt_av_gbt_example_design_wrap_verilog #(
.g_GbtBankId (1),
.g_TxOptimization (0), // Comment: Standard
.g_RxOptimization (0), // Comment: Standard
.g_TxEncoding (0), // Comment: GBT Frame
.g_RxEncoding (0), // Comment: GBT Frame
// Extended configuration:
.g_DataGeneratorEnable (1),
.g_DataCheckerEnable (1),
.g_MatchFlagEnable (1))
i_GbtExampleDesign_4xGbtLinks (
// Clocks:
.TxFrameClk40Mhz_ik (GbtTxFrameClk40Mhz_k),
.MgtRefClk120Mhz_ik (PllRefClkOut_ik),
.TxFrameClk_1_ok (),
.TxFrameClk_2_ok (),
.TxFrameClk_3_ok (),
.TxFrameClk_4_ok (),
.RxFrameClk_1_ok (),
.RxFrameClk_2_ok (),
.RxFrameClk_3_ok (),
.RxFrameClk_4_ok (),
.TxWordClk_1_ok (),
.TxWordClk_2_ok (),
.TxWordClk_3_ok (),
.TxWordClk_4_ok (),
.RxWordClk_1_ok (),
.RxWordClk_2_ok (),
.RxWordClk_3_ok (),
.RxWordClk_4_ok (),
// Reset:
.GbtBankGeneralReset_ir (Reset_irqp),
.GbtBankManualResetTx_1_ir (GbtBankManualResetTx_1_r),
.GbtBankManualResetTx_2_ir (GbtBankManualResetTx_2_r),
.GbtBankManualResetTx_3_ir (GbtBankManualResetTx_3_r),
.GbtBankManualResetTx_4_ir (GbtBankManualResetTx_4_r),
.GbtBankManualResetRx_1_ir (GbtBankManualResetRx_1_r),
.GbtBankManualResetRx_2_ir (GbtBankManualResetRx_2_r),
.GbtBankManualResetRx_3_ir (GbtBankManualResetRx_3_r),
.GbtBankManualResetRx_4_ir (GbtBankManualResetRx_4_r),
// Serial lanes:
.GbtBankMgtRx_1_i (AppSfpRx_ib4[1]),
.GbtBankMgtRx_2_i (AppSfpRx_ib4[2]),
.GbtBankMgtRx_3_i (AppSfpRx_ib4[3]),
.GbtBankMgtRx_4_i (AppSfpRx_ib4[4]),
.GbtBankMgtTx_1_o (AppSfpTx_ob4[1]),
.GbtBankMgtTx_2_o (AppSfpTx_ob4[2]),
.GbtBankMgtTx_3_o (AppSfpTx_ob4[3]),
.GbtBankMgtTx_4_o (AppSfpTx_ob4[4]),
// Data:
.GbtBankGbtTxData_1_ib84 ( 84'h0),
.GbtBankGbtTxData_2_ib84 ( 84'h0),
.GbtBankGbtTxData_3_ib84 ( 84'h0),
.GbtBankGbtTxData_4_ib84 ( 84'h0),
.GbtBankWbTxData_1_ib116 (116'h0),
.GbtBankWbTxData_2_ib116 (116'h0),
.GbtBankWbTxData_3_ib116 (116'h0),
.GbtBankWbTxData_4_ib116 (116'h0),
.GbtBankGbtRxData_1_ob84 (),
.GbtBankGbtRxData_2_ob84 (),
.GbtBankGbtRxData_3_ob84 (),
.GbtBankGbtRxData_4_ob84 (),
.GbtBankWbRxData_1_ob32 (),
.GbtBankWbRxData_2_ob32 (),
.GbtBankWbRxData_3_ob32 (),
.GbtBankWbRxData_4_ob32 (),
// Reconfiguration:
.GbtBankReconfAvmmRst_ir (Reset_irqp),
.GbtBankReconfAvmmClk_ik (PllRefClkOut_ik),
.GbtBankReconfAvmmAddr_ib7 ( 7'h0),
.GbtBankReconfAvmmRead_i ( 1'b0),
.GbtBankReconfAvmmWrite_i ( 1'b0),
.GbtBankReconfAvmmWriteData_ib32 (32'h0),
.GbtBankReconfAvmmReadData_ob32 (),
.GbtBankReconfAvmmWaitRequest_o (),
// Control:
.GbtBankTxIsDataSel_1_i (GbtBankTxIsDataSel),
.GbtBankTxIsDataSel_2_i (GbtBankTxIsDataSel),
.GbtBankTxIsDataSel_3_i (GbtBankTxIsDataSel),
.GbtBankTxIsDataSel_4_i (GbtBankTxIsDataSel),
.GbtBankTestPatternSel_ib2 (GbtBankTestPatternSel),
.GbtBankResetGbtRxReadyLostFlag_1_i (GbtBankResetGbtRxReadyLostFlag_1),
.GbtBankResetGbtRxReadyLostFlag_2_i (GbtBankResetGbtRxReadyLostFlag_2),
.GbtBankResetGbtRxReadyLostFlag_3_i (GbtBankResetGbtRxReadyLostFlag_3),
.GbtBankResetGbtRxReadyLostFlag_4_i (GbtBankResetGbtRxReadyLostFlag_4),
.GbtBankResetDataErrorSeenFlag_1_i (GbtBankResetDataErrorSeenFlag_1),
.GbtBankResetDataErrorSeenFlag_2_i (GbtBankResetDataErrorSeenFlag_2),
.GbtBankResetDataErrorSeenFlag_3_i (GbtBankResetDataErrorSeenFlag_3),
.GbtBankResetDataErrorSeenFlag_4_i (GbtBankResetDataErrorSeenFlag_4),
// Status:
.GbtBankLinkReady_1_o (GbtBankLinkReady_1),
.GbtBankLinkReady_2_o (GbtBankLinkReady_2),
.GbtBankLinkReady_3_o (GbtBankLinkReady_3),
.GbtBankLinkReady_4_o (GbtBankLinkReady_4),
.GbtBankLinkTxReady_1_o (GbtBankLinkTxReady_1),
.GbtBankLinkTxReady_2_o (GbtBankLinkTxReady_2),
.GbtBankLinkTxReady_3_o (GbtBankLinkTxReady_3),
.GbtBankLinkTxReady_4_o (GbtBankLinkTxReady_4),
.GbtBankLinkRxReady_1_o (GbtBankLinkRxReady_1),
.GbtBankLinkRxReady_2_o (GbtBankLinkRxReady_2),
.GbtBankLinkRxReady_3_o (GbtBankLinkRxReady_3),
.GbtBankLinkRxReady_4_o (GbtBankLinkRxReady_4),
.GbtBankGbtRxReady_1_o (GbtBankGbtRxReady_1),
.GbtBankGbtRxReady_2_o (GbtBankGbtRxReady_2),
.GbtBankGbtRxReady_3_o (GbtBankGbtRxReady_3),
.GbtBankGbtRxReady_4_o (GbtBankGbtRxReady_4),
.GbtBankRxIsDataSel_1_o (GbtBankRxIsDataSel_1),
.GbtBankRxIsDataSel_2_o (GbtBankRxIsDataSel_2),
.GbtBankRxIsDataSel_3_o (GbtBankRxIsDataSel_3),
.GbtBankRxIsDataSel_4_o (GbtBankRxIsDataSel_4),
.GbtBankGbtRxReadyLostFlag_1_o (GbtBankGbtRxReadyLostFlag_1),
.GbtBankGbtRxReadyLostFlag_2_o (GbtBankGbtRxReadyLostFlag_2),
.GbtBankGbtRxReadyLostFlag_3_o (GbtBankGbtRxReadyLostFlag_3),
.GbtBankGbtRxReadyLostFlag_4_o (GbtBankGbtRxReadyLostFlag_4),
.GbtBankRxDataErrorSeenFlag_1_o (GbtBankRxDataErrorSeenFlag_1),
.GbtBankRxDataErrorSeenFlag_2_o (GbtBankRxDataErrorSeenFlag_2),
.GbtBankRxDataErrorSeenFlag_3_o (GbtBankRxDataErrorSeenFlag_3),
.GbtBankRxDataErrorSeenFlag_4_o (GbtBankRxDataErrorSeenFlag_4),
.GbtBankRxExtraDataWbErrorSeenFlag_1_o (GbtBankRxExtraDataWbErrorSeenFlag_1),
.GbtBankRxExtraDataWbErrorSeenFlag_2_o (GbtBankRxExtraDataWbErrorSeenFlag_2),
.GbtBankRxExtraDataWbErrorSeenFlag_3_o (GbtBankRxExtraDataWbErrorSeenFlag_3),
.GbtBankRxExtraDataWbErrorSeenFlag_4_o (GbtBankRxExtraDataWbErrorSeenFlag_4),
.GbtBankTxMatchFlag_o (FmcLaP_iob34[ 0]),
.GbtBankRxMatchFlag_1_o (FmcLaP_iob34[ 7]),
.GbtBankRxMatchFlag_2_o (FmcLaP_iob34[ 8]),
.GbtBankRxMatchFlag_3_o (FmcLaP_iob34[ 9]),
.GbtBankRxMatchFlag_4_o (FmcLaP_iob34[10]),
// XCVR ctrl:
.GbtBankLoopBack_1_i (GbtBankLoopBack_1),
.GbtBankLoopBack_2_i (GbtBankLoopBack_2),
.GbtBankLoopBack_3_i (GbtBankLoopBack_3),
.GbtBankLoopBack_4_i (GbtBankLoopBack_4),
.GbtBankTxPol_1_i (GbtBankTxPol_1),
.GbtBankTxPol_2_i (GbtBankTxPol_2),
.GbtBankTxPol_3_i (GbtBankTxPol_3),
.GbtBankTxPol_4_i (GbtBankTxPol_4),
.GbtBankRxPol_1_i (GbtBankRxPol_1),
.GbtBankRxPol_2_i (GbtBankRxPol_2),
.GbtBankRxPol_3_i (GbtBankRxPol_3),
.GbtBankRxPol_4_i (GbtBankRxPol_4),
.GbtBankTxWordClkMonEn_i (GbtBankTxWordClkMonEn));
wire [ 3:0] txAnalogReset_from_gxRstCtrl;
wire [ 3:0] txDigitalReset_from_gxRstCtrl;
wire [ 0:0] TxPllLocked;
wire [ 3:0] txCalBusy_from_gxStd;
wire [ 3:0] rxAnalogReset_from_gxRstCtrl;
wire [ 3:0] rxDigitalReset_from_gxRstCtrl;
wire [ 3:0] rxIsLockedToData_from_gxStd;
wire [ 3:0] rxCalBusy_from_gxStd;
wire TxPll_clkout;
wire pllPowerDown_from_txPll;
//wire [279:0] reconfToXCVR;
//wire [239:0] XCVRToReconf;
//wire [ 69:0] reconfToTxPll;
//wire [ 45:0] TxPllToReconf;
wire [ 3:0] tx_usrclk;
wire [ 3:0] rx_usrclk;
reg [ 39:0] TxData_q40;
wire [159:0] TxData_b160;
wire [159:0] RxData_b160;
reg [ 39:0] RxData_q40 [3:0];
//
//gx_reset_dummy i_GxReset (
// .clock (PllRefClkOut_ik),
// .reset (Reset_irqp || GbtBankManualResetTx_1_r),
// .tx_analogreset (txAnalogReset_from_gxRstCtrl),
// .tx_digitalreset (txDigitalReset_from_gxRstCtrl),
// .tx_ready (),
// .pll_locked (TxPllLocked),
// .pll_select (1'b0),
// .tx_cal_busy (txCalBusy_from_gxStd),
// .rx_analogreset (rxAnalogReset_from_gxRstCtrl),
// .rx_digitalreset (rxDigitalReset_from_gxRstCtrl),
// .rx_ready (),
// .rx_is_lockedtodata (rxIsLockedToData_from_gxStd),
// .rx_cal_busy (rxCalBusy_from_gxStd));
//
//alt_av_mgt_txpll i_TxPll (
// .RESET_I (Reset_irqp || GbtBankManualResetTx_1_r),
// .MGT_REFCLK_I (PllRefClkOut_ik),
// .FEEDBACK_CLK_I (1'b0),
// .EXTGXTXPLL_CLK_O (TxPll_clkout),
// .POWER_DOWN_O (pllPowerDown_from_txPll),
// .LOCKED_O (TxPllLocked),
// .RECONFIG_I (reconfToTxPll),
// .RECONFIG_O (TxPllToReconf));
//
//alt_av_gx_reconfctrl_x4 i_ReconfCtrl (
// .RECONFIG_BUSY (),
// .MGMT_RST_RESET (1'b0),
// .MGMT_CLK_CLK (1'b0),
// .RECONFIG_MGMT_ADDRESS (7'h0),
// .RECONFIG_MGMT_READ (1'b0),
// .RECONFIG_MGMT_READDATA (),
// .RECONFIG_MGMT_WAITREQUEST (),
// .RECONFIG_MGMT_WRITE (1'b0),
// .RECONFIG_MGMT_WRITEDATA (32'h0),
// .CH0_3_TO_XCVR (reconfToXCVR),
// .CH0_3_FROM_XCVR (XCVRToReconf),
// .CH4_4_TO_XCVR (reconfToTxPll),
// .CH4_4_FROM_XCVR (TxPllToReconf));
always @(posedge tx_usrclk[0])
if (Reset_irqp) TxData_q40 <= #1 40'h0;
else TxData_q40 <= #1 ~TxData_q40;
assign TxData_b160 = {TxData_q40,TxData_q40,TxData_q40,TxData_q40};
//alt_av_gx_std_x4 i_4xGx (
// .PLL_POWERDOWN ({pllPowerDown_from_txPll,pllPowerDown_from_txPll,pllPowerDown_from_txPll,pllPowerDown_from_txPll}),
// .TX_ANALOGRESET (txAnalogReset_from_gxRstCtrl),
// .TX_DIGITALRESET (txDigitalReset_from_gxRstCtrl),
// .TX_SERIAL_DATA ({AppSfpTx_ob4[4],AppSfpTx_ob4[3],AppSfpTx_ob4[2],AppSfpTx_ob4[1]}),
// .EXT_PLL_CLK ({TxPll_clkout,TxPll_clkout,TxPll_clkout,TxPll_clkout}),
// .RX_ANALOGRESET (rxAnalogReset_from_gxRstCtrl),
// .RX_DIGITALRESET (rxDigitalReset_from_gxRstCtrl),
// .RX_CDR_REFCLK (PllRefClkOut_ik),
// .RX_SERIAL_DATA ({AppSfpRx_ib4[4],AppSfpRx_ib4[3],AppSfpRx_ib4[2],AppSfpRx_ib4[1]}),
// .RX_IS_LOCKEDTOREF (),
// .RX_IS_LOCKEDTODATA (rxIsLockedToData_from_gxStd),
// .RX_SERIALLPBKEN ({GbtBankLoopBack_4,GbtBankLoopBack_3,GbtBankLoopBack_2,GbtBankLoopBack_1}),
// .TX_STD_CORECLKIN (tx_usrclk[0]),
// .RX_STD_CORECLKIN (rx_usrclk),
// .TX_STD_CLKOUT (tx_usrclk),
// .RX_STD_CLKOUT (rx_usrclk),
// .TX_STD_POLINV (4'h0),
// .RX_STD_POLINV (4'h0),
// .TX_CAL_BUSY (txCalBusy_from_gxStd),
// .RX_CAL_BUSY (rxCalBusy_from_gxStd),
// .RECONFIG_TO_XCVR (reconfToXCVR),
// .RECONFIG_FROM_XCVR (XCVRToReconf),
// .TX_PARALLEL_DATA (TxData_b160),
// .RX_PARALLEL_DATA (RxData_b160));
// Control registers bank, Clock Domain Crossing & wires mapping:
Generic4OutputRegs #(
.Reg0Default (32'h00000000),
.Reg0AutoClrMask (32'hF807FFFF),
.Reg1Default (32'h00000000),
.Reg1AutoClrMask (32'hFFFFFFFF),
.Reg2Default (32'h00000000),
.Reg2AutoClrMask (32'hFFFFFFFF),
.Reg3Default (32'h00000000),
.Reg3AutoClrMask (32'hFFFFFFFF))
i_GbtControlRegs (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbGbtCtrlReg),
.We_i (WbSlaveWr_i),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_oab32 (WbDatGbtCtrlReg_b32),
.Ack_oa (WbAckGbtCtrlReg),
//--
.Reg0Value_ob32 (GbtCtrlReg_2x32[0]),
.Reg1Value_ob32 (GbtCtrlReg_2x32[1]),
.Reg2Value_ob32 (),
.Reg3Value_ob32 ());
//gx_std_x4_dummy i_4xGxDummy (
// .phy_mgmt_clk (PllRefClkOut_ik),
// .phy_mgmt_clk_reset (Reset_irqp),
// .phy_mgmt_address (9'h0),
// .phy_mgmt_read (1'b0),
// .phy_mgmt_readdata (),
// .phy_mgmt_waitrequest (),
// .phy_mgmt_write (1'b0),
// .phy_mgmt_writedata (31'h0),
// .tx_ready (),
// .rx_ready (),
// .pll_ref_clk (PllRefClkOut_ik),
// .tx_serial_data ({AppSfpTx_ob4[4],AppSfpTx_ob4[3],AppSfpTx_ob4[2],AppSfpTx_ob4[1]}),
// .pll_locked (),
// .rx_serial_data ({AppSfpRx_ib4[4],AppSfpRx_ib4[3],AppSfpRx_ib4[2],AppSfpRx_ib4[1]}),
// .rx_bitslip (4'h0),
// .tx_clkout (tx_usrclk[0]),
// .rx_clkout (rx_usrclk),
// .tx_parallel_data (TxData_b160),
// .rx_parallel_data (RxData_b160),
// .reconfig_from_xcvr (),
// .reconfig_to_xcvr (350'h0));
generate for (i=0;i<2;i=i+1) begin: GenGbtCtrlRegCdc
generic_dpram #(
.aw ( 1),
.dw (32))
i_GbtCtrlRegCdc (
.rclk (GbtTxFrameClk40Mhz_k),
.rrst (Reset_irqp),
.rce (1'b1),
.oe (1'b1),
.raddr (1'b0),
.do (GbtCtrlRegCdc_2x32[i]),
.wclk (Clk_k),
.wrst (Reset_irqp),
.wce (1'b1),
.we (1'b1),
.waddr (1'b0),
.di (GbtCtrlReg_2x32[i]));
end endgenerate
assign GbtBankManualResetTx_1_r = GbtCtrlRegCdc_2x32[0][ 0];
assign GbtBankManualResetTx_2_r = GbtCtrlRegCdc_2x32[0][ 1];
assign GbtBankManualResetTx_3_r = GbtCtrlRegCdc_2x32[0][ 2];
assign GbtBankManualResetTx_4_r = GbtCtrlRegCdc_2x32[0][ 3];
assign GbtBankManualResetRx_1_r = GbtCtrlRegCdc_2x32[0][ 4];
assign GbtBankManualResetRx_2_r = GbtCtrlRegCdc_2x32[0][ 5];
assign GbtBankManualResetRx_3_r = GbtCtrlRegCdc_2x32[0][ 6];
assign GbtBankManualResetRx_4_r = GbtCtrlRegCdc_2x32[0][ 7];
//--
assign GbtBankTxIsDataSel = GbtCtrlRegCdc_2x32[0][ 16];
//--
assign GbtBankTestPatternSel = GbtCtrlRegCdc_2x32[0][18:17];
//--
assign GbtBankResetGbtRxReadyLostFlag_1 = GbtCtrlRegCdc_2x32[0][ 19]; // Comment: Auto-clear
assign GbtBankResetGbtRxReadyLostFlag_2 = GbtCtrlRegCdc_2x32[0][ 20]; // Comment: Auto-clear
assign GbtBankResetGbtRxReadyLostFlag_3 = GbtCtrlRegCdc_2x32[0][ 21]; // Comment: Auto-clear
assign GbtBankResetGbtRxReadyLostFlag_4 = GbtCtrlRegCdc_2x32[0][ 22]; // Comment: Auto-clear
//--
assign GbtBankResetDataErrorSeenFlag_1 = GbtCtrlRegCdc_2x32[0][ 23]; // Comment: Auto-clear
assign GbtBankResetDataErrorSeenFlag_2 = GbtCtrlRegCdc_2x32[0][ 24]; // Comment: Auto-clear
assign GbtBankResetDataErrorSeenFlag_3 = GbtCtrlRegCdc_2x32[0][ 25]; // Comment: Auto-clear
assign GbtBankResetDataErrorSeenFlag_4 = GbtCtrlRegCdc_2x32[0][ 26]; // Comment: Auto-clear
generate for (i=0;i<4;i=i+1) begin: GenGxRstCtrl
alt_av_mgt_resetctrl i_GxRstCtrl (
.CLK_I (PllRefClkOut_ik),
.TX_RESET_I (Reset_irqp),
.RX_RESET_I (Reset_irqp),
.TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl[i]),
.TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl[i]),
.TX_READY_O (),
.PLL_LOCKED_I (TxPllLocked),
.TX_CAL_BUSY_I (txCalBusy_from_gxStd[i]),
.RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl[i]),
.RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl[i]),
.RX_READY_O (),
.RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd[i]),
.RX_CAL_BUSY_I (rxCalBusy_from_gxStd[i]));
assign GbtBankLoopBack_1 = GbtCtrlRegCdc_2x32[1][ 0];
assign GbtBankLoopBack_2 = GbtCtrlRegCdc_2x32[1][ 1];
assign GbtBankLoopBack_3 = GbtCtrlRegCdc_2x32[1][ 2];
assign GbtBankLoopBack_4 = GbtCtrlRegCdc_2x32[1][ 3];
//--
assign GbtBankTxPol_1 = GbtCtrlRegCdc_2x32[1][ 8];
assign GbtBankTxPol_2 = GbtCtrlRegCdc_2x32[1][ 9];
assign GbtBankTxPol_3 = GbtCtrlRegCdc_2x32[1][ 10];
assign GbtBankTxPol_4 = GbtCtrlRegCdc_2x32[1][ 11];
assign GbtBankRxPol_1 = GbtCtrlRegCdc_2x32[1][ 12];
assign GbtBankRxPol_2 = GbtCtrlRegCdc_2x32[1][ 13];
assign GbtBankRxPol_3 = GbtCtrlRegCdc_2x32[1][ 14];
assign GbtBankRxPol_4 = GbtCtrlRegCdc_2x32[1][ 15];
//--
assign GbtBankTxWordClkMonEn = GbtCtrlRegCdc_2x32[1][ 24];
// Status registers bank, Clock Domain Crossing & wires mapping:
Generic4InputRegs i_GbtStatusRegs (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbGbtStatReg),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatGbtStatReg_b32),
.Ack_oa (WbAckGbtStatReg),
//--
.Reg0Value_ib32 (GbtStatRegCdc_2x32[0]),
.Reg1Value_ib32 (GbtStatRegCdc_2x32[1]),
.Reg2Value_ib32 (32'h01234567),
.Reg3Value_ib32 (32'h89ABCDEF));
generate for (i=0;i<2;i=i+1) begin: GenGbtStatRegCdc
generic_dpram #(
.aw ( 1),
.dw (32))
i_GbtStatRegCdc (
.rclk (Clk_k),
.rrst (Reset_irqp),
.rce (1'b1),
.oe (1'b1),
.raddr (1'b0),
.do (GbtStatRegCdc_2x32[i]),
.wclk (GbtTxFrameClk40Mhz_k),
.wrst (Reset_irqp),
.wce (1'b1),
.we (1'b1),
.waddr (1'b0),
.di (GbtStatReg_2x32[i]));
end endgenerate
assign GbtStatReg_2x32[0][ 0] = GbtBankLinkReady_1;
assign GbtStatReg_2x32[0][ 1] = GbtBankLinkReady_2;
assign GbtStatReg_2x32[0][ 2] = GbtBankLinkReady_3;
assign GbtStatReg_2x32[0][ 3] = GbtBankLinkReady_4;
//alt_av_mgt_resetctrl i_GxRstCtrl0 (
// .CLK_I (PllRefClkOut_ik),
// .TX_RESET_I (Reset_irqp),
// .RX_RESET_I (Reset_irqp),
// .TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl(0)),
// .TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl(0)),
// .TX_READY_O (),
// .PLL_LOCKED_I (TxPllLocked),
// .TX_CAL_BUSY_I (txCalBusy_from_gxStd(0)),
// .RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl(0)),
// .RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl(0)),
// .RX_READY_O (),
// .RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd(0)),
// .RX_CAL_BUSY_I (rxCalBusy_from_gxStd(0)));
//
//alt_av_mgt_resetctrl i_GxRstCtrl1 (
// .CLK_I (PllRefClkOut_ik),
// .TX_RESET_I (Reset_irqp),
// .RX_RESET_I (Reset_irqp),
// .TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl(1)),
// .TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl(1)),
// .TX_READY_O (),
// .PLL_LOCKED_I (TxPllLocked),
// .TX_CAL_BUSY_I (txCalBusy_from_gxStd(1)),
// .RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl(1)),
// .RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl(1)),
// .RX_READY_O (),
// .RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd(1)),
// .RX_CAL_BUSY_I (rxCalBusy_from_gxStd(1)));
//
//alt_av_mgt_resetctrl i_GxRstCtrl2 (
// .CLK_I (PllRefClkOut_ik),
// .TX_RESET_I (Reset_irqp),
// .RX_RESET_I (Reset_irqp),
// .TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl(2)),
// .TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl(2)),
// .TX_READY_O (),
// .PLL_LOCKED_I (TxPllLocked),
// .TX_CAL_BUSY_I (txCalBusy_from_gxStd(2)),
// .RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl(2)),
// .RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl(2)),
// .RX_READY_O (),
// .RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd(2)),
// .RX_CAL_BUSY_I (rxCalBusy_from_gxStd(2)));
//
//alt_av_mgt_resetctrl i_GxRstCtrl3 (
// .CLK_I (PllRefClkOut_ik),
// .TX_RESET_I (Reset_irqp),
// .RX_RESET_I (Reset_irqp),
// .TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl(3)),
// .TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl(3)),
// .TX_READY_O (),
// .PLL_LOCKED_I (TxPllLocked),
// .TX_CAL_BUSY_I (txCalBusy_from_gxStd(3)),
// .RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl(3)),
// .RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl(3)),
// .RX_READY_O (),
// .RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd(3)),
// .RX_CAL_BUSY_I (rxCalBusy_from_gxStd(3)));
assign GbtStatReg_2x32[0][ 8] = GbtBankLinkTxReady_1;
assign GbtStatReg_2x32[0][ 9] = GbtBankLinkTxReady_2;
assign GbtStatReg_2x32[0][10] = GbtBankLinkTxReady_3;
assign GbtStatReg_2x32[0][11] = GbtBankLinkTxReady_4;
assign GbtStatReg_2x32[0][12] = GbtBankLinkRxReady_1;
assign GbtStatReg_2x32[0][13] = GbtBankLinkRxReady_2;
assign GbtStatReg_2x32[0][14] = GbtBankLinkRxReady_3;
assign GbtStatReg_2x32[0][15] = GbtBankLinkRxReady_4;
alt_av_mgt_txpll i_TxPll (
.RESET_I (Reset_irqp || GbtBankManualResetTx_1_r),
.MGT_REFCLK_I (PllRefClkOut_ik),
.FEEDBACK_CLK_I (1'b0),
.FEEDBACK_CLK_O (),
.EXTGXTXPLL_CLK_O (TxPll_clkout),
.POWER_DOWN_O (pllPowerDown_from_txPll),
.LOCKED_O (TxPllLocked),
.RECONFIG_I (70'h0),
.RECONFIG_O ());
assign GbtStatReg_2x32[0][16] = GbtBankGbtRxReady_1;
assign GbtStatReg_2x32[0][17] = GbtBankGbtRxReady_2;
assign GbtStatReg_2x32[0][18] = GbtBankGbtRxReady_3;
assign GbtStatReg_2x32[0][19] = GbtBankGbtRxReady_4;
alt_av_gx_std_x4 i_4xGx (
.pll_powerdown ({pllPowerDown_from_txPll, pllPowerDown_from_txPll, pllPowerDown_from_txPll, pllPowerDown_from_txPll}),
.tx_analogreset (txAnalogReset_from_gxRstCtrl),
.tx_digitalreset (txDigitalReset_from_gxRstCtrl),
.tx_serial_data ({AppSfpTx_ob4[4],AppSfpTx_ob4[3],AppSfpTx_ob4[2],AppSfpTx_ob4[1]}),
.ext_pll_clk ({TxPll_clkout, TxPll_clkout, TxPll_clkout, TxPll_clkout}),
.rx_analogreset (rxAnalogReset_from_gxRstCtrl),
.rx_digitalreset (rxDigitalReset_from_gxRstCtrl),
.rx_cdr_refclk (PllRefClkOut_ik),
.rx_serial_data ({AppSfpRx_ib4[4],AppSfpRx_ib4[3],AppSfpRx_ib4[2],AppSfpRx_ib4[1]}),
.rx_is_lockedtoref (),
.rx_is_lockedtodata (rxIsLockedToData_from_gxStd),
.rx_seriallpbken (4'h0),
.tx_std_coreclkin ({tx_usrclk[0], tx_usrclk[0], tx_usrclk[0], tx_usrclk[0]}),
.rx_std_coreclkin (rx_usrclk),
.tx_std_clkout (tx_usrclk),
.rx_std_clkout (rx_usrclk),
.tx_std_polinv (4'h0),
.rx_std_polinv (4'h0),
.tx_cal_busy (txCalBusy_from_gxStd),
.rx_cal_busy (rxCalBusy_from_gxStd),
.reconfig_to_xcvr (280'h0),
.reconfig_from_xcvr (),
.tx_parallel_data (TxData_b160),
.rx_parallel_data (RxData_b160));
always @(posedge rx_usrclk[0])
if (Reset_irqp) RxData_q40[0] <= #1 40'h0;
else RxData_q40[0] <= #1 RxData_b160[39:0];
assign GbtStatReg_2x32[1][ 0] = GbtBankRxIsDataSel_1;
assign GbtStatReg_2x32[1][ 1] = GbtBankRxIsDataSel_2;
assign GbtStatReg_2x32[1][ 2] = GbtBankRxIsDataSel_3;
assign GbtStatReg_2x32[1][ 3] = GbtBankRxIsDataSel_4;
always @(posedge rx_usrclk[1])
if (Reset_irqp) RxData_q40[1] <= #1 40'h0;
else RxData_q40[1] <= #1 RxData_b160[79:40];
assign GbtStatReg_2x32[1][ 8] = GbtBankGbtRxReadyLostFlag_1;
assign GbtStatReg_2x32[1][ 9] = GbtBankGbtRxReadyLostFlag_2;
assign GbtStatReg_2x32[1][10] = GbtBankGbtRxReadyLostFlag_3;
assign GbtStatReg_2x32[1][11] = GbtBankGbtRxReadyLostFlag_4;
always @(posedge rx_usrclk[2])
if (Reset_irqp) RxData_q40[2] <= #1 40'h0;
else RxData_q40[2] <= #1 RxData_b160[119:80];
assign GbtStatReg_2x32[1][12] = GbtBankRxDataErrorSeenFlag_1;
assign GbtStatReg_2x32[1][13] = GbtBankRxDataErrorSeenFlag_2;
assign GbtStatReg_2x32[1][14] = GbtBankRxDataErrorSeenFlag_3;
assign GbtStatReg_2x32[1][15] = GbtBankRxDataErrorSeenFlag_4;
always @(posedge rx_usrclk[3])
if (Reset_irqp) RxData_q40[3] <= #1 40'h0;
else RxData_q40[3] <= #1 RxData_b160[159:120];
//****************************
// GBT-FPGA example design
//****************************
//// GBT-FPGA Example Deging (Features 4 GBT Link):
//alt_av_gbt_example_design_wrap_verilog #(