Commit 1ff29b7b authored by Jan Pospisil's avatar Jan Pospisil
Browse files

updated .gitignore

parent 8e435741
*.bak
*.pyc
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
Doc/AlteraDocuments/EMIF_Altera.pdf
Doc/AlteraDocuments/an520.pdf
Doc/AlteraDocuments/arriav_handbook.pdf
Doc/AlteraDocuments/ddr3AlteraDesign.pdf
Doc/Datasheets/8Gb_DDR3L.pdf
Hw/Assembly data/
Hw/EDA-03133-V2-0_project.Annotation
Hw/EDA-03133-V2-0_project.PrjPCB
Hw/EDA-03133-V2-0_project.PrjPCBStructure
Hw/Manufacturing/EDA-03133-V2_mfg.cam
Hw/PCB-Layout/
Hw/Schematics/
Hdl/Simulation/BasicVmeAccesses/modelsim/project/BasicVmeAccesses.cr.mti
/Hdl/Simulation/BaseProjectSimulation/modelsim/project/*
!/Hdl/Simulation/BaseProjectSimulation/modelsim/project/BaseProject_sim.mpf
/Hdl/Synthesis/*/QuartusPrj/*
!/Hdl/Synthesis/*/QuartusPrj/VfcHd_BaseProject.qpf
!/Hdl/Synthesis/*/QuartusPrj/VfcHd_BaseProject.qsf
/Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
/Doc/AlteraDocuments/EMIF_Altera.pdf
/Doc/AlteraDocuments/an520.pdf
/Doc/AlteraDocuments/arriav_handbook.pdf
/Doc/AlteraDocuments/ddr3AlteraDesign.pdf
/Doc/Datasheets/8Gb_DDR3L.pdf
/Doc/VfcHd_UserGuides/BI-VFC-HD-V2_0.pdf
/Hw/Assembly data/
/Hw/EDA-03133-V2-0_project.Annotation
/Hw/EDA-03133-V2-0_project.PrjPCB
/Hw/EDA-03133-V2-0_project.PrjPCBStructure
/Hw/Manufacturing/EDA-03133-V2_mfg.cam
/Hw/PCB-Layout/
/Hw/Schematics/
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment