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Commit 204202a5 authored by Manoel Barros Marin's avatar Manoel Barros Marin
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- GBT-FPGA in application ready 

- Note!!! GBT GX not operational (Reset controller issue)
- Dummy Gx operational
parent 0d1a14f3
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Hdl/FpgaModules/ApplicationSpecific/GbtFpgaBaseProject/AddrDecoderWbApp.v → Hdl/FpgaModules/ApplicationSpecific/GbtBaseProject/AddrDecoderWbApp.v
View file @ 204202a5
......@@ -17,25 +17,43 @@ module AddrDecoderWBApp(
input [31:0] DatStatReg_ib32,
input AckStatReg_i,
output reg StbStatReg_o
output reg StbStatReg_o,
input [31:0] DatPllRef_ib32,
input AckPllRef_i,
output reg StbPllRef_o,
input [31:0] DatGbtCtrlReg_ib32,
input AckGbtCtrlReg_i,
output reg StbGbtCtrlReg_o,
input [31:0] DatGbtStatReg_ib32,
input AckGbtStatReg_i,
output reg StbGbtStatReg_o
);
localparam dly = 1;
reg [1:0] SelectedModule_b2;
reg [2:0] SelectedModule_b3;
localparam c_SelNothing = 2'd0,
c_SelAppRevisionId = 2'd1,
c_SelCtrlReg = 2'd2,
c_SelStatReg = 2'd3;
localparam c_SelNothing = 3'd0,
c_SelAppRevisionId = 3'd1,
c_SelCtrlReg = 3'd2,
c_SelStatReg = 3'd3,
c_SelPllRef = 3'd4,
c_SelGbtCtrlReg = 3'd5,
c_SelGbtStatReg = 3'd6;
always @*
casez(Adr_ib21)
21'b0_0000_0000_0000_0000_00??: SelectedModule_b2 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_01??: SelectedModule_b2 = c_SelCtrlReg; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_10??: SelectedModule_b2 = c_SelStatReg; // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
default: SelectedModule_b2 = c_SelNothing;
21'b0_0000_0000_0000_0000_00??: SelectedModule_b3 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_01??: SelectedModule_b3 = c_SelCtrlReg; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_10??: SelectedModule_b3 = c_SelStatReg; // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_110?: SelectedModule_b3 = c_SelPllRef; // FROM 00_000C TO 00_000D (WB) == FROM 00_0030 TO 00_0034 (VME) <- 2 regs ( 8B)
21'b0_0000_0000_0000_0001_00??: SelectedModule_b3 = c_SelGbtCtrlReg; // FROM 00_0010 TO 00_0013 (WB) == FROM 00_0040 TO 00_004C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0001_01??: SelectedModule_b3 = c_SelGbtStatReg; // FROM 00_0014 TO 00_0017 (WB) == FROM 00_0050 TO 00_005C (VME) <- 4 regs (16B)
default: SelectedModule_b3 = c_SelNothing;
endcase
always @(posedge Clk_ik) begin
......@@ -44,7 +62,8 @@ always @(posedge Clk_ik) begin
StbAppReleaseId_o <= #dly 1'b0;
StbCtrlReg_o <= #dly 1'b0;
StbStatReg_o <= #dly 1'b0;
case(SelectedModule_b2)
StbPllRef_o <= #dly 1'b0;
case(SelectedModule_b3)
c_SelAppRevisionId: begin
StbAppReleaseId_o <= #dly Stb_i;
Dat_ob32 <= #dly DatAppReleaseId_ib32;
......@@ -60,6 +79,21 @@ always @(posedge Clk_ik) begin
Dat_ob32 <= #dly DatStatReg_ib32;
Ack_o <= #dly AckStatReg_i;
end
c_SelPllRef: begin
StbPllRef_o <= #dly Stb_i;
Dat_ob32 <= #dly DatPllRef_ib32;
Ack_o <= #dly AckPllRef_i;
end
c_SelGbtCtrlReg: begin
StbGbtCtrlReg_o <= #dly Stb_i;
Dat_ob32 <= #dly DatGbtCtrlReg_ib32;
Ack_o <= #dly AckGbtCtrlReg_i;
end
c_SelGbtStatReg: begin
StbGbtStatReg_o <= #dly Stb_i;
Dat_ob32 <= #dly DatGbtStatReg_ib32;
Ack_o <= #dly AckGbtStatReg_i;
end
endcase
end
......
Hdl/FpgaModules/ApplicationSpecific/GbtFpgaBaseProject/VfcHdApplication.v deleted 100644 → 0
View file @ 0d1a14f3
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'h01,
g_ApplicationReleaseDay_b8 = 8'h18,
g_ApplicationReleaseMonth_b8 = 8'h07,
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
input BstSfpRx_i, // Comment: Differential signal
output BstSfpTx_o, // Comment: Differential signal
input EthSfpRx_i, // Comment: Differential signal
output EthSfpTx_o, // Comment: Differential signal
// SFP Gbit:
input [ 4:1] AppSfpRx_ib4, // Comment: Differential signal
output [ 4:1] AppSfpTx_ob4, // Comment: Differential signal
// DDR3 SO-DIMM:
output [ 2:0] DdrBa_ob3,
output [ 7:0] DdrDm_ob8,
inout [ 7:0] DdrDqs_iob8, // Comment: Differential signal
inout [63:0] DdrDq_iob64,
output [15:0] DdrA_ob16,
output [ 1:0] DdrCk_okb2, // Comment: Differential signal
output [ 1:0] DdrCkE_ohb2,
output DdrReset_orn,
output DdrRas_on,
output DdrCas_on,
output DdrWe_on,
output [ 1:0] DdrCs_onb2,
output [ 1:0] DdrOdt_ob2,
input DdrTempEvent_in,
output DdrI2cScl_ok,
inout DdrI2cSda_io,
// TestIo:
inout TestIo1_io,
inout TestIo2_io,
// FMC connector:
inout [33:0] FmcLaP_iob34,
inout [33:0] FmcLaN_iob34,
inout [23:0] FmcHaP_iob24,
inout [23:0] FmcHaN_iob24,
inout [21:0] FmcHbP_iob22,
inout [21:0] FmcHbN_iob22,
input FmcPrsntM2C_in,
output FmcTck_ok,
output FmcTms_o,
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,
inout FmcScl_iok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
inout FmcClk2Bidir_iok, // Comment: Differential signal
inout FmcClk3Bidir_iok, // Comment: Differential signal
input FmcClkDir_i,
output [ 9:0] FmcDpC2M_ob10, // Comment: Differential signal
input [ 9:0] FmcDpM2C_ib10,
input FmcGbtClk0M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk1M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk0M2CRight_ik, // Comment: Differential signal
input FmcGbtClk1M2CRight_ik, // Comment: Differential signal
// Clock sources and control:
output OeSi57x_oe,
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
output PllRefScl_ok,
inout PllRefSda_io,
input PllRefInt_i,
output PllSourceMuxOut_ok,
input PllRefClkOut_ik, // Comment: Differential reference for the Gbit lines
input GbitTrxClkRefR_ik, // Comment: Differential reference for the Gbit lines ~125MHz
// SW1:
input [ 1:0] Switch_ib2,
// P2 RTM:
inout [19:0] P2DataP_iob20, //Comment: The 0 is a clock capable input
inout [19:0] P2DataN_iob20,
// P0 Timing:
input [ 7:0] P0HwHighByte_ib8,
input [ 7:0] P0HwLowByte_ib8,
output DaisyChain1Cntrl_o,
output DaisyChain2Cntrl_o,
input VmeP0BunchClk_ik,
input VmeP0Tclk_ik,
// GPIO:
inout [ 4:1] GpIo_iob4,
// Specials:
input PushButtonN_in,
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
// Reset:
input Reset_irqp, // Comment: Reset Synchronous with the WbClk_ik
output ResetRequest_oqp, // Comment: Request to issue a reset
// WishBone:
output WbClk_ok,
input WbSlaveCyc_i,
input WbSlaveStb_i,
input [24:0] WbSlaveAdr_ib25,
input WbSlaveWr_i,
input [31:0] WbSlaveDat_ib32,
output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o,
output WbMasterCyc_o,
output WbMasterStb_o,
output [24:0] WbMasterAdr_ob25,
output WbMasterWr_o,
output [31:0] WbMasterDat_ob32,
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
// LED control:
output [ 1:0] TopLed_ob2,
output [ 3:0] BottomLed_ob4,
// BST input:
input BstOn_i,
input BunchClk_ik,
input TurnClk_ip,
input [ 5:0] BstByteAddress_ib5,
input [ 7:0] BstByte_ib8,
// Interrupt:
output [23:0] InterruptRequest_opb24,
// Ethernet streamer:
output StreamerClk_ok,
output [31:0] StreamerData_ob32,
output SreamerDav_o,
output StreamerPckt_o,
input StreamerWait_i,
// GPIO direction:
output GpIo1DirOut_o,
output GpIo2DirOut_o,
output GpIo34DirOut_o
);
//****************************
//Declarations
//****************************
wire Clk_k;
wire WbStbAppReleaseId, WbAckAppReleaseId;
wire [31:0] WbDatAppReleaseId_b32;
wire WbStbCtrlReg, WbAckCtrlReg;
wire [31:0] WbDatCtrlReg_b32;
wire WbStbStatReg, WbAckStatReg;
wire [31:0] WbDatStatReg_b32;
wire WbStbPllRef, WbAckPllRef;
wire [31:0] WbDatPllRef_b32;
wire [31:0] Reg0Value_b32;
//****************************
//Fixed assignments
//****************************
assign OeSi57x_oe = 1'b1;
//****************************
//Clocking
//****************************
assign Clk_k = GbitTrxClkRefR_ik; //~125MHz
assign WbClk_ok = Clk_k;
//****************************
//WB address decoder
//****************************
AddrDecoderWBApp i_AddrDecoderWbApp(
.Clk_ik (Clk_k),
.Adr_ib21 (WbSlaveAdr_ib25[20:0]),
.Stb_i (WbSlaveStb_i),
.Dat_ob32 (WbSlaveDat_ob32),
.Ack_o (WbSlaveAck_o),
//--
.DatAppReleaseId_ib32 (WbDatAppReleaseId_b32),
.AckAppReleaseId_i (WbAckAppReleaseId),
.StbAppReleaseId_o (WbStbAppReleaseId),
//--
.DatCtrlReg_ib32 (WbDatCtrlReg_b32),
.AckCtrlReg_i (WbAckCtrlReg),
.StbCtrlReg_o (WbStbCtrlReg),
//--
.DatStatReg_ib32 (WbDatStatReg_b32),
.AckStatReg_i (WbAckStatReg),
.StbStatReg_o (WbStbStatReg));
//****************************
//Release ID
//****************************
Generic4InputRegs i_AppReleaseId(
.Rst_irq (Reset_irqp),
.Clk_ik (Clk_k),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbAppReleaseId),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatAppReleaseId_b32),
.Ack_oa (WbAckAppReleaseId),
.Reg0Value_ib32 ("VFC-"),
.Reg1Value_ib32 ("HD G"),
.Reg2Value_ib32 ("BT "),
.Reg3Value_ib32 ({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
//****************************
//Example registers
//****************************
//Control register bank:
Generic4OutputRegs #(
.Reg0Default (32'hBABEB00B),
.Reg0AutoClrMask (32'hFFFFFFFF),
.Reg1Default (32'h00000000),
.Reg1AutoClrMask (32'hFFFFFFFF),
.Reg2Default (32'h00000000),
.Reg2AutoClrMask (32'hFFFFFFFF),
.Reg3Default (32'h00000000),
.Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbCtrlReg),
.We_i (WbSlaveWr_i),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_oab32 (WbDatCtrlReg_b32),
.Ack_oa (WbAckCtrlReg),
//--
.Reg0Value_ob32 (Reg0Value_b32),
.Reg1Value_ob32 (),
.Reg2Value_ob32 (),
.Reg3Value_ob32 ());
//Status registers bank:
Generic4InputRegs i_StatusRegs (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbStatReg),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatStatReg_b32),
.Ack_oa (WbAckStatReg),
//--
.Reg0Value_ib32 (Reg0Value_b32),
.Reg1Value_ib32 (32'hCAFEAC1D),
.Reg2Value_ib32 (32'hACDCDEAD),
.Reg3Value_ib32 (32'hFEEDBEEF));
//****************************
//PLL Ref (Si5338) I2C control
//****************************
I2cMasterWb #(
.g_CycleLenght (10'd256))
i_I2cPllRef (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbStatReg),
.We_i (WbSlaveWr_i),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_oab32 (WbDatPllRef_b32),
.Ack_oa (WbAckPllRef),
.Scl_ioz (PllRefScl_ok),
.Sda_ioz (PllRefSda_io));
//****************************
// GBT-FPGA example design
//****************************
endmodule
\ No newline at end of file
Hdl/FpgaModules/GeneralPurpose/Ip_Altera/OBufDdr/ObufDdr.qip 0 → 100644
View file @ 204202a5
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "15.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ObufDdr.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ObufDdr.ppf"]
Hdl/FpgaModules/GeneralPurpose/Ip_Altera/OBufDdr/ObufDdr.v 0 → 100644
View file @ 204202a5
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTDDIO_OUT
// ============================================================
// File Name: ObufDdr.v
// Megafunction Name(s):
// ALTDDIO_OUT
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ObufDdr (
datain_h,
datain_l,
outclock,
dataout);
input [0:0] datain_h;
input [0:0] datain_l;
input outclock;
output [0:0] dataout;
wire [0:0] sub_wire0;
wire [0:0] dataout = sub_wire0[0:0];
altddio_out ALTDDIO_OUT_component (
.datain_h (datain_h),
.datain_l (datain_l),
.outclock (outclock),
.dataout (sub_wire0),
.aclr (1'b0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
ALTDDIO_OUT_component.extend_oe_disable = "OFF",
ALTDDIO_OUT_component.intended_device_family = "Cyclone V",
ALTDDIO_OUT_component.invert_output = "OFF",
ALTDDIO_OUT_component.lpm_hint = "UNUSED",
ALTDDIO_OUT_component.lpm_type = "altddio_out",
ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
ALTDDIO_OUT_component.power_up_high = "OFF",
ALTDDIO_OUT_component.width = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.cmp FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
Hdl/FpgaModules/GeneralPurpose/Ip_Cern/GbtFpga/gbt_fpga_4_0_0/example_designs/altera_av/VfcHd/issp_project/cvGtFpgaDevkit_gbt_example_design.spf 0 → 100644
View file @ 204202a5
<session jtag_chain="USB-BlasterII [USB-1]" jtag_device="@1: 5CGTFD9(A5|C5|D5|E5)/.. (0x02B040DD)" sof_file="D:/svn/trunk/example_designs/altera_cv/cv_gt_fpga_devkit/qii_project_qsys/output_files/cvGtFpgaDevkit_gbt_example_design.sof">
<display_attributes is_max_probe_read_interval="1" is_write_immediate="1" probe_read_interval="1" probe_read_interval_units="s"/>
<instance enable_logging="true" entity_name="NONE" is_auto_node="true" name="alt_cv_issp:inSysSrcAndPrb|altsource_probe:altsource_probe_component">
<node_ip_info instance_id="0" mfg_id="110" node_id="9" version="0"/>
<sources>
<source name="LOOPBACK" value="false"/>
<source name="GENERAL RESET" value="false"/>
<source name="RESERVED" value="false"/>
<source name="TX RESET" value="false"/>
<source name="RX RESET" value="false"/>
<source name="LSB" value="false"/>
<source name="MSB" value="true"/>
<source name="TX ISDATA" value="false"/>
<source name="RESET DATA_ERROR_SEEN FLAG" value="false"/>
<source name="RESET RX_READY_LOST FLAG" value="false"/>
<source name="source[10]" value="false"/>
<source name="source[11]" value="false"/>
<source name="source[12]" value="false"/>
<source name="source[13]" value="false"/>
<source name="source[14]" value="false"/>
<source name="source[15]" value="false"/>
<source name="source[16]" value="false"/>
<source name="source[17]" value="false"/>
<source name="source[18]" value="false"/>
<source name="source[19]" value="false"/>
<source name="source[20]" value="false"/>
<source name="source[21]" value="false"/>
<source name="source[22]" value="false"/>
<source name="source[23]" value="false"/>
<source name="source[24]" value="false"/>
<source name="source[25]" value="false"/>
<source name="source[26]" value="false"/>
<source name="source[27]" value="false"/>
<source name="source[28]" value="false"/>
<source name="source[29]" value="false"/>
<source name="source[30]" value="false"/>
<source name="source[31]" value="false"/>
<source name="source[32]" value="false"/>
<source name="source[33]" value="false"/>
<source name="source[34]" value="false"/>
<source name="source[35]" value="false"/>
</sources>
<probes>
<probe name="TX LATENCY OPTIMIZED"/>
<probe name="RX LATENCY OPTIMIZED"/>
<probe name="MGT TX READY"/>
<probe name="MGT RX READY"/>
<probe name="MGT READY"/>
<probe name="GBT RX READY"/>
<probe name="DATA_ERROR_SEEN FLAG"/>
<probe name="RX_READY_LOST FLAG"/>
<probe name="FRAMECLK LOCKED"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[9]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[10]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[11]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[12]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[13]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[14]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[15]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[16]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[17]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[18]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[19]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[20]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[21]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[22]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[23]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[24]"/>
<probe name="alt_cv_issp:inSysSrcAndPrb|probe[25]"/>