[WR-dev] Modifications to VME-WB interface. Make it compliant with standard WB classic.

Tested with the WR PTP core, as well as with the WB I2C master already used in the VFC-HD project. Works with both.

Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v

@@ -57,12 +57,13 @@ always @*
 		22'b00000000000000000010??: SelectedModule_b8 = c_SelUniqueIdReader; // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
 		22'b00000000000000000011??: SelectedModule_b8 = c_SelI2cWrProm;      // FROM 00_000C TO 00_000F (WB) == FROM 00_0030 TO 00_003C (VME) <- 4 regs (16B)	
 		22'b0000000000000000010???: SelectedModule_b8 = c_SelSpiMaster;      // FROM 00_0010 TO 00_0017 (WB) == FROM 00_0040 TO 00_005C (VME) <- 8 regs (32B)
-	        22'b000001????????????????: SelectedModule_b8 = c_SelWrPtpCore;      // FROM 01_0000 TO 01_FFFF (WB) == FROM 04_0000 TO 07_FFFC (VME) <- 64K regs (256KB)
+		22'b000001????????????????: SelectedModule_b8 = c_SelWrPtpCore;      // FROM 01_0000 TO 01_FFFF (WB) == FROM 04_0000 TO 07_FFFC (VME)
 		22'b1?????????????????????: SelectedModule_b8 = c_SelAppSlaveBus;    // FROM 20_0000 TO 3F_FFFF (WB) == FROM 80_0000 TO FF_FFFC (VME) <- 2M regs (8MB)
 		default: SelectedModule_b8 = c_SelNothing;
     endcase     
 
-always @(posedge Clk_ik) begin
+//always @(posedge Clk_ik) begin  
+always @* begin  
     Ack_o                 	<= #dly 1'b0;
     Dat_ob32              	<= #dly 32'h0;
     StbIntManager_o       	<= #dly 1'b0;
@@ -71,6 +72,7 @@ always @(posedge Clk_ik) begin
     StbAppSlaveBus_o  <= #dly 1'b0;
 	StbI2cIoExpAndMux_o <= #dly 1'b0;
 	StbI2cWrProm_o	<= #dly 1'b0;  
+	StbWrpcSlaveBus_o <= #dly 1'b0;  
 	case (SelectedModule_b8)
 		c_SelIntManager: begin            
 			StbIntManager_o <= #dly  Stb_i;
@@ -101,7 +103,12 @@ always @(posedge Clk_ik) begin
 			StbAppSlaveBus_o <= #dly Stb_i;
 			Dat_ob32 <= #dly DatAppSlaveBus_ib32;
 			Ack_o <= #dly AckAppSlaveBus_i;
-		end    
+		end
+		c_SelWrPtpCore: begin
+			StbWrpcSlaveBus_o <= #dly Stb_i;
+			Dat_ob32 <= #dly DatWrpcSlaveBus_ib32;
+			Ack_o <= #dly AckWrpcSlaveBus_i;
+		end
 	endcase
 end 
     

Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v

@@ -175,9 +175,11 @@ always @(posedge Clk_ik) begin
       end
       if (RoraTimeoutCounter_c10==g_ClocksIn2us) RoraTimeoutCounter_c10 <= #1 10'h3ff;
       else if (~&RoraTimeoutCounter_c10) RoraTimeoutCounter_c10 <= #1 RoraTimeoutCounter_c10 + 1'b1;
+      InternalDataReg_b31 <= #1 InternalDataReg_b31;      
       WbCyc_o  <= #1 1'b0;
       WbStb_o  <= #1 1'b0;
       WbWe_o  <= #1 1'b0;
+      WbDat_ob32  <= #1 WbDat_ob32;
       WbTimeoutCounter_c14 <= #1 'h0;
 //state dependent assignments   
       case(State_qb3)
@@ -198,12 +200,17 @@ always @(posedge Clk_ik) begin
       s_RdWaitWbAnswer: begin
          VmeDataBuffsOutEnable_e  <= #1 1'b1;
          VmeAccess_o  <= #1 1'b1;
-         WbCyc_o  <= #1 1'b1;
-         WbStb_o  <= #1 1'b1;
          WbWe_o  <= #1 1'b0;
          WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
-         if (WbAck_i) InternalDataReg_b31 <= #1 WbDat_ib32;
-         else if (&WbTimeoutCounter_c14) InternalDataReg_b31 <= #1 32'hFFFF_FFFF;
+         if (WbAck_i) begin
+	    WbStb_o  <= #1 1'b0;
+            WbCyc_o  <= #1 1'b0;
+	    InternalDataReg_b31 <= #1 WbDat_ib32;
+	 end else begin
+	    WbStb_o  <= #1 1'b1;
+            WbCyc_o  <= #1 1'b1;
+	    if (&WbTimeoutCounter_c14) InternalDataReg_b31 <= #1 32'hFFFF_FFFF;
+	 end
       end 
       s_RdCloseVmeCycle: begin
          VmeDataBuffsOutEnable_e  <= #1 1'b1;
@@ -215,6 +222,8 @@ always @(posedge Clk_ik) begin
          VmeAccess_o  <= #1 1'b1;
          if (WbTimeoutCounter_c14==14'h1) begin
             VmeDtAck_on  <= #1 1'b0;    //delaying of 1 cycle extra
+            WbDat_ob32 <= #1 VmeD_iob32;
+/* -----\/----- EXCLUDED -----\/-----
             WbDat_ob32 <= #1 VmeD_iob32; 
             WbCyc_o  <= #1 1'b1;
             WbWe_o  <= #1 1'b1;
@@ -225,20 +234,22 @@ always @(posedge Clk_ik) begin
             WbCyc_o  <= #1 WbCyc_o;
             WbWe_o  <= #1 WbWe_o;
             WbStb_o  <= #1 WbStb_o;             
+ -----/\----- EXCLUDED -----/\----- */
          end
          if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
          if (NextState_ab3==s_WrWaitWbAnswer && VmeAm_ib6==6'h0B) VmeAddressInternal_b30 <= #1 VmeAddressInternal_b30 + 1'b1;          
       end
       s_WrWaitWbAnswer: begin
          VmeAccess_o  <= #1 1'b0;
+         VmeDtAck_on  <= #1 1'b0;
          if (WbAck_i) begin
             WbCyc_o  <= #1 1'b0;
             WbWe_o  <= #1 1'b0;
             WbStb_o  <= #1 1'b0;
          end else begin
-            WbCyc_o  <= #1 WbCyc_o;
-            WbWe_o  <= #1 WbWe_o;
-            WbStb_o  <= #1 WbStb_o;        
+            WbCyc_o  <= #1 1'b1;
+            WbWe_o  <= #1 1'b1;
+            WbStb_o  <= #1 1'b1;
          end
          if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
       end
@@ -262,4 +273,4 @@ always @(posedge Clk_ik) begin
    end
 end
    
-endmodule   
\ No newline at end of file
+endmodule