Commit 31e051cf authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev] fully merged WR-Btrain, tested with signal-tap, verified correct...

[WR-dev] fully merged WR-Btrain, tested with signal-tap, verified correct reception and decoding of Bvalues
parent 62c57f41
......@@ -4,3 +4,6 @@
[submodule "Hdl/FpgaModules/SystemSpecific/wr-cores"]
path = Hdl/FpgaModules/SystemSpecific/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "Hdl/FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit"]
path = Hdl/FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit
url = ssh://git@gitlab.cern.ch:7999/BTrain-TEAM/PS-BTrain-over-WhiteRabbit.git
......@@ -27,13 +27,13 @@ module AddrDecoderWBApp(
localparam dly = 1;
reg [1:0] SelectedModule_b2;
reg [2:0] SelectedModule_b2;
localparam c_SelNothing = 2'd0,
c_SelAppRevisionId = 2'd1,
c_SelCtrlReg = 2'd2,
c_SelStatReg = 2'd3,
c_SelWRBtarin = 2'd4;
localparam c_SelNothing = 3'd0,
c_SelAppRevisionId = 3'd1,
c_SelCtrlReg = 3'd2,
c_SelStatReg = 3'd3,
c_SelWRBtarin = 3'd4;
always @*
casez(Adr_ib21)
......@@ -70,8 +70,9 @@ always @(posedge Clk_ik) begin
StbWrBtrain_o <= #dly Stb_i;
Dat_ob32 <= #dly DatWrBtrain_ib32;
Ack_o <= #dly AckWrBtrain_i;
end
end
default:;
endcase
end
endmodule
\ No newline at end of file
endmodule
......@@ -65,10 +65,8 @@ module VfcHdApplication
input FmcGbtClk1M2CLeft_ik, //differential signal
input FmcGbtClk0M2CRight_ik, //differential signal
input FmcGbtClk1M2CRight_ik, //differential signal
-----/\----- EXCLUDED -----/\----- */
//Clock sources and control
output OeSi57x_oe,
/* -----\/----- EXCLUDED -----\/-----
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
......@@ -125,36 +123,49 @@ module VfcHdApplication
output [24:0] WbMasterAdr_ob25,
output WbMasterWr_o,
output [31:0] WbMasterDat_ob32,
-----/\----- EXCLUDED -----/\----- */
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
//LED control
/* -----\/----- EXCLUDED -----\/-----
output [1:0] TopLed_ob2,
output [3:0] BottomLed_ob4,
-----/\----- EXCLUDED -----/\----- */
//BST input
input BstOn_i,
input BunchClk_ik,
input TurnClk_ip,
input [5:0] BstByteAddress_ib5,
input [7:0] BstByte_ib8,
-----/\----- EXCLUDED -----/\----- */
//Interrupt
/* -----\/----- EXCLUDED -----\/-----
output [23:0] InterruptRequest_opb24,
/* -----\/----- EXCLUDED -----\/-----
//Ethernet streamer
output StreamerClk_ok,
output [31:0] StreamerData_ob32,
output SreamerDav_o,
output StreamerPckt_o,
-----/\----- EXCLUDED -----/\----- */
input StreamerWait_i
//GPIO direction
/* -----\/----- EXCLUDED -----\/-----
output GpIo1DirOut_o,
output GpIo2DirOut_o,
output GpIo34DirOut_o
-----/\----- EXCLUDED -----/\----- */
//WR Btrain interface
output [207:0] WrBtrainTxData_o,
output WrBtrainTxValid_o,
input WrBtrainTxDreq_i,
output WrBtrainTxLast_o,
output WrBtrainTxFlush_o,
input WrBtrainRxFirst_i,
input WrBtrainRxLast_i,
input [207:0] WrBtrainRxData_i,
input WrBtrainRxValid_i,
output WrBtrainRxDreq_o,
//WRPC timecode input
input WrpcTmTimeValid_i,
input [39:0] WrpcTmTai_i,
input [27:0] WrpcTmCycles_i,
//WRPC system clock
input WrpcSysClk_ik
);
//****************************
......@@ -179,26 +190,19 @@ wire [31:0] Reg1Value_b32;
wire [31:0] Reg2Value_b32;
wire [31:0] Reg3Value_b32;
// WR-Btrain stuff -- temporary loopback (lb)
wire [207:0] LoobackData;
wire LoobackValid;
wire LoobackDreq;
wire LoobackLast;
wire LoobackFlash;
wire [31:0] Bvalue;
//****************************
//Fixed assignments
//****************************
assign OeSi57x_oe = 1'b1;
//assign OeSi57x_oe = 1'b1;
//****************************
//Clocking
//****************************
assign Clk_k = GbitTrxClkRefR_ik; //~125MHz
//assign Clk_k = GbitTrxClkRefR_ik; //~125MHz
assign Clk_k = WrpcSysClk_ik;
assign WbClk_ok = Clk_k;
//****************************
......@@ -299,17 +303,17 @@ i_WrBtrainWrapper (
.clk_i (Clk_k),
.rst_n_i (~Reset_irqp),
.tx_data_o (LoobackData),
.tx_valid_o (LoobackValid),
.tx_dreq_i (LoobackDreq),
.tx_last_o (LoobackLast),
.tx_flush_o (LoobackFlash),
.tx_data_o (WrBtrainTxData_o),
.tx_valid_o (WrBtrainTxValid_o),
.tx_dreq_i (WrBtrainTxDreq_i),
.tx_last_o (WrBtrainTxLast_o),
.tx_flush_o (WrBtrainTxFlush_o),
.rx_data_i (LoobackData),
.rx_valid_i (LoobackValid),
.rx_first_i (LoobackFlash),
.rx_dreq_o (LoobackDreq),
.rx_last_i (LoobackLast),
.rx_data_i (WrBtrainRxData_i),
.rx_valid_i (WrBtrainRxValid_i),
.rx_first_i (WrBtrainRxFirst_i),
.rx_dreq_o (WrBtrainRxDreq_o),
.rx_last_i (WrBtrainRxLast_i),
.Bvalue_o (),
......
Subproject commit 802d56708174d2b955940d6697e27763913c9181
......@@ -7,7 +7,7 @@
-- Dimitrios lampridis
-- Company : GSI
-- Created : 2013-05-14
-- Last update: 2016-08-09
-- Last update: 2016-08-31
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -55,7 +55,7 @@ entity wr_arria5_phy is
port (
clk_reconf_i : in std_logic; -- 100 MHz
clk_phy_i : in std_logic; -- feeds transmitter CMU and CRU
locked_o : out std_logic; -- Is the rx_rbclk valid?
ready_o : out std_logic; -- Is the PHY ready?
loopen_i : in std_logic; -- local loopback enable (Tx->Rx), active hi
drop_link_i : in std_logic; -- Kill the link?
......@@ -188,7 +188,7 @@ begin
tx_disparity_o <= '0';
tx_enc_err_o <= '0';
locked_o <= pll_locked and tx_ready and not reconfig_busy;
ready_o <= pll_locked and tx_ready and rx_ready and not reconfig_busy;
-- Slow registered signals out of the GXB
p_rx_regs : process(clk_rx_gxb) is
......
......@@ -10,40 +10,40 @@ module VfcHdSystem
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
// VME interface
input VmeAs_in,
input [5:0] VmeAm_ib6,
input [31:1] VmeA_iob31,
input VmeLWord_ion,
output VmeAOe_oen,
output VmeADir_o,
input [1:0] VmeDs_inb2,
input VmeWrite_in,
inout [31:0] VmeD_iob32,
output VmeDOe_oen,
output VmeDDir_o,
output VmeDtAckOe_o,
output [7:1] VmeIrq_ob7,
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
input VmeAs_in,
input [5:0] VmeAm_ib6,
input [31:1] VmeA_iob31,
input VmeLWord_ion,
output VmeAOe_oen,
output VmeADir_o,
input [1:0] VmeDs_inb2,
input VmeWrite_in,
inout [31:0] VmeD_iob32,
output VmeDOe_oen,
output VmeDDir_o,
output VmeDtAckOe_o,
output [7:1] VmeIrq_ob7,
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
/* -----\/----- EXCLUDED -----\/-----
input VmeSysClk_ik,
-----/\----- EXCLUDED -----/\----- */
input VmeSysReset_irn,
input VmeSysReset_irn,
//System SFPs Gbit lanes
// input BstSfpRx_i, //Differential
// output BstSfpTx_o, //Differential
input EthSfpRx_i, //Differential
output EthSfpTx_o, //Differential
input EthSfpRx_i, //Differential
output EthSfpTx_o, //Differential
//I2C Mux and IO expanders
inout I2cMuxSda_io,
output I2cMuxScl_ok,
input I2CMuxIntN0_in,
input I2CMuxIntN1_in,
input I2CIoExpIntApp12_in,
input I2CIoExpIntApp34_in,
input I2CIoExpIntBstEth_in,
input I2CIoExpIntBlmIn_in,
inout I2cMuxSda_io,
output I2cMuxScl_ok,
input I2CMuxIntN0_in,
input I2CMuxIntN1_in,
input I2CIoExpIntApp12_in,
input I2CIoExpIntApp34_in,
input I2CIoExpIntBstEth_in,
input I2CIoExpIntBlmIn_in,
/* -----\/----- EXCLUDED -----\/-----
//BST
input BstDataIn_i,
......@@ -51,36 +51,36 @@ module VfcHdSystem
input CdrDataOut_i,
-----/\----- EXCLUDED -----/\----- */
//ADC Voltage monitoring
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_o,
output VAdcSclk_ok,
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_o,
output VAdcSclk_ok,
//Clock sources and control
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
//Fmc Voltage control
output VadjCs_o,
output VadjSclk_ok,
output VadjDin_o,
output VadjCs_o,
output VadjSclk_ok,
output VadjDin_o,
/* -----\/----- EXCLUDED -----\/-----
output VfmcEnableN_oen,
-----/\----- EXCLUDED -----/\----- */
//SW1
input [4:0] NoGa_ib5,
input UseGa_i,
input [4:0] NoGa_ib5,
input UseGa_i,
/* -----\/----- EXCLUDED -----\/-----
//Pcb Revision resistor network
input [7:0] PcbRev_ib7,
-----/\----- EXCLUDED -----/\----- */
//WR PROM
inout WrPromSda_io,
output WrPromScl_ok,
inout WrPromSda_io,
output WrPromScl_ok,
//Specials
inout TempIdDq_ioz,
inout TempIdDq_ioz,
/* -----\/----- EXCLUDED -----\/-----
output ResetFpgaConfigN_orn,
-----/\----- EXCLUDED -----/\----- */
......@@ -88,22 +88,22 @@ module VfcHdSystem
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
//Reset
output Reset_orqp, //Reset Synchronous with the WbClk_ik
input ResetRequest_iqp, //Request to issue a reset
output Reset_orqp, //Reset Synchronous with the WbClk_ik
input ResetRequest_iqp, //Request to issue a reset
//WishBone
input WbClk_ik,
output reg WbMasterCyc_o,
output reg WbMasterStb_o,
input WbClk_ik,
output reg WbMasterCyc_o,
output reg WbMasterStb_o,
output reg [24:0] WbMasterAdr_ob25,
output reg WbMasterWr_o,
output reg WbMasterWr_o,
output reg [31:0] WbMasterDat_ob32,
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
input WbSlaveCyc_i,
input WbSlaveStb_i,
input [24:0] WbSlaveAdr_ib25,
input WbSlaveWr_i,
input [31:0] WbSlaveDat_ib32,
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
input WbSlaveCyc_i,
input WbSlaveStb_i,
input [24:0] WbSlaveAdr_ib25,
input WbSlaveWr_i,
input [31:0] WbSlaveDat_ib32,
/* -----\/----- EXCLUDED -----\/-----
output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o,
......@@ -118,23 +118,39 @@ module VfcHdSystem
output [5:0] BstByteAddress_ob5,
-----/\----- EXCLUDED -----/\----- */
//Interrupt
input [23:0] InterruptRequest_ipb24,
//Ethernet streamer
input StreamerClk_ik,
input [31:0] StreamerData_ib32,
input SreamerDav_i,
input StreamerPckt_i,
input [23:0] InterruptRequest_ipb24,
/* -----\/----- EXCLUDED -----\/-----
//Ethernet streamer
input StreamerClk_ik,
input [31:0] StreamerData_ib32,
input SreamerDav_i,
input StreamerPckt_i,
output StreamerWait_o,
//GPIO direction
input GpIo1DirOut_i,
input GpIo2DirOut_i,
input GpIo34DirOut_i,
-----/\----- EXCLUDED -----/\----- */
// WRPC status
output WrpcTmTimeValid_o,
output WrpcLedLink_o,
output WrpcLedAct_o
//WR Btrain interface
input [207:0] WrBtrainTxData_i,
input WrBtrainTxValid_i,
output WrBtrainTxDreq_o,
input WrBtrainTxLast_i,
input WrBtrainTxFlush_i,
output WrBtrainRxFirst_o,
output WrBtrainRxLast_o,
output [207:0] WrBtrainRxData_o,
output WrBtrainRxValid_o,
input WrBtrainRxDreq_i,
//WRPC timecode output
output WrpcTmTimeValid_o,
output [39:0] WrpcTmTai_o,
output [27:0] WrpcTmCycles_o,
// WRPC status LEDs
output WrpcLedLink_o,
output WrpcLedAct_o,
// WRPC system clock output
output WrpcSysClk_ok
);
//****************************
......@@ -186,7 +202,7 @@ wire [31:0] WbAdr_b32;
//The WbClk_ik is used only for the interface with the application module
wire Clk_k; // = GbitTrxClkRefR_ik;
assign WrpcSysClk_ok = Clk_k;
//****************************
//Reset
......@@ -421,7 +437,8 @@ I2CMaster #(.g_CycleLenght(10'd256))
//****************************
//WR PTP core Wrapper
//****************************
WrpcWrapper #(.g_simulation(0), .g_dpram_initf("wrc.mif"))
//WrpcWrapper #(.g_simulation(0), .g_dpram_initf("wrc.mif"))
WrpcWrapper #(.g_simulation(0), .g_dpram_initf(""))
i_WrpcWrapper
(
.clk_125m_i(GbitTrxClkRefR_ik),
......@@ -447,7 +464,19 @@ I2CMaster #(.g_CycleLenght(10'd256))
.wb_err_o(),
.wb_rty_o(),
.wb_stall_o(),
.trans_tx_data_i(WrBtrainTxData_i),
.trans_tx_valid_i(WrBtrainTxValid_i),
.trans_tx_dreq_o(WrBtrainTxDreq_o),
.trans_tx_last_i(WrBtrainTxLast_i),
.trans_tx_flush_i(WrBtrainTxFlush_i),
.trans_rx_first_o(WrBtrainRxFirst_o),
.trans_rx_last_o(WrBtrainRxLast_o),
.trans_rx_data_o(WrBtrainRxData_o),
.trans_rx_valid_o(WrBtrainRxValid_o),
.trans_rx_dreq_i(WrBtrainRxDreq_i),
.tm_time_valid_o(WrpcTmTimeValid_o),
.tm_tai_o(WrpcTmTai_o),
.tm_cycles_o(WrpcTmCycles_o),
.led_link_o(WrpcLedLink_o),
.led_act_o(WrpcLedAct_o)
);
......
......@@ -37,12 +37,15 @@ use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.WRBtrain_pkg.all; -- needed for c_STREAMER_DATA_WIDTH
use work.wr_transmission_pkg.all; -- needed for c_WR_TRANS_ARR_SIZE_*
entity WrpcWrapper is
generic(
g_simulation : integer := 0;
g_dpram_initf : string := "default");
g_st_data_width : integer := c_STREAMER_DATA_WIDTH; -- wr streamer data width
g_simulation : integer := 0;
g_dpram_initf : string := "default");
port (
---------------------------------------------------------------------------
......@@ -96,12 +99,46 @@ entity WrpcWrapper is
wb_stall_o : out std_logic;
---------------------------------------------------------------------------
-- WRPC timing interface and status
-- BTrain RX/TX interface (application-specific)
---------------------------------------------------------------------------
-- Data word to be sent.
trans_tx_data_i : in std_logic_vector(g_st_data_width-1 downto 0);
-- 1 indicates that the tx_data_i contains a valid data word.
trans_tx_valid_i : in std_logic;
-- Synchronous data request: if active, the user may send a data word in
-- the following clock cycle.
trans_tx_dreq_o : out std_logic;
-- Last signal. Can be used to indicate the last data word in a larger
-- block of samples (see documentation for more details).
trans_tx_last_i : in std_logic := '1';
-- Flush input. When asserted, the streamer will immediatly send out all
-- the data that is stored in its TX buffer, ignoring g_tx_timeout.
trans_tx_flush_i : in std_logic := '0';
-- 1 indicates the 1st word of the data block on rx_data_o.
trans_rx_first_o : out std_logic;
-- 1 indicates the last word of the data block on rx_data_o.
trans_rx_last_o : out std_logic;
-- Received data.
trans_rx_data_o : out std_logic_vector(g_st_data_width-1 downto 0);
-- 1 indicted that rx_data_o is outputting a valid data word.
trans_rx_valid_o : out std_logic;
-- Synchronous data request input: when 1, the streamer may output another
-- data word in the subsequent clock cycle.
trans_rx_dreq_i : in std_logic;
---------------------------------------------------------------------------
-- Timecode output
---------------------------------------------------------------------------
tm_time_valid_o : out std_logic;
led_link_o : out std_logic;
led_act_o : out std_logic);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- WRPC status LEDs
---------------------------------------------------------------------------
led_link_o : out std_logic;
led_act_o : out std_logic);
end entity WrpcWrapper;
......@@ -109,7 +146,7 @@ end entity WrpcWrapper;
architecture struct of WrpcWrapper is
-----------------------------------------------------------------------------
-- Component declarations
-- Component declarations (platform-specific)
-----------------------------------------------------------------------------
component AlteraPllSys is
......@@ -134,7 +171,7 @@ architecture struct of WrpcWrapper is
port (
clk_reconf_i : in std_logic;
clk_phy_i : in std_logic;
locked_o : out std_logic;
ready_o : out std_logic;
loopen_i : in std_logic;
drop_link_i : in std_logic;
tx_clk_o : out std_logic;
......@@ -150,7 +187,7 @@ architecture struct of WrpcWrapper is
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component wr_arria5_phy;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
......@@ -177,7 +214,7 @@ architecture struct of WrpcWrapper is
signal dac_dpll_data : std_logic_vector(15 downto 0);
-- PHY
signal gxb_locked : std_logic;
signal phy_ready : std_logic;
signal phy_loopen : std_logic;
signal phy_rst : std_logic;
signal phy_tx_clk : std_logic;
......@@ -193,10 +230,29 @@ architecture struct of WrpcWrapper is
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
-- Timecode interface
signal tm_time_valid : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
-- WR fabric interface
signal wrf_src_out : t_wrf_source_out;
signal wrf_src_in : t_wrf_source_in;
signal wrf_snk_out : t_wrf_sink_out;
signal wrf_snk_in : t_wrf_sink_in;
-- WR SNMP
signal aux_diag_in : t_generic_word_array(c_WR_TRANS_ARR_SIZE_OUT-1 downto 0);
signal aux_diag_out : t_generic_word_array(c_WR_TRANS_ARR_SIZE_IN-1 downto 0);
-- External WB interface
signal wb_slave_out : t_wishbone_slave_out;
signal wb_slave_in : t_wishbone_slave_in;
-- Aux WB interface
signal aux_master_out : t_wishbone_master_out;
signal aux_master_in : t_wishbone_master_in;
begin -- architecture struct
-----------------------------------------------------------------------------
......@@ -229,7 +285,6 @@ begin -- architecture struct
rstlogic_arst_n <= pll_sys_locked and
pll_dmtd_locked and
(not arst_i);
--gxb_locked and
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= pll_clk_62m5;
......@@ -281,9 +336,9 @@ begin -- architecture struct
port map (
clk_reconf_i => pll_clk_100m,
clk_phy_i => pll_clk_125m,
locked_o => gxb_locked,
ready_o => phy_ready,
loopen_i => phy_loopen,
drop_link_i => '0',
drop_link_i => phy_rst,
tx_clk_o => phy_tx_clk,
tx_data_i => phy_tx_data,
tx_k_i => phy_tx_k_bit,
......@@ -311,7 +366,11 @@ begin -- architecture struct
g_aux_clks => 1,
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_dpram_initf => g_dpram_initf)
g_dpram_initf => g_dpram_initf,
g_diag_id => 0,
g_diag_ver => 0,
g_diag_ro_size => c_WR_TRANS_ARR_SIZE_OUT,
g_diag_rw_size => c_WR_TRANS_ARR_SIZE_IN)
port map (
clk_sys_i => pll_clk_62m5,
clk_dmtd_i => pll_clk_dmtd,
......@@ -340,13 +399,12 @@ begin -- architecture struct
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_rdy_i => gxb_locked,
phy_loopen_o => open,
phy_rdy_i => phy_ready,