Commit 37654f74 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev] migrated PHYs and PLLs into wr-cores

parent 9dc0ee45
......@@ -2,5 +2,5 @@
path = Hdl/FpgaModules/GeneralPurpose/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "Hdl/FpgaModules/SystemSpecific/wr-cores"]
path = Hdl/FpgaModules/SystemSpecific/wr-cores
path = Hdl/FpgaModules/SystemSpecific/WhiteRabbit/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
-------------------------------------------------------------------------------
-- Title : Deterministic Altera PHY wrapper - Arria 5
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : wr_arria5_phy.vhd
-- Authors : Wesley W. Terpstra
-- Dimitrios lampridis
-- Company : GSI
-- Created : 2013-05-14
-- Last update: 2016-08-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single channel wrapper for deterministic PHY
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 GSI / Wesley W. Terpstra
-- Copyright (c) 2016 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-12 1.0 terpstra Rewrote using deterministic mode
-- 2013-08-22 1.1 terpstra Now runs on arria5 hardware
-- 2016-08-09 2.0 dlamprid Use Altera-provided 8b10b blocks and
-- get rid unnecessary clock controllers
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
entity wr_arria5_phy is
port (
clk_reconf_i : in std_logic; -- 100 MHz
clk_phy_i : in std_logic; -- feeds transmitter CMU and CRU
locked_o : out std_logic; -- Is the rx_rbclk valid?
loopen_i : in std_logic; -- local loopback enable (Tx->Rx), active hi
drop_link_i : in std_logic; -- Kill the link?
tx_clk_o : out std_logic; -- clock used for TX data;
tx_data_i : in std_logic_vector(7 downto 0); -- data input (8 bits, not 8b10b-encoded)
tx_k_i : in std_logic; -- 1 when tx_data_i contains a control code, 0 when it's a data byte
tx_disparity_o : out std_logic; -- disparity of the currently transmitted 8b10b code (1 = plus, 0 = minus).
tx_enc_err_o : out std_logic; -- error encoding
rx_rbclk_o : out std_logic; -- RX recovered clock
rx_data_o : out std_logic_vector(7 downto 0); -- 8b10b-decoded data output.
rx_k_o : out std_logic; -- 1 when the byte on rx_data_o is a control code
rx_enc_err_o : out std_logic; -- encoding error indication
rx_bitslide_o : out std_logic_vector(3 downto 0); -- RX bitslide indication, indicating the delay of the RX path of the transceiver (in UIs). Must be valid when rx_data_o is valid.
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end wr_arria5_phy;
architecture rtl of wr_arria5_phy is
component arria5_phy_reconf
port(
reconfig_busy : out std_logic;
mgmt_clk_clk : in std_logic;
mgmt_rst_reset : in std_logic;
reconfig_mgmt_address : in std_logic_vector(6 downto 0);
reconfig_mgmt_read : in std_logic;
reconfig_mgmt_readdata : out std_logic_vector(31 downto 0);
reconfig_mgmt_waitrequest : out std_logic;
reconfig_mgmt_write : in std_logic;
reconfig_mgmt_writedata : in std_logic_vector(31 downto 0);
reconfig_to_xcvr : out std_logic_vector(139 downto 0);
reconfig_from_xcvr : in std_logic_vector(91 downto 0));
end component;
component arria5_phy is
port (
phy_mgmt_clk : in std_logic := '0';
phy_mgmt_clk_reset : in std_logic := '0';
phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0');
phy_mgmt_read : in std_logic := '0';
phy_mgmt_readdata : out std_logic_vector(31 downto 0);
phy_mgmt_waitrequest : out std_logic;
phy_mgmt_write : in std_logic := '0';
phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0');
tx_ready : out std_logic;
rx_ready : out std_logic;
pll_ref_clk : in std_logic_vector(0 downto 0) := (others => '0');
tx_serial_data : out std_logic_vector(0 downto 0);
tx_bitslipboundaryselect : in std_logic_vector(4 downto 0) := (others => '0');
pll_locked : out std_logic_vector(0 downto 0);
rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0');
rx_runningdisp : out std_logic_vector(0 downto 0);
rx_disperr : out std_logic_vector(0 downto 0);
rx_errdetect : out std_logic_vector(0 downto 0);
rx_bitslipboundaryselectout : out std_logic_vector(4 downto 0);
tx_clkout : out std_logic_vector(0 downto 0);
rx_clkout : out std_logic_vector(0 downto 0);
tx_parallel_data : in std_logic_vector(7 downto 0) := (others => '0');
tx_datak : in std_logic_vector(0 downto 0) := (others => '0');
rx_parallel_data : out std_logic_vector(7 downto 0);
rx_datak : out std_logic_vector(0 downto 0);
reconfig_from_xcvr : out std_logic_vector(91 downto 0);
reconfig_to_xcvr : in std_logic_vector(139 downto 0) := (others => '0'));
end component arria5_phy;
signal clk_rx_gxb : std_logic; -- external fabric
signal pll_locked : std_logic;
signal rx_ready : std_logic;
signal tx_ready : std_logic;
signal reconfig_busy : std_logic;
signal xcvr_to_reconfig : std_logic_vector(91 downto 0);
signal reconfig_to_xcvr : std_logic_vector(139 downto 0);
signal rx_bitslipboundaryselectout : std_logic_vector (4 downto 0);
begin
rx_rbclk_o <= clk_rx_gxb;
-- Altera PHY calibration block
U_Reconf : arria5_phy_reconf
port map (
reconfig_busy => reconfig_busy,
mgmt_clk_clk => clk_reconf_i,
mgmt_rst_reset => drop_link_i,
reconfig_mgmt_address => (others => '0'),
reconfig_mgmt_read => '0',
reconfig_mgmt_readdata => open,
reconfig_mgmt_waitrequest => open,
reconfig_mgmt_write => '0',
reconfig_mgmt_writedata => (others => '0'),
reconfig_to_xcvr => reconfig_to_xcvr,
reconfig_from_xcvr => xcvr_to_reconfig);
U_The_PHY : arria5_phy
port map (
phy_mgmt_clk => clk_reconf_i,
phy_mgmt_clk_reset => drop_link_i,
phy_mgmt_address => "010000101", -- 0x085
phy_mgmt_read => '0',
phy_mgmt_readdata => open,
phy_mgmt_waitrequest => open,
phy_mgmt_write => '1',
phy_mgmt_writedata => (0 => '1', others => '0'),
tx_ready => tx_ready,
rx_ready => rx_ready,
pll_ref_clk(0) => clk_phy_i,
tx_serial_data(0) => pad_txp_o,
tx_bitslipboundaryselect => (others => '0'),
pll_locked(0) => pll_locked,
rx_serial_data(0) => pad_rxp_i,
rx_runningdisp => open,
rx_disperr => open,
rx_errdetect(0) => rx_enc_err_o,
rx_bitslipboundaryselectout => rx_bitslipboundaryselectout,
tx_clkout(0) => tx_clk_o,
rx_clkout(0) => clk_rx_gxb,
tx_parallel_data => tx_data_i,
tx_datak(0) => tx_k_i,
rx_parallel_data => rx_data_o,
rx_datak(0) => rx_k_o,
reconfig_from_xcvr => xcvr_to_reconfig,
reconfig_to_xcvr => reconfig_to_xcvr);
-- [TODO] DL: not sure how to get these yet
tx_disparity_o <= '0';
tx_enc_err_o <= '0';
locked_o <= pll_locked and tx_ready and not reconfig_busy;
-- Slow registered signals out of the GXB
p_rx_regs : process(clk_rx_gxb) is
begin
if rising_edge(clk_rx_gxb) then
rx_bitslide_o <= rx_bitslipboundaryselectout(3 downto 0);
end if;
end process;
end rtl;
files = [
"wr_arria5_phy.vhd",
"wr_arria5_phy.qip",
]
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 528 584)
(text "arria5_phy" (rect 233 -1 276 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 568 20 580)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "phy_mgmt_clk" (rect 0 0 61 12)(font "Arial" (font_size 8)))
(text "phy_mgmt_clk" (rect 4 61 76 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 160 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "phy_mgmt_clk_reset" (rect 0 0 87 12)(font "Arial" (font_size 8)))
(text "phy_mgmt_clk_reset" (rect 4 101 112 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 160 112)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "phy_mgmt_address[8..0]" (rect 0 0 102 12)(font "Arial" (font_size 8)))
(text "phy_mgmt_address[8..0]" (rect 4 141 136 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 160 152)(line_width 3))
)
(port
(pt 0 168)
(input)
(text "phy_mgmt_read" (rect 0 0 68 12)(font "Arial" (font_size 8)))
(text "phy_mgmt_read" (rect 4 157 82 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 160 168)(line_width 1))
)
(port
(pt 0 216)
(input)
(text "phy_mgmt_write" (rect 0 0 68 12)(font "Arial" (font_size 8)))
(text "phy_mgmt_write" (rect 4 205 88 216)(font "Arial" (font_size 8)))
(line (pt 0 216)(pt 160 216)(line_width 1))
)
(port
(pt 0 232)
(input)
(text "phy_mgmt_writedata[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
(text "phy_mgmt_writedata[31..0]" (rect 4 221 154 232)(font "Arial" (font_size 8)))
(line (pt 0 232)(pt 160 232)(line_width 3))
)
(port
(pt 0 272)
(input)
(text "pll_ref_clk" (rect 0 0 41 12)(font "Arial" (font_size 8)))
(text "pll_ref_clk" (rect 4 261 70 272)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 160 272)(line_width 1))
)
(port
(pt 0 312)
(input)
(text "tx_bitslipboundaryselect[4..0]" (rect 0 0 114 12)(font "Arial" (font_size 8)))
(text "tx_bitslipboundaryselect[4..0]" (rect 4 301 184 312)(font "Arial" (font_size 8)))
(line (pt 0 312)(pt 160 312)(line_width 3))
)
(port
(pt 0 352)
(input)
(text "rx_serial_data" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "rx_serial_data" (rect 4 341 88 352)(font "Arial" (font_size 8)))
(line (pt 0 352)(pt 160 352)(line_width 1))
)
(port
(pt 0 392)
(input)
(text "tx_parallel_data[7..0]" (rect 0 0 81 12)(font "Arial" (font_size 8)))
(text "tx_parallel_data[7..0]" (rect 4 381 136 392)(font "Arial" (font_size 8)))
(line (pt 0 392)(pt 160 392)(line_width 3))
)
(port
(pt 0 432)
(input)
(text "tx_datak" (rect 0 0 34 12)(font "Arial" (font_size 8)))
(text "tx_datak" (rect 4 421 52 432)(font "Arial" (font_size 8)))
(line (pt 0 432)(pt 160 432)(line_width 1))
)
(port
(pt 0 472)
(input)
(text "reconfig_to_xcvr[139..0]" (rect 0 0 97 12)(font "Arial" (font_size 8)))
(text "reconfig_to_xcvr[139..0]" (rect 4 461 148 472)(font "Arial" (font_size 8)))
(line (pt 0 472)(pt 160 472)(line_width 3))
)
(port
(pt 0 184)
(output)
(text "phy_mgmt_readdata[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
(text "phy_mgmt_readdata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 160 184)(line_width 3))
)
(port
(pt 0 200)
(output)
(text "phy_mgmt_waitrequest" (rect 0 0 94 12)(font "Arial" (font_size 8)))
(text "phy_mgmt_waitrequest" (rect 4 189 124 200)(font "Arial" (font_size 8)))
(line (pt 0 200)(pt 160 200)(line_width 1))
)
(port
(pt 528 72)
(output)
(text "tx_ready" (rect 0 0 36 12)(font "Arial" (font_size 8)))
(text "tx_ready" (rect 482 61 530 72)(font "Arial" (font_size 8)))
(line (pt 528 72)(pt 352 72)(line_width 1))
)
(port
(pt 528 112)
(output)
(text "rx_ready" (rect 0 0 37 12)(font "Arial" (font_size 8)))
(text "rx_ready" (rect 481 101 529 112)(font "Arial" (font_size 8)))
(line (pt 528 112)(pt 352 112)(line_width 1))
)
(port
(pt 528 152)
(output)
(text "tx_serial_data" (rect 0 0 55 12)(font "Arial" (font_size 8)))
(text "tx_serial_data" (rect 456 141 540 152)(font "Arial" (font_size 8)))
(line (pt 528 152)(pt 352 152)(line_width 1))
)
(port
(pt 528 192)
(output)
(text "pll_locked" (rect 0 0 37 12)(font "Arial" (font_size 8)))
(text "pll_locked" (rect 478 181 538 192)(font "Arial" (font_size 8)))
(line (pt 528 192)(pt 352 192)(line_width 1))
)
(port
(pt 528 232)
(output)
(text "rx_runningdisp" (rect 0 0 57 12)(font "Arial" (font_size 8)))
(text "rx_runningdisp" (rect 453 221 537 232)(font "Arial" (font_size 8)))
(line (pt 528 232)(pt 352 232)(line_width 1))
)
(port
(pt 528 272)
(output)
(text "rx_disperr" (rect 0 0 41 12)(font "Arial" (font_size 8)))
(text "rx_disperr" (rect 475 261 535 272)(font "Arial" (font_size 8)))
(line (pt 528 272)(pt 352 272)(line_width 1))
)
(port
(pt 528 312)
(output)
(text "rx_errdetect" (rect 0 0 49 12)(font "Arial" (font_size 8)))
(text "rx_errdetect" (rect 465 301 537 312)(font "Arial" (font_size 8)))
(line (pt 528 312)(pt 352 312)(line_width 1))
)
(port
(pt 528 352)
(output)
(text "rx_bitslipboundaryselectout[4..0]" (rect 0 0 127 12)(font "Arial" (font_size 8)))
(text "rx_bitslipboundaryselectout[4..0]" (rect 368 341 566 352)(font "Arial" (font_size 8)))
(line (pt 528 352)(pt 352 352)(line_width 3))
)
(port
(pt 528 392)
(output)
(text "tx_clkout" (rect 0 0 35 12)(font "Arial" (font_size 8)))
(text "tx_clkout" (rect 482 381 536 392)(font "Arial" (font_size 8)))
(line (pt 528 392)(pt 352 392)(line_width 1))
)
(port
(pt 528 432)
(output)
(text "rx_clkout" (rect 0 0 36 12)(font "Arial" (font_size 8)))
(text "rx_clkout" (rect 481 421 535 432)(font "Arial" (font_size 8)))
(line (pt 528 432)(pt 352 432)(line_width 1))
)
(port
(pt 528 472)
(output)
(text "rx_parallel_data[7..0]" (rect 0 0 82 12)(font "Arial" (font_size 8)))
(text "rx_parallel_data[7..0]" (rect 423 461 555 472)(font "Arial" (font_size 8)))
(line (pt 528 472)(pt 352 472)(line_width 3))
)
(port
(pt 528 512)
(output)
(text "rx_datak" (rect 0 0 35 12)(font "Arial" (font_size 8)))
(text "rx_datak" (rect 483 501 531 512)(font "Arial" (font_size 8)))
(line (pt 528 512)(pt 352 512)(line_width 1))
)
(port
(pt 528 552)
(output)
(text "reconfig_from_xcvr[91..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
(text "reconfig_from_xcvr[91..0]" (rect 398 541 548 552)(font "Arial" (font_size 8)))
(line (pt 528 552)(pt 352 552)(line_width 3))
)
(drawing
(text "phy_mgmt_clk" (rect 76 43 224 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 165 67 348 144)(font "Arial" (color 0 0 0)))
(text "phy_mgmt_clk_reset" (rect 38 83 184 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 165 107 360 224)(font "Arial" (color 0 0 0)))
(text "phy_mgmt" (rect 100 123 248 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "address" (rect 165 147 372 304)(font "Arial" (color 0 0 0)))
(text "read" (rect 165 163 354 336)(font "Arial" (color 0 0 0)))
(text "readdata" (rect 165 179 378 368)(font "Arial" (color 0 0 0)))
(text "waitrequest" (rect 165 195 396 400)(font "Arial" (color 0 0 0)))
(text "write" (rect 165 211 360 432)(font "Arial" (color 0 0 0)))
(text "writedata" (rect 165 227 384 464)(font "Arial" (color 0 0 0)))
(text "tx_ready" (rect 353 43 754 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 67 680 144)(font "Arial" (color 0 0 0)))
(text "rx_ready" (rect 353 83 754 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 107 680 224)(font "Arial" (color 0 0 0)))
(text "pll_ref_clk" (rect 99 243 264 499)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 165 267 348 544)(font "Arial" (color 0 0 0)))
(text "tx_serial_data" (rect 353 123 790 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 147 680 304)(font "Arial" (color 0 0 0)))
(text "tx_bitslipboundaryselect" (rect 22 283 188 579)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 165 307 366 624)(font "Arial" (color 0 0 0)))
(text "pll_locked" (rect 353 163 766 339)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 187 680 384)(font "Arial" (color 0 0 0)))
(text "rx_serial_data" (rect 77 323 238 659)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 165 347 366 704)(font "Arial" (color 0 0 0)))
(text "rx_runningdisp" (rect 353 203 790 419)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 227 680 464)(font "Arial" (color 0 0 0)))
(text "rx_disperr" (rect 353 243 766 499)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 267 680 544)(font "Arial" (color 0 0 0)))
(text "rx_errdetect" (rect 353 283 778 579)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 307 680 624)(font "Arial" (color 0 0 0)))
(text "rx_bitslipboundaryselectout" (rect 353 323 868 659)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 347 680 704)(font "Arial" (color 0 0 0)))
(text "tx_clkout" (rect 353 363 760 739)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 387 680 784)(font "Arial" (color 0 0 0)))
(text "rx_clkout" (rect 353 403 760 819)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 427 680 864)(font "Arial" (color 0 0 0)))
(text "tx_parallel_data" (rect 68 363 232 739)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 165 387 366 784)(font "Arial" (color 0 0 0)))
(text "tx_datak" (rect 111 403 270 819)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 165 427 366 864)(font "Arial" (color 0 0 0)))
(text "rx_parallel_data" (rect 353 443 802 899)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 467 680 944)(font "Arial" (color 0 0 0)))
(text "rx_datak" (rect 353 483 754 979)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 322 507 680 1024)(font "Arial" (color 0 0 0)))
(text "reconfig_from_xcvr" (rect 353 523 814 1059)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reconfig_from_xcvr" (rect 261 547 630 1104)(font "Arial" (color 0 0 0)))
(text "reconfig_to_xcvr" (rect 64 443 224 899)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reconfig_to_xcvr" (rect 165 467 426 944)(font "Arial" (color 0 0 0)))
(text " altera_xcvr_det_latency " (rect 419 568 988 1146)(font "Arial" ))
(line (pt 160 32)(pt 352 32)(line_width 1))
(line (pt 352 32)(pt 352 568)(line_width 1))
(line (pt 160 568)(pt 352 568)(line_width 1))
(line (pt 160 32)(pt 160 568)(line_width 1))
(line (pt 161 52)(pt 161 76)(line_width 1))
(line (pt 162 52)(pt 162 76)(line_width 1))
(line (pt 161 92)(pt 161 116)(line_width 1))
(line (pt 162 92)(pt 162 116)(line_width 1))
(line (pt 161 132)(pt 161 236)(line_width 1))
(line (pt 162 132)(pt 162 236)(line_width 1))
(line (pt 351 52)(pt 351 76)(line_width 1))
(line (pt 350 52)(pt 350 76)(line_width 1))
(line (pt 351 92)(pt 351 116)(line_width 1))
(line (pt 350 92)(pt 350 116)(line_width 1))
(line (pt 161 252)(pt 161 276)(line_width 1))
(line (pt 162 252)(pt 162 276)(line_width 1))
(line (pt 351 132)(pt 351 156)(line_width 1))
(line (pt 350 132)(pt 350 156)(line_width 1))
(line (pt 161 292)(pt 161 316)(line_width 1))
(line (pt 162 292)(pt 162 316)(line_width 1))
(line (pt 351 172)(pt 351 196)(line_width 1))
(line (pt 350 172)(pt 350 196)(line_width 1))
(line (pt 161 332)(pt 161 356)(line_width 1))
(line (pt 162 332)(pt 162 356)(line_width 1))
(line (pt 351 212)(pt 351 236)(line_width 1))
(line (pt 350 212)(pt 350 236)(line_width 1))
(line (pt 351 252)(pt 351 276)(line_width 1))
(line (pt 350 252)(pt 350 276)(line_width 1))
(line (pt 351 292)(pt 351 316)(line_width 1))
(line (pt 350 292)(pt 350 316)(line_width 1))
(line (pt 351 332)(pt 351 356)(line_width 1))
(line (pt 350 332)(pt 350 356)(line_width 1))
(line (pt 351 372)(pt 351 396)(line_width 1))
(line (pt 350 372)(pt 350 396)(line_width 1))
(line (pt 351 412)(pt 351 436)(line_width 1))
(line (pt 350 412)(pt 350 436)(line_width 1))
(line (pt 161 372)(pt 161 396)(line_width 1))
(line (pt 162 372)(pt 162 396)(line_width 1))
(line (pt 161 412)(pt 161 436)(line_width 1))
(line (pt 162 412)(pt 162 436)(line_width 1))
(line (pt 351 452)(pt 351 476)(line_width 1))
(line (pt 350 452)(pt 350 476)(line_width 1))
(line (pt 351 492)(pt 351 516)(line_width 1))
(line (pt 350 492)(pt 350 516)(line_width 1))
(line (pt 351 532)(pt 351 556)(line_width 1))
(line (pt 350 532)(pt 350 556)(line_width 1))
(line (pt 161 452)(pt 161 476)(line_width 1))
(line (pt 162 452)(pt 162 476)(line_width 1))
(line (pt 0 0)(pt 528 0)(line_width 1))
(line (pt 528 0)(pt 528 584)(line_width 1))
(line (pt 0 584)(pt 528 584)(line_width 1))
(line (pt 0 0)(pt 0 584)(line_width 1))
)
)
component arria5_phy is
port (
phy_mgmt_clk : in std_logic := 'X'; -- clk
phy_mgmt_clk_reset : in std_logic := 'X'; -- reset
phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
phy_mgmt_read : in std_logic := 'X'; -- read
phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- readdata
phy_mgmt_waitrequest : out std_logic; -- waitrequest
phy_mgmt_write : in std_logic := 'X'; -- write
phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
tx_ready : out std_logic; -- export
rx_ready : out std_logic; -- export
pll_ref_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
tx_serial_data : out std_logic_vector(0 downto 0); -- export
tx_bitslipboundaryselect : in std_logic_vector(4 downto 0) := (others => 'X'); -- export
pll_locked : out std_logic_vector(0 downto 0); -- export
rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
rx_runningdisp : out std_logic_vector(0 downto 0); -- export
rx_disperr : out std_logic_vector(0 downto 0); -- export
rx_errdetect : out std_logic_vector(0 downto 0); -- export
rx_bitslipboundaryselectout : out std_logic_vector(4 downto 0); -- export
tx_clkout : out std_logic_vector(0 downto 0); -- export
rx_clkout : out std_logic_vector(0 downto 0); -- export
tx_parallel_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
tx_datak : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
rx_parallel_data : out std_logic_vector(7 downto 0); -- export
rx_datak : out std_logic_vector(0 downto 0); -- export
reconfig_from_xcvr : out std_logic_vector(91 downto 0); -- reconfig_from_xcvr
reconfig_to_xcvr : in std_logic_vector(139 downto 0) := (others => 'X') -- reconfig_to_xcvr
);
end component arria5_phy;
<?xml version="1.0" encoding="UTF-8"?>
<pinplan
variation_name="arria5_phy"
megafunction_name="ALTERA_XCVR_DET_LATENCY"
intended_family="Arria V"
specifies="all_ports">
<global>
<pin name="phy_mgmt_clk" direction="input" scope="external" />
<pin name="phy_mgmt_clk_reset" direction="input" scope="external" />
<pin name="phy_mgmt_address[8..0]" direction="input" scope="external" />
<pin name="phy_mgmt_read" direction="input" scope="external" />
<pin name="phy_mgmt_readdata[31..0]" direction="output" scope="external" />
<pin name="phy_mgmt_waitrequest" direction="output" scope="external" />
<pin name="phy_mgmt_write" direction="input" scope="external" />
<pin name="phy_mgmt_writedata[31..0]" direction="input" scope="external" />
<pin name="tx_ready" direction="output" scope="external" />
<pin name="rx_ready" direction="output" scope="external" />
<pin name="pll_ref_clk" direction="input" scope="external" />
<pin name="tx_serial_data" direction="output" scope="external" />
<pin
name="tx_bitslipboundaryselect[4..0]"
direction="input"
scope="external" />
<pin name="pll_locked" direction="output" scope="external" />
<pin name="rx_serial_data" direction="input" scope="external" />
<pin