Commit 384d4569 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev] Use xwrc_platform_altera from wr-cores

parent bd040521
......@@ -37,12 +37,14 @@ use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_altera_pkg.all;
entity WrpcWrapper is
generic(
g_simulation : integer := 0;
g_pcs_16bit : boolean := FALSE;
g_dpram_initf : string := "default");
port (
......@@ -114,11 +116,10 @@ architecture struct of WrpcWrapper is
-----------------------------------------------------------------------------
-- PLLs
signal pll_clk_62m5 : std_logic;
signal pll_clk_125m : std_logic;
signal pll_clk_dmtd : std_logic;
signal pll_sys_locked : std_logic;
signal pll_dmtd_locked : std_logic;
signal pll_clk_62m5 : std_logic;
signal pll_clk_125m : std_logic;
signal pll_clk_dmtd : std_logic;
signal pll_locked : std_logic;
-- Reset logic
signal rst_62m5_n : std_logic;
......@@ -134,58 +135,105 @@ architecture struct of WrpcWrapper is
signal dac_dpll_data : std_logic_vector(15 downto 0);
-- PHY
signal gxb_locked : std_logic;
signal phy_ready : std_logic;
signal phy_loopen : std_logic;
signal phy_rst : std_logic;
signal phy_tx_clk : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic_vector(0 downto 0);
signal phy_tx_k_bit : std_logic;
signal phy_tx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_rbclk : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_k : std_logic_vector(0 downto 0);
signal phy_rx_k_bit : std_logic;
signal phy_rx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rx_bitslide : std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
-- External WB interface
signal wb_slave_out : t_wishbone_slave_out;
signal wb_slave_in : t_wishbone_slave_in;
component xwrc_platform_altera is
generic (
g_fpga_family : string;
g_with_external_clock_input : boolean;
g_use_default_plls : boolean;
g_pcs_16bit : boolean);
port (
areset_n_i : in std_logic := '1';
clk_20m_i : in std_logic := '0';
clk_125m_i : in std_logic := '0';
clk_62m5_dmtd_i : in std_logic := '0';
clk_62m5_sys_i : in std_logic := '0';
clk_125m_ref_i : in std_logic := '0';
clk_10m_ext_ref_i : in std_logic := '0';
pps_ext_ref_i : in std_logic := '0';
pad_tx_o : out std_logic;
pad_rx_i : in std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
phy_ready_o : out std_logic;
phy_loopen_i : in std_logic;
phy_rst_i : in std_logic;
phy_tx_clk_o : out std_logic;
phy_tx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_o : out std_logic;
phy_tx_enc_err_o : out std_logic;
phy_rx_rbclk_o : out std_logic;
phy_rx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_rx_enc_err_o : out std_logic;
phy_rx_bitslide_o : out std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
ext_ref_rst_i : in std_logic := '0');
end component;
begin -- architecture struct
-----------------------------------------------------------------------------
-- Clock PLLs (with auto-reset)
-- Platform-dependent part (PHY, PLLs, etc)
-----------------------------------------------------------------------------
cmp_pll_sys : arria5_sys_pll_default
cmp_xwrc_platform : xwrc_platform_altera
generic map (
g_fpga_family => "arria5",
g_with_external_clock_input => FALSE,
g_use_default_plls => TRUE,
g_pcs_16bit => g_pcs_16bit)
port map (
refclk => clk_125m_i,
rst => arst_i,
outclk_0 => pll_clk_62m5,
outclk_1 => pll_clk_125m,
locked => pll_sys_locked);
areset_n_i => not arst_i,
clk_20m_i => clk_20m_i,
clk_125m_i => clk_125m_i,
pad_tx_o => wr_sfp_tx_o,
pad_rx_i => wr_sfp_rx_i,
clk_62m5_sys_o => pll_clk_62m5,
clk_125m_ref_o => pll_clk_125m,
clk_62m5_dmtd_o => pll_clk_dmtd,
pll_locked_o => pll_locked,
phy_ready_o => phy_ready,
phy_loopen_i => phy_loopen,
phy_rst_i => phy_rst,
phy_tx_clk_o => phy_tx_clk,
phy_tx_data_i => phy_tx_data,
phy_tx_k_i => phy_tx_k,
phy_tx_disparity_o => phy_tx_disparity,
phy_tx_enc_err_o => phy_tx_enc_err,
phy_rx_rbclk_o => phy_rx_rbclk,
phy_rx_data_o => phy_rx_data,
phy_rx_k_o => phy_rx_k,
phy_rx_enc_err_o => phy_rx_enc_err,
phy_rx_bitslide_o => phy_rx_bitslide);
clk_sys_62m5_o <= pll_clk_62m5;
cmp_pll_dmtd : arria5_dmtd_pll_default
port map (
refclk => clk_20m_i,
rst => arst_i,
outclk_0 => pll_clk_dmtd,
locked => pll_dmtd_locked);
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_sys_locked and
pll_dmtd_locked and
(not arst_i);
--gxb_locked and
rstlogic_arst_n <= pll_locked and (not arst_i);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= pll_clk_62m5;
......@@ -229,33 +277,6 @@ begin -- architecture struct
plldac_ref_sync_n_o <= plldac_sync_n(0);
plldac_dmtd_sync_n_o <= plldac_sync_n(1);
-----------------------------------------------------------------------------
-- Altera PHY
-----------------------------------------------------------------------------
cmp_phy : wr_arria5_phy
port map (
clk_reconf_i => pll_clk_125m,
clk_phy_i => pll_clk_125m,
locked_o => gxb_locked,
loopen_i => phy_loopen,
drop_link_i => '0',
tx_clk_o => phy_tx_clk,
tx_data_i => phy_tx_data,
tx_k_i => phy_tx_k_bit,
tx_disparity_o => phy_tx_disparity,
tx_enc_err_o => phy_tx_enc_err,
rx_rbclk_o => phy_rx_rbclk,
rx_data_o => phy_rx_data,
rx_k_o => phy_rx_k_bit,
rx_enc_err_o => phy_rx_enc_err,
rx_bitslide_o => phy_rx_bitslide,
pad_txp_o => wr_sfp_tx_o,
pad_rxp_i => wr_sfp_rx_i);
phy_tx_k_bit <= phy_tx_k(0);
phy_rx_k(0) <= phy_rx_k_bit;
-----------------------------------------------------------------------------
-- The WR PTP core itself
-----------------------------------------------------------------------------
......@@ -267,6 +288,7 @@ begin -- architecture struct
g_aux_clks => 1,
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_pcs_16bit => g_pcs_16bit,
g_dpram_initf => g_dpram_initf)
port map (
clk_sys_i => pll_clk_62m5,
......@@ -296,8 +318,7 @@ begin -- architecture struct
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_rdy_i => gxb_locked,
phy_loopen_o => open,
phy_rdy_i => phy_ready,
phy_loopen_vec_o => open,
phy_tx_prbs_sel_o => open,
phy_sfp_tx_fault_i => '0',
......
wr-cores @ c2234a14
Subproject commit 811b35de37a6a3e3564d6a33ef3a02a39c3a31d6
Subproject commit c2234a142a739f6e765fd57a31eed1df467ffc01
......@@ -1977,7 +1977,11 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_T
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id WbClockDomain
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id WbClockDomain
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id WbClockDomain
set_global_assignment -name SEARCH_PATH "../../../FpgaModules/SystemSpecific/WhiteRabbit/"
set_global_assignment -name SEARCH_PATH ../../../FpgaModules/SystemSpecific/WhiteRabbit/
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/platform/altera/xwrc_platform_altera.vhd"
set_global_assignment -name QIP_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.qip"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/platform/altera/wr_altera_pkg.vhd"
set_global_assignment -name SOURCE_FILE VfcHd_BaseProject.qsf
......@@ -2032,7 +2036,7 @@ set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/White
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/genram_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gencores_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/WrpcWrapper.vhd"
set_global_assignment -name VHDL_FILE ../../../FpgaModules/SystemSpecific/WhiteRabbit/WrpcWrapper.vhd
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wishbone_pkg.vhd"
......
......@@ -78,19 +78,19 @@ derive_clock_uncertainty
#**************************************************************
# splitting of PHY clocks based on pexarria5 project from GSI
set_clock_groups -asynchronous \
-group { GbitTrxClkRefR_ik \
i_VfcHdSystem|i_WrpcWrapper|cmp_pll_sys|*|general[0]* \
i_VfcHdSystem|i_WrpcWrapper|cmp_pll_sys|*|general[1]* } \
-group { Clk20VCOx_ik \
i_VfcHdSystem|i_WrpcWrapper|cmp_pll_dmtd|* } \
-group { i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*.cdr_refclk* \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*.cmu_pll.* \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|av_tx_pma|* \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|inst_av_pcs|*|tx* } \
-group { i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|clk90bdes \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|clk90b \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|rcvdclkpma }
set_clock_groups -asynchronous \
-group { GbitTrxClkRefR_ik \
i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_sys_clk_pll|*|general[0]* \
i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_sys_clk_pll|*|general[1]* } \
-group { Clk20VCOx_ik \
i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_dmtd_clk_pll|* } \
-group { i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_phy|*.cdr_refclk* \
i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_phy|*.cmu_pll.* \
i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_phy|*|av_tx_pma|* \
i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_phy|*|inst_av_pcs|*|tx* } \
-group { i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_phy|*|clk90bdes \
i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_phy|*|clk90b \
i_VfcHdSystem|i_WrpcWrapper|cmp_xwrc_platform|*cmp_phy|*|rcvdclkpma }
#**************************************************************
# Set False Path
......
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