Skip to content
GitLab
Commit 3dd3145d authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

Merge remote-tracking branch 'origin/ML-btrain-wrenable' into dlamprid-wrbtrain_vfchd

parents aaff76e8 05c3a6c8
Expand all Hide whitespace changes
Inline Side-by-side
.gitmodules
View file @ 3dd3145d
......@@ -4,3 +4,6 @@
[submodule "Hdl/FpgaModules/SystemSpecific/wr-cores"]
path = Hdl/FpgaModules/SystemSpecific/WhiteRabbit/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "Hdl/FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit"]
path = Hdl/FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit
url = ssh://git@gitlab.cern.ch:7999/BTrain-TEAM/PS-BTrain-over-WhiteRabbit.git
Hdl/FpgaModules/ApplicationSpecific/BaseProject/AddrDecoderWbApp.v
View file @ 3dd3145d
......@@ -11,13 +11,9 @@ module AddrDecoderWBApp(
input AckAppReleaseId_i,
output reg StbAppReleaseId_o,
input [31:0] DatCtrlReg_ib32,
input AckCtrlReg_i,
output reg StbCtrlReg_o,
input [31:0] DatStatReg_ib32,
input AckStatReg_i,
output reg StbStatReg_o
input [31:0] DatWrBtrain_ib32,
input AckWrBtrain_i,
output reg StbWrBtrain_o
);
......@@ -27,14 +23,12 @@ reg [1:0] SelectedModule_b2;
localparam c_SelNothing = 2'd0,
c_SelAppRevisionId = 2'd1,
c_SelCtrlReg = 2'd2,
c_SelStatReg = 2'd3;
c_SelWRBtrain = 2'd2;
always @*
casez(Adr_ib21)
21'b0_0000_0000_0000_0000_00??: SelectedModule_b2 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_01??: SelectedModule_b2 = c_SelCtrlReg; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_10??: SelectedModule_b2 = c_SelStatReg; // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0001_????: SelectedModule_b2 = c_SelWRBtrain; // FROM 00_0010 TO 00_001F (WB) == FROM 00_0040 TO 00_007C (VME) <-16 regs (64B)
default: SelectedModule_b2 = c_SelNothing;
endcase
......@@ -42,23 +36,17 @@ always @* begin
Ack_o <= #dly 1'b0;
Dat_ob32 <= #dly 32'h0;
StbAppReleaseId_o <= #dly 1'b0;
StbCtrlReg_o <= #dly 1'b0;
StbStatReg_o <= #dly 1'b0;
StbWrBtrain_o <= #dly 1'b0;
case(SelectedModule_b2)
c_SelAppRevisionId: begin
StbAppReleaseId_o <= #dly Stb_i;
Dat_ob32 <= #dly DatAppReleaseId_ib32;
Ack_o <= #dly AckAppReleaseId_i;
end
c_SelCtrlReg: begin
StbCtrlReg_o <= #dly Stb_i;
Dat_ob32 <= #dly DatCtrlReg_ib32;
Ack_o <= #dly AckCtrlReg_i;
end
c_SelStatReg: begin
StbStatReg_o <= #dly Stb_i;
Dat_ob32 <= #dly DatStatReg_ib32;
Ack_o <= #dly AckStatReg_i;
c_SelWRBtrain: begin
StbWrBtrain_o <= #dly Stb_i;
Dat_ob32 <= #dly DatWrBtrain_ib32;
Ack_o <= #dly AckWrBtrain_i;
end
default: ;
endcase
......
Hdl/FpgaModules/ApplicationSpecific/BaseProject/VfcHdApplication.v
View file @ 3dd3145d
......@@ -6,49 +6,14 @@ module VfcHdApplication
g_ApplicationReleaseMonth_b8 = 8'h07,
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
// FMC connector:
output VfmcEnableN_oen,
/* -----\/----- EXCLUDED -----\/-----
inout [33:0] FmcLaP_iob34,
inout [33:0] FmcLaN_iob34,
inout [23:0] FmcHaP_iob24,
inout [23:0] FmcHaN_iob24,
inout [21:0] FmcHbP_iob22,
inout [21:0] FmcHbN_iob22,
input FmcPrsntM2C_in,
output FmcTck_ok,
output FmcTms_o,
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,
inout FmcScl_iok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
inout FmcClk2Bidir_iok, // Comment: Differential signal
inout FmcClk3Bidir_iok, // Comment: Differential signal
input FmcClkDir_i,
output [ 9:0] FmcDpC2M_ob10, // Comment: Differential signal
input [ 9:0] FmcDpM2C_ib10,
input FmcGbtClk0M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk1M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk0M2CRight_ik, // Comment: Differential signal
input FmcGbtClk1M2CRight_ik, // Comment: Differential signal
-----/\----- EXCLUDED -----/\----- */
output [33:0] FmcLaP_ob34,
output [33:0] FmcLaN_ob34,
// GPIO:
output [3:0] GpIo_ob4,
// Clock sources and control:
input GbitTrxClkRefR_ik, // Comment: Differential reference for the Gbit lines ~125MHz
// SW1:
input [ 1:0] Switch_ib2,
// GPIO:
inout [ 4:1] GpIo_iob4,
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
// Reset:
input Reset_irqp, // Comment: Reset Synchronous with the WbClk_ik
output ResetRequest_oqp, // Comment: Request to issue a reset
......@@ -63,10 +28,26 @@ module VfcHdApplication
output WbSlaveAck_o,
// Interrupt:
output [23:0] InterruptRequest_opb24,
// GPIO direction:
output GpIo1DirOut_o,
output GpIo2DirOut_o,
output GpIo34DirOut_o
// WR Btrain interface:
output [207:0] WrBtrainTxData_o,
output WrBtrainTxValid_o,
input WrBtrainTxDreq_i,
output WrBtrainTxLast_o,
output WrBtrainTxFlush_o,
input WrBtrainRxFirst_i,
input WrBtrainRxLast_i,
input [207:0] WrBtrainRxData_i,
input WrBtrainRxValid_i,
output WrBtrainRxDreq_o,
// WRPC timecode input:
input WrpcPps_i,
input WrpcTmTimeValid_i,
input [39:0] WrpcTmTai_i,
input [27:0] WrpcTmCycles_i,
input WrpcLedLink_i,
input WrpcLedAct_i,
// WRPC system clock:
input WrpcSysClk_ik
);
//****************************
......@@ -77,15 +58,13 @@ wire Clk_k;
wire WbStbAppReleaseId, WbAckAppReleaseId;
wire [31:0] WbDatAppReleaseId_b32;
wire WbStbCtrlReg, WbAckCtrlReg;
wire [31:0] WbDatCtrlReg_b32;
wire WbStbStatReg, WbAckStatReg;
wire [31:0] WbDatStatReg_b32;
wire [31:0] Reg0Value_b32;
wire GpIo1Dir, GpIo2Dir,GpIo34Dir;
wire WbStbWrBtrain, WbAckWrBtrain;
wire [31:0] WbDatWrBtrain_b32;
wire [31:0] WrBtrainBvalue;
wire WrBtrainBvalueValid;
wire WrBtrainBvalueUpdated;
//****************************
//Fixed assignments
//****************************
......@@ -94,26 +73,12 @@ assign InterruptRequest_opb24 = 24'b0;
assign ResetRequest_oqp = 1'b0;
assign GpIo1Dir = 1'b0;
assign GpIo2Dir = 1'b0;
assign GpIo34Dir = 1'b0;
assign GpIo1DirOut_o = GpIo1Dir;
assign GpIo2DirOut_o = GpIo2Dir;
assign GpIo34DirOut_o = GpIo34Dir;
assign GpIo_iob4[4] = GpIo34Dir ? 1'b0 : 1'bz;
assign GpIo_iob4[3] = GpIo34Dir ? 1'b0 : 1'bz;
assign GpIo_iob4[2] = GpIo2Dir ? 1'b0 : 1'bz;
assign GpIo_iob4[1] = GpIo1Dir ? 1'b0 : 1'bz;
assign VfmcEnableN_oen = 1'b0;
//****************************
//Clocking
//****************************
assign Clk_k = GbitTrxClkRefR_ik; //~125MHz
//assign Clk_k = GbitTrxClkRefR_ik; //~125MHz
assign Clk_k = WrpcSysClk_ik;
assign WbClk_ok = Clk_k;
//****************************
......@@ -121,23 +86,19 @@ assign WbClk_ok = Clk_k;
//****************************
AddrDecoderWBApp i_AddrDecoderWbApp(
.Clk_ik (Clk_k),
.Adr_ib21 (WbSlaveAdr_ib25[20:0]),
.Stb_i (WbSlaveStb_i),
.Dat_ob32 (WbSlaveDat_ob32),
.Ack_o (WbSlaveAck_o),
//--
.DatAppReleaseId_ib32 (WbDatAppReleaseId_b32),
.AckAppReleaseId_i (WbAckAppReleaseId),
.StbAppReleaseId_o (WbStbAppReleaseId),
//--
.DatCtrlReg_ib32 (WbDatCtrlReg_b32),
.AckCtrlReg_i (WbAckCtrlReg),
.StbCtrlReg_o (WbStbCtrlReg),
//--
.DatStatReg_ib32 (WbDatStatReg_b32),
.AckStatReg_i (WbAckStatReg),
.StbStatReg_o (WbStbStatReg));
.Clk_ik(Clk_k),
.Adr_ib21(WbSlaveAdr_ib25[20:0]),
.Stb_i(WbSlaveStb_i),
.Dat_ob32(WbSlaveDat_ob32),
.Ack_o(WbSlaveAck_o),
.DatAppReleaseId_ib32(WbDatAppReleaseId_b32),
.AckAppReleaseId_i(WbAckAppReleaseId),
.StbAppReleaseId_o(WbStbAppReleaseId),
.DatWrBtrain_ib32(WbDatWrBtrain_b32),
.AckWrBtrain_i(WbAckWrBtrain),
.StbWrBtrain_o(WbStbWrBtrain));
//****************************
//Release ID
......@@ -157,48 +118,133 @@ Generic4InputRegs i_AppReleaseId(
.Reg3Value_ib32 ({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
//****************************
//Example registers
////WR-Btrain
//****************************
//Control register bank:
Generic4OutputRegs #(
.Reg0Default (32'hBABEB00B),
.Reg0AutoClrMask (32'hFFFFFFFF),
.Reg1Default (32'h00000000),
.Reg1AutoClrMask (32'hFFFFFFFF),
.Reg2Default (32'h00000000),
.Reg2AutoClrMask (32'hFFFFFFFF),
.Reg3Default (32'h00000000),
.Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbCtrlReg),
.We_i (WbSlaveWr_i),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_oab32 (WbDatCtrlReg_b32),
.Ack_oa (WbAckCtrlReg),
//--
.Reg0Value_ob32 (Reg0Value_b32),
.Reg1Value_ob32 (),
.Reg2Value_ob32 (),
.Reg3Value_ob32 ());
//Status registers bank:
Generic4InputRegs i_StatusRegs (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbStatReg),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatStatReg_b32),
.Ack_oa (WbAckStatReg),
//--
.Reg0Value_ib32 (Reg0Value_b32),
.Reg1Value_ib32 (32'hCAFEAC1D),
.Reg2Value_ib32 (32'hACDCDEAD),
.Reg3Value_ib32 (32'hFEEDBEEF));
WrBtrainWrapper #(
.g_st_data_width (208),
.g_wb_addr_width (25),
.g_wb_data_width (32))
i_WrBtrainWrapper (
.clk_i (Clk_k),
.rst_n_i (~Reset_irqp),
.tx_data_o (WrBtrainTxData_o),
.tx_valid_o (WrBtrainTxValid_o),
.tx_dreq_i (WrBtrainTxDreq_i),
.tx_last_o (WrBtrainTxLast_o),
.tx_flush_o (WrBtrainTxFlush_o),
.rx_data_i (WrBtrainRxData_i),
.rx_valid_i (WrBtrainRxValid_i),
.rx_first_i (WrBtrainRxFirst_i),
.rx_dreq_o (WrBtrainRxDreq_o),
.rx_last_i (WrBtrainRxLast_i),
.Bvalue_o (WrBtrainBvalue),
.BvalueValid_o (WrBtrainBvalueValid),
.BvalueUpdated_p1_o (WrBtrainBvalueUpdated),
.wb_adr_i (WbSlaveAdr_ib25),
.wb_dat_i (WbSlaveDat_ib32),
.wb_dat_o (WbDatWrBtrain_b32),
.wb_sel_i (3'b111),
.wb_we_i (WbSlaveWr_i),
.wb_cyc_i (WbSlaveCyc_i),
.wb_stb_i (WbStbWrBtrain),
.wb_ack_o (WbAckWrBtrain),
.wb_err_o (),
.wb_rty_o (),
.wb_stall_o ());
//@@@@@@@@@@@@@@@@@@@
//FMC signal mapping
//@@@@@@@@@@@@@@@@@@@
assign VfmcEnableN_oen = 1'b0;
assign FmcLaP_ob34[0] = ~WrBtrainBvalue[31];
assign FmcLaP_ob34[2] = WrBtrainBvalue[30];
assign FmcLaN_ob34[0] = WrBtrainBvalue[29];
assign FmcLaN_ob34[2] = WrBtrainBvalue[28];
assign FmcLaP_ob34[3] = WrBtrainBvalue[27];
assign FmcLaP_ob34[4] = WrBtrainBvalue[26];
assign FmcLaN_ob34[3] = WrBtrainBvalue[25];
assign FmcLaN_ob34[4] = WrBtrainBvalue[24];
assign FmcLaP_ob34[8] = WrBtrainBvalue[23];
assign FmcLaP_ob34[7] = WrBtrainBvalue[22];
assign FmcLaN_ob34[8] = WrBtrainBvalue[21];
assign FmcLaN_ob34[7] = WrBtrainBvalue[20];
assign FmcLaP_ob34[12] = WrBtrainBvalue[19];
assign FmcLaP_ob34[11] = WrBtrainBvalue[18];
assign FmcLaN_ob34[12] = WrBtrainBvalue[17];
assign FmcLaN_ob34[11] = WrBtrainBvalue[16];
assign FmcLaP_ob34[16] = WrBtrainBvalue[15];
assign FmcLaP_ob34[15] = WrBtrainBvalue[14];
assign FmcLaN_ob34[16] = WrBtrainBvalue[13];
assign FmcLaN_ob34[15] = WrBtrainBvalue[12];
assign FmcLaP_ob34[20] = WrBtrainBvalue[11];
assign FmcLaP_ob34[19] = WrBtrainBvalue[10];
assign FmcLaN_ob34[20] = WrBtrainBvalue[9];
assign FmcLaN_ob34[19] = WrBtrainBvalue[8];
assign FmcLaP_ob34[22] = WrBtrainBvalue[7];
assign FmcLaP_ob34[21] = WrBtrainBvalue[6];
assign FmcLaN_ob34[22] = WrBtrainBvalue[5];
assign FmcLaN_ob34[21] = WrBtrainBvalue[4];
assign FmcLaP_ob34[25] = WrBtrainBvalue[3];
assign FmcLaP_ob34[24] = WrBtrainBvalue[2];
assign FmcLaN_ob34[25] = WrBtrainBvalue[1];
assign FmcLaN_ob34[24] = WrBtrainBvalue[0];
assign FmcLaP_ob34[28] = WrBtrainBvalueUpdated;
assign FmcLaP_ob34[29] = WrBtrainBvalueValid;
assign FmcLaN_ob34[28] = WrpcLedAct_i;
assign FmcLaN_ob34[29] = WrpcLedLink_i;
assign FmcLaP_ob34[31] = WrpcTmTimeValid_i;
assign FmcLaP_ob34[30] = 1'b0; // BT_UP_o
assign FmcLaN_ob34[31] = 1'b0; // BT_DN_o
// unused, driven to ground
assign FmcLaP_ob34[1] = 1'b0;
assign FmcLaN_ob34[1] = 1'b0;
assign FmcLaP_ob34[5] = 1'b0;
assign FmcLaN_ob34[5] = 1'b0;
assign FmcLaP_ob34[6] = 1'b0;
assign FmcLaN_ob34[6] = 1'b0;
assign FmcLaP_ob34[9] = 1'b0;
assign FmcLaN_ob34[9] = 1'b0;
assign FmcLaP_ob34[10] = 1'b0;
assign FmcLaN_ob34[10] = 1'b0;
assign FmcLaP_ob34[13] = 1'b0;
assign FmcLaN_ob34[13] = 1'b0;
assign FmcLaP_ob34[14] = 1'b0;
assign FmcLaN_ob34[14] = 1'b0;
assign FmcLaP_ob34[17] = 1'b0;
assign FmcLaN_ob34[17] = 1'b0;
assign FmcLaP_ob34[18] = 1'b0;
assign FmcLaN_ob34[18] = 1'b0;
assign FmcLaP_ob34[23] = 1'b0;
assign FmcLaN_ob34[23] = 1'b0;
assign FmcLaP_ob34[26] = 1'b0;
assign FmcLaN_ob34[26] = 1'b0;
assign FmcLaP_ob34[27] = 1'b0;
assign FmcLaN_ob34[27] = 1'b0;
assign FmcLaN_ob34[30] = 1'b0;
assign FmcLaP_ob34[32] = 1'b0;
assign FmcLaN_ob34[32] = 1'b0;
assign FmcLaP_ob34[33] = 1'b0;
assign FmcLaN_ob34[33] = 1'b0;
//@@@@@@@@@@@@@@@@@@@
//GPIO signal mapping
//@@@@@@@@@@@@@@@@@@@
assign GpIo_ob4[0] = WrpcPps_i;
assign GpIo_ob4[1] = WrBtrainBvalueValid;
assign GpIo_ob4[2] = 1'b0;
assign GpIo_ob4[3] = 1'b0;
endmodule
PS-BTrain-over-WhiteRabbit @ 3a10c23e
Subproject commit 3a10c23e80700930de0172ea8d196465e05331e6
Hdl/FpgaModules/ApplicationSpecific/WrBtrain/WrBtrainWrapper.vhd 0 → 100644
View file @ 3dd3145d
-------------------------------------------------------------------------------
-- Title : Btrain over White Rabbit
-- Project : Btrain
-------------------------------------------------------------------------------
-- File : WrBtrainWrapper.vhd
-- Author : Maciej Lipinski
-- Company : CERN
-- Created : 2016-07-01
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2016 CERN BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-07-01 1.0 mlipinsk Created
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.WRBtrain_pkg.all;
use work.wishbone_pkg.all;
library work;
entity WrBtrainWrapper is
generic (
g_st_data_width : integer:=c_STREAMER_DATA_WIDTH; -- wr streamer data width
g_wb_addr_width : integer:=25; -- wishbone address width
g_wb_data_width : integer:=32 -- wishbone data width
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
----------------------------------------------------------------
-- Interface with wr_transmission
----------------------------------------------------------------
-- tx
tx_data_o : out std_logic_vector(g_st_data_width-1 downto 0);
tx_valid_o : out std_logic;
tx_dreq_i : in std_logic;
tx_last_o : out std_logic;
tx_flush_o : out std_logic;
-- rx
rx_data_i : in std_logic_vector(g_st_data_width-1 downto 0);
rx_valid_i : in std_logic;
rx_first_i : in std_logic;
rx_dreq_o : out std_logic;
rx_last_i : in std_logic;
----------------------------------------------------------------
-- Interface with Btrain FMC
----------------------------------------------------------------
-- 32-bit value of magnetic field received from Btrain master via WR
Bvalue_o : out std_logic_vector(31 downto 0);
-- HIGH indicates that the value in the register have been received (basically, it is low
-- between reset/powerup and first reception)
BvalueValid_o : out std_logic;
-- single period strobe to which indates update of the Bvalue (first cycle of new value)
BvalueUpdated_p1_o : out std_logic;
----------------------------------------------------------------
-- Wishbone interface
----------------------------------------------------------------
wb_adr_i : in std_logic_vector(g_wb_addr_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(g_wb_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(g_wb_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(g_wb_addr_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic
);
end WrBtrainWrapper;
architecture Behavioral of WrBtrainWrapper is
------------------------------------------------------------------------------
---Wishbone access to WRPC's: RAM, peripherals, vuart, etc..
------------------------------------------------------------------------------
signal wb_slave_out : t_wishbone_slave_out;
signal wb_slave_in : t_wishbone_slave_in;
------------------------------------------------------------------------------
---Btrain data records
------------------------------------------------------------------------------
signal rx_BFramePayloads : t_BFramePayload;
signal rx_Frame_valid_pX : std_logic;
signal tx_FrameHeader : t_FrameHeader;
signal tx_BFramePayloads : t_BFramePayload;
-- ---------------------------------------------------------------------------
-- The function below provides conversion from two's complement to Offset
-- Binary encoding. The encoding is done by adding the offset without overflow.
--
-- The encoding of Bvalue needed by the VFC-HD-based WR-Btrain receiver is
-- an Offset Binary (access-2^31), the value provided by the btrain is signed
-- encoded as two's complement.
-- ---------------------------------------------------------------------------
-- | description |offest binary(access-32 binary)| two's complement |
-- | | (hex) | MSB | MSB | (hex) |
-- | +Full Scale | 0x FFFF FFFF | 1111 1111 | 0111 1111 | 0x 7FFF FFFF |
-- | +Half Scale | 0x C000 0000 | 1100 0000 | | 0x 4000 0000 |
-- | zero | 0x 8000 0000 | 1000 0000 | 0000 0000 | 0x 0000 0000 |
-- | -Half Scale | 0x 4000 0000 | 0100 0000 | | 0x C000 0000 |
-- | -Full Scale | 0x 0000 0000 | 0000 0000 | 1000 0000 | 0x 8000 0000 |
-- ---------------------------------------------------------------------------
function f_encodeOffsetBinary(BvalueIn : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0);
begin
ret := not BvalueIn(31) & BvalueIn(30 downto 0);
return ret;
end;
begin
U_WR_BTRAIN_STUFF: WRBTrain
generic map(
g_data_width => g_st_data_width,
g_slave_granularity => WORD
)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
tx_data_o => tx_data_o,
tx_valid_o => tx_valid_o,
tx_dreq_i => tx_dreq_i,
tx_last_o => tx_last_o,
tx_flush_o => tx_flush_o,
-- rx
rx_data_i => rx_data_i,
rx_valid_i => rx_valid_i,
rx_first_i => rx_first_i,
rx_dreq_o => rx_dreq_o,
rx_last_i => rx_last_i,
rx_FrameHeader_o => open,
rx_BFramePayloads_o => rx_BFramePayloads,
rx_IFramePayloads_o => open,
rx_Frame_valid_pX_o => rx_Frame_valid_pX,
tx_FrameHeader_i => tx_FrameHeader,
tx_BFramePayloads_i => tx_BFramePayloads,