Commit 48d79528 authored by Jan Pospisil's avatar Jan Pospisil
Browse files

updated simulation files for BaseProjectSimulation

parent 74166919
......@@ -77,12 +77,12 @@ compile_verilog $sc work $DUT_PATH/AddrDecoderWbApp.v
compile_verilog $sc work $DUT_PATH/VfcHdApplication.v
# VFC HD hierarchy:
compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_dpram.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_fifo_dc_gray.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_dpram_mod.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_fifo_dc_gray_mod.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/Generic4InputRegs.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/Generic4OutputRegs.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2CMaster.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2CMasterNoBus.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2CMasterWb.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2cMasterGeneric.v
compile_verilog $sc work $VFC_PATH/GeneralPurpose/SpiMasterWB.v
compile_verilog $sc work $VFC_PATH/SystemSpecific/VmeInterface/InterruptManagerWb.v
compile_verilog $sc work $VFC_PATH/SystemSpecific/VmeInterface/VmeInterfaceWb.v
......@@ -104,7 +104,7 @@ compile_verilog $sc work $MODELS_PATH/VfcHd_v2_0.v
compile_verilog $sc work $MODELS_PATH/VmeBusModule.sv
# Test Bench files:
compile_verilog $sc work $TB_PATH/tb_BaseProjectAppAcceses.sv
compile_verilog $sc work $TB_PATH/tb_BaseProject.sv
###############################################
# Top file
......
......@@ -15,7 +15,7 @@ echo ""
echo "Starting Simulation..."
echo ""
vsim -gui -novopt work.tb_BaseProjectAppAcceses
vsim -gui -novopt work.tb_BaseProject
do waveforms.do
run -all
......
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