Commit 5463a848 authored by Manoel Barros Marin's avatar Manoel Barros Marin
Browse files

- Swapped PllRefSda & PllRefScl pins

- Removed application related methods in Class_VfcHd and renamed Class_VfcHd_System
- Added CHILD Class_VfcHd_Base with the applicaction related methods
- Adapted Base_Script to the new classes and renamet to Script_Base
- Cosmetic modifications to several files
parent 763c4d71
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'hC2,
g_ApplicationReleaseDay_b8 = 8'h07,
#(parameter g_ApplicationVersion_b8 = 8'hC4,
g_ApplicationReleaseDay_b8 = 8'h12,
g_ApplicationReleaseMonth_b8 = 8'h07,
g_ApplicationReleaseYear_b8 = 8'h16)
(
......@@ -179,15 +179,15 @@ AddrDecoderWBApp i_AddrDecoderWbApp(
.Stb_i(WbSlaveStb_i),
.Dat_ob32(WbSlaveDat_ob32),
.Ack_o(WbSlaveAck_o),
//--
.DatAppReleaseId_ib32(WbDatAppReleaseId_b32),
.AckAppReleaseId_i(WbAckAppReleaseId),
.StbAppReleaseId_o(WbStbAppReleaseId),
//--
.DatCtrlReg_ib32(WbDatCtrlReg_b32),
.AckCtrlReg_i(WbAckCtrlReg),
.StbCtrlReg_o(WbStbCtrlReg),
//--
.DatStatReg_ib32(WbDatStatReg_b32),
.AckStatReg_i(WbAckStatReg),
.StbStatReg_o(WbStbStatReg));
......@@ -224,8 +224,8 @@ Generic4OutputRegs #(
.Reg3Default (32'h00000000),
.Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs (
.Rst_irq (Reset_irqp),
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbCtrlReg),
.We_i (WbSlaveWr_i),
......@@ -241,10 +241,10 @@ i_ControlRegs (
//Status Registers Bank:
Generic4InputRegs i_StatusRegs (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbStatReg),
.Clk_ik (Clk_k),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatStatReg_b32),
.Ack_oa (WbAckStatReg),
......
......@@ -3,10 +3,10 @@
// Added by M. Barros Marin (10/05/16)
module Generic16InputRegs (
input Clk_ik,
input Rst_irq,
input Cyc_i,
input Stb_i,
input Clk_ik,
input [ 3:0] Adr_ib4,
output reg [31:0] Dat_oab32,
output reg Ack_oa,
......
......@@ -3,10 +3,10 @@
// Mod by M. Barros Marin (02/03/16): Re-written
module Generic4InputRegs (
input Clk_ik,
input Rst_irq,
input Cyc_i,
input Stb_i,
input Clk_ik,
input [ 1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output reg Ack_oa,
......
......@@ -12,8 +12,8 @@ module Generic4OutputRegs
Reg3Default = 32'h00000000,
Reg3AutoClrMask = 32'hFFFFFFFF
)(
input Rst_irq,
input Clk_ik,
input Rst_irq,
input Cyc_i,
input Stb_i,
input We_i,
......
`timescale 1ns/100ps
module I2cMasterWb #( parameter g_CycleLenght = 10'h3ff)
( input Rst_irq,
input Clk_ik,
( input Clk_ik,
input Rst_irq,
input Cyc_i,
input Stb_i,
input We_i,
......
......@@ -15,8 +15,8 @@
`timescale 1ns/100ps
module SpiMasterWb (
input Rst_irq,
input Clk_ik,
input Rst_irq,
input Cyc_i,
input Stb_i,
input We_i,
......
......@@ -282,8 +282,8 @@ InterruptManagerWb #(
//SPI INTERFACES: Vadj pot, ADC
//****************************
SpiMasterWb i_SpiMaster(
.Rst_irq(Reset_rq),
.Clk_ik(Clk_k),
.Rst_irq(Reset_rq),
.Cyc_i(WbCyc),
.Stb_i(WbStbSpiMaster),
.We_i(WbWe),
......@@ -344,8 +344,8 @@ UniqueIdReader #(.g_OneUsClkCycles(125))
I2cMasterWb #(.g_CycleLenght(10'd256))
i_I2cIoExpAndMux
(
.Rst_irq(Reset_rq),
.Clk_ik(Clk_k),
.Rst_irq(Reset_rq),
.Cyc_i(WbCyc),
.Stb_i(WbStbI2cIoExpAndMux),
.We_i(WbWe),
......@@ -364,8 +364,8 @@ I2cMasterWb #(.g_CycleLenght(10'd256))
I2cMasterWb #(.g_CycleLenght(10'd256))
i_I2cWrProm
(
.Rst_irq(Reset_rq),
.Clk_ik(Clk_k),
.Rst_irq(Reset_rq),
.Cyc_i(WbCyc),
.Stb_i(WbStbI2cWrProm),
.We_i(WbWe),
......
......@@ -538,8 +538,8 @@ set_location_assignment PIN_AF25 -to PllDac20Sync_o
set_location_assignment PIN_AC24 -to PllDac25Sync_o
set_location_assignment PIN_AH26 -to PllDacSclk_ok
set_location_assignment PIN_AG26 -to PllDacDin_o
set_location_assignment PIN_AL34 -to PllRefSda_io
set_location_assignment PIN_AK33 -to PllRefScl_ok
set_location_assignment PIN_AL34 -to PllRefScl_ok
set_location_assignment PIN_AK33 -to PllRefSda_io
set_location_assignment PIN_AJ33 -to PllRefInt_i
set_location_assignment PIN_AC21 -to PllSourceMuxOut_ok
#set_location_assignment PIN_AG32 -to PllRefClkOut_ik
......@@ -634,23 +634,6 @@ set_location_assignment PIN_AF7 -to "GbitTrxClkRefR_ik(n)"
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "NORMAL COMPILATION"
set_global_assignment -name SOURCE_FILE VfcHd_BaseProject.qsf
set_global_assignment -name SDC_FILE ../Sdc/VfcHd_BaseProject.sdc
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/SpiMasterWb.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/I2CMasterWb.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/Generic4InputRegs.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/Generic4OutputRegs.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/Ip_OpenCores/generic_fifo_dc_gray_mod.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/Ip_OpenCores/generic_dpram_mod.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/ApplicationSpecific/BaseProject/AddrDecoderWbApp.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/ApplicationSpecific/BaseProject/VfcHdApplication.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/UniqueIdReader.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/AddrDecoderWbSys.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/VfcHdSystem.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/VfcHdTop.v
set_global_assignment -name SIGNALTAP_FILE ../StpII/stp1.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE ../StpII/VfcHd_BaseProject.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id WbClockDomain
......@@ -1984,5 +1967,22 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLE
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id WbClockDomain
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id WbClockDomain
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id WbClockDomain
set_global_assignment -name SOURCE_FILE VfcHd_BaseProject.qsf
set_global_assignment -name SDC_FILE ../Sdc/VfcHd_BaseProject.sdc
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/SpiMasterWb.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/I2cMasterWb.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/Generic4InputRegs.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/Generic4OutputRegs.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/Ip_OpenCores/generic_fifo_dc_gray_mod.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/GeneralPurpose/Ip_OpenCores/generic_dpram_mod.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/ApplicationSpecific/BaseProject/AddrDecoderWbApp.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/ApplicationSpecific/BaseProject/VfcHdApplication.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/UniqueIdReader.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/AddrDecoderWbSys.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/VfcHdSystem.v
set_global_assignment -name VERILOG_FILE ../../../FpgaModules/VfcHdTop.v
set_global_assignment -name SIGNALTAP_FILE ../StpII/stp1.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SLD_FILE db/VfcHd_BaseProject_auto_stripped.stp
\ No newline at end of file
from Class_VfcHd_System import *
class VfcHd_Base(VfcHd_System):
'############################################################################################################'
'#### Note!! This is a CHILD class of the VfcHd_System class. ####'
'#### All attributes and methods related to the Application module of the VFC-HD firmware must be ####'
'#### declared here. ####'
'############################################################################################################'
def __init__(self, Driver="vfc_hd_base", Lun=1, IntLevel = 3, IntVector = 0xA0, RORA="ROACK", Timeout=1000):
VfcHd_System.__init__(self, Driver, Lun, IntLevel, IntVector, RORA, Timeout)
# Application Release ID access
def ReadAppReleaseId(self):
return VfcHd_System.ReadMem(self, "App_ReleaseId")
# Control Register access
def WriteCtrlReg(self, DataLw, Offset=0):
return VfcHd_System.Write(self, "App_CtrlReg", DataLw, Offset)
def WriteMemCtrlReg(self, DataLw, Offset=0, Dma=0, Time=0):
return VfcHd_System.WriteMem(self, "App_CtrlReg",DataLw, Offset, Dma, Time)
def ReadCtrlReg(self, Offset=0):
return VfcHd_System.Read(self, "App_CtrlReg", Offset)
def ReadMemCtrlReg(self, NbLongWords=-1, Offset=0, Dma=0, Time=0):
return VfcHd_System.ReadMem(self, "App_CtrlReg", NbLongWords, Offset, Dma, Time)
def RdModWrCtrlReg(self, DataLw, Mask=0xFFFFFFFF, Offset=0):
return VfcHd_System.RdModWr(self, "App_CtrlReg", DataLw, Mask, Offset)
# Control Register access
def ReadStatReg(self, Offset=0):
return VfcHd_System.Read(self, "App_StatReg", Offset)
def ReadMemStatReg(self, NbLongWords=-1, Offset=0, Dma=0, Time=0):
return VfcHd_System.ReadMem(self, "App_StatReg", NbLongWords, Offset, Dma, Time)
\ No newline at end of file
......@@ -13,7 +13,18 @@ from time import sleep
def HexN(Value, N=8):
return hex(Value).lstrip('0x').rstrip('L').zfill(N)
class VfcHd:
class VfcHd_System:
'############################################################################################################'
'#### ####'
'#### **** PLEASE, DO NOT MODIFY THIS FILE **** ####'
'#### ####'
'#### Note!! This is the PARENT class containing all attributes and methods related to the System module ####'
'#### of the VFC-HD firmware. ####'
'#### All attributes and methods related to the Application module of the VFC-HD firmware must be ####'
'#### declared in a separated CHILD class. ####'
'#### ####'
'############################################################################################################'
def __init__(self, Driver="vfc_hd_base", Lun=1, IntLevel = 3, IntVector = 0xA0, RORA="ROACK", Timeout=1000):
self.Driver = Driver
......@@ -60,24 +71,27 @@ class VfcHd:
return self.VfcHd.read(RegName, Am, Start, To, Dma, Time)[0]
def ReadMem(self, RegName, NbLongWords=-1, Offset=0, Dma=0, Time=0):
Am = -1 # Default
Start = Offset
Am = -1 # Default
Start = Offset
if NbLongWords == -1:
To = -1 # Full memory block
else:
To = Start + NbLongWords
return self.VfcHd.read(RegName, Am, Start, To, Dma, Time)
def RdModWr(self, RegName, DataLw, Mask, Offset): # In the Mask, set to 1 the bits to be modified
Am = -1 # Default
Start = Offset
To = Offset + 1
Dma = 0 # Disabled
Time = 0 # Transaction time report disabled
PrevDataLw = self.VfcHd.read(RegName, Am, Start, To, Dma, Time)[0]
PrevDataLwMasked = PrevDataLw & (~Mask)
DataLwMasked = DataLw & Mask
NewDataLw = PrevDataLwMasked + DataLwMasked
def RdModWr(self, RegName, DataLw, Mask=0xFFFFFFFF, Offset=0): # In the Mask, set to 1 the bits to be modified
Am = -1 # Default
Start = Offset
To = Offset + 1
Dma = 0 # Disabled
Time = 0 # Transaction time report disabled
if Mask == 0xFFFFFFFF:
NewDataLw = DataLw
else:
PrevDataLw = self.VfcHd.read(RegName, Am, Start, To, Dma, Time)[0]
PrevDataLwMasked = PrevDataLw & (~Mask)
DataLwMasked = DataLw & Mask
NewDataLw = PrevDataLwMasked + DataLwMasked
return self.VfcHd.write(RegName, (NewDataLw, ), Am, Start, To, Dma, Time)
# Interrupt functions
......@@ -410,22 +424,22 @@ class VfcHd:
pass
def WrPromWrite(self, Data, Address):
self.I2CPromStartBit()
self.I2CPromSelectSlave('write')
self.I2CPromWriteByte(Address>>8)
self.I2CPromWriteByte(Address%255)
self.I2CPromWriteByte(Data)
self.I2CPromStopBit()
self.I2cPromStartBit()
self.I2cPromSelectSlave('write')
self.I2cPromWriteByte(Address>>8)
self.I2cPromWriteByte(Address%255)
self.I2cPromWriteByte(Data)
self.I2cPromStopBit()
def WrPromRead(self, Address):
self.I2CPromStartBit()
self.I2CPromSelectSlave('write')
self.I2CPromWriteByte(Address>>8)
self.I2CPromWriteByte(Address%255)
self.I2CPromStartBit()
self.I2CPromSelectSlave('read')
Data = self.I2CPromReadByte(1)
self.I2CPromStopBit()
self.I2cPromStartBit()
self.I2cPromSelectSlave('write')
self.I2cPromWriteByte(Address>>8)
self.I2cPromWriteByte(Address%255)
self.I2cPromStartBit()
self.I2cPromSelectSlave('read')
Data = self.I2cPromReadByte(1)
self.I2cPromStopBit()
return Data
# I2C access and IOexp control
......@@ -479,346 +493,54 @@ class VfcHd:
pass
def IoExpWrite(self, IoExpAddr, Command, Data):
self.I2CIoExpStartBit()
self.I2CIoExpSelectSlave('write', IoExpAddr+0x20)
self.I2CIoExpWriteByte(Command)
self.I2CIoExpWriteByte(Data)
self.I2CIoExpStopBit()
self.I2cIoExpStartBit()
self.I2cIoExpSelectSlave('write', IoExpAddr+0x20)
self.I2cIoExpWriteByte(Command)
self.I2cIoExpWriteByte(Data)
self.I2cIoExpStopBit()
def IoExpRead(self, IoExpAddr, Command):
self.I2CIoExpStartBit()
self.I2CIoExpSelectSlave('write', IoExpAddr+0x20)
self.I2CIoExpWriteByte(Command)
self.I2CIoExpStartBit()
self.I2CIoExpSelectSlave('read', IoExpAddr+0x20)
Data = self.I2CIoExpReadByte(1)
self.I2CIoExpStopBit()
self.I2cIoExpStartBit()
self.I2cIoExpSelectSlave('write', IoExpAddr+0x20)
self.I2cIoExpWriteByte(Command)
self.I2cIoExpStartBit()
self.I2cIoExpSelectSlave('read', IoExpAddr+0x20)
Data = self.I2cIoExpReadByte(1)
self.I2cIoExpStopBit()
return Data
def I2cExpDisable(self):
for I2CExpAddr in range(2):
self.I2CIoExpStartBit()
self.I2CIoExpSelectSlave('write', I2CExpAddr+0x70)
self.I2CIoExpWriteByte(0)
self.I2CIoExpStopBit()
self.I2cIoExpStartBit()
self.I2cIoExpSelectSlave('write', I2CExpAddr+0x70)
self.I2cIoExpWriteByte(0)
self.I2cIoExpStopBit()
def I2cExpEnableCh(self, I2CExpAddr, Channel):
self.I2CExpDisable()
self.I2CIoExpStartBit()
self.I2CIoExpSelectSlave('write', I2CExpAddr+0x70)
self.I2CIoExpWriteByte(Channel+4)
self.I2CIoExpStopBit()
self.I2cExpDisable()
self.I2cIoExpStartBit()
self.I2cIoExpSelectSlave('write', I2CExpAddr+0x70)
self.I2cIoExpWriteByte(Channel+4)
self.I2cIoExpStopBit()
def Si57xReadReg(self, RegAddress):
self.I2CExpDisable()
self.I2CExpEnableCh(1, 2)
self.I2CIoExpStartBit()
self.I2CIoExpSelectSlave('write', 0x55)
self.I2CIoExpWriteByte(RegAddress)
self.I2CIoExpStartBit()
self.I2CIoExpSelectSlave('read', 0x55)
Data = self.I2CIoExpReadByte(1)
self.I2cExpDisable()
self.I2cExpEnableCh(1, 2)
self.I2cIoExpStartBit()
self.I2cIoExpSelectSlave('write', 0x55)
self.I2cIoExpWriteByte(RegAddress)
self.I2cIoExpStartBit()
self.I2cIoExpSelectSlave('read', 0x55)
Data = self.I2cIoExpReadByte(1)
self.I2CIoExpStopBit()
return Data
return Data
def Si57xWriteReg(self, Address, Data):
self.I2CExpDisable()
self.I2CExpEnableCh(1, 2)
self.I2CIoExpStartBit()
self.I2CIoExpSelectSlave('write', 0x55)
self.I2CIoExpWriteByte(Address)
self.I2CIoExpWriteByte(Data)
self.I2CIoExpStopBit()
# PLL ref
def I2cPllRefStartBit(self):
self.Write("App_I2cPllContro", 0x01000000)
while (self.Read("App_I2cPllStatus") &0xff000000):
pass
def I2cPllRefSelectSlave(self, ReadWrite):
if (ReadWrite == 'read') :
ReadWriteBit = 1
elif (ReadWrite == 'write'):
ReadWriteBit = 0
else :
print "Only the options 'read' and 'write' are valid"
return "ERROR"
Data = 0x02000000 + (0x70<<1) + ReadWriteBit
self.Write("App_I2cPllContro", Data)
while (self.Read("App_I2cPllStatus") &0xff000000):
pass
if (self.Read("App_I2cPllStatus") &0x100):
print "No module acknoledge the I2C transaction sending the slave address"
return 1
else:
return 0
def I2cPllRefWriteByte(self, Byte):
self.Write("App_I2cPllContro", 0x02000000+Byte) #Sending the byte address
while (self.Read("App_I2cPllStatus") &0xff000000):
pass
if (self.Read("App_I2cPllStatus") &0x100):
print "No module acknoledge the I2C transaction on the byte address"
return 1
else:
return 0
def I2cPllRefReadByte(self, Last=0):
if (Last==1 or Last==0):
self.Write("App_I2cPllContro", 0x03000000+Last)
while (self.Read("App_I2cPllStatus") &0xff000000):
pass
else:
print "only 0 and 1 are valid options"
return "ERROR"
Data = self.Read("App_I2cPllStatus") &0xff
return Data
def I2cPllRefStopBit(self):
self.Write("App_I2cPllContro", 0x04000000)
while (self.Read("App_I2cPllStatus") &0xff000000):
pass
def IoPllRefWrite(self, RegAddress, Data):
self.I2CPllRefStartBit()
self.I2CPllRefSelectSlave('write')
self.I2CPllRefWriteByte(RegAddress)
self.I2CPllRefWriteByte(Data)
self.I2CPllRefStopBit()
def IoPllRefRead(self, RegAddress):
self.I2CPllRefStartBit()
self.I2CPllRefSelectSlave('write')
self.I2CPllRefWriteByte(RegAddress)
self.I2CPllRefStopBit()
self.I2CPllRefSelectSlave('read')
Data = self.I2CPllRefReadByte(1)
self.I2CPllRefStopBit()
return Data
#GPIO control
def EnableGpIoController(self):
self.IoExpWrite(4, 3, 0)
def SetGpIo1Mode(self, Mode):
PresentConfig = self.IoExpRead(4, 3)
if (Mode=="out"):
NewConfiguration = PresentConfig | 0x1
else :
NewConfiguration = PresentConfig & 0xFE
self.IoExpWrite(4, 1, NewConfiguration)
def SetGpIo2Mode(self, Mode):
PresentConfig = self.IoExpRead(4, 3)
if (Mode=="out"):
NewConfiguration = PresentConfig | 0x2
else :
NewConfiguration = PresentConfig & 0xFD
self.IoExpWrite(4, 1, NewConfiguration)
def SetGpIo34Mode(self, Mode):
PresentConfig = self.IoExpRead(4, 3)
if (Mode=="out"):
NewConfiguration = PresentConfig | 0x4
else :
NewConfiguration = PresentConfig & 0xFB
self.IoExpWrite(4, 1, NewConfiguration)
def SetGpIo1Term(self, Mode):
PresentConfig = self.IoExpRead(4, 3)
if (Mode=="on"):
NewConfiguration = PresentConfig | 0x8
else :
NewConfiguration = PresentConfig & 0xF7
self.IoExpWrite(4, 1, NewConfiguration)
def SetGpIo2Term(self, Mode):
PresentConfig = self.IoExpRead(4, 3)
if (Mode=="on"):
NewConfiguration = PresentConfig | 0x10
else :
NewConfiguration = PresentConfig & 0xEF
self.IoExpWrite(4, 1, NewConfiguration)
def SetGpIo3Term(self, Mode):
PresentConfig = self.IoExpRead(4, 3)
if (Mode=="on"):
NewConfiguration = PresentConfig | 0x20
else :
NewConfiguration = PresentConfig & 0xDF
self.IoExpWrite(4, 1, NewConfiguration)
def SetGpIo4Term(self, Mode):
PresentConfig = self.IoExpRead(4, 3)
if (Mode=="on"):
NewConfiguration = PresentConfig | 0x40
else :
NewConfiguration = PresentConfig & 0xBF
self.IoExpWrite(4, 1, NewConfiguration)
def SetGpIo1Value(self, Value):
PresentConfig = self.Read("App_I2cGpIoCntrl")
if (Value):
NewConfiguration = PresentConfig | 0x1
else:
NewConfiguration = PresentConfig & 0xFFFE
self.Write("App_I2cGpIoCntrl", NewConfiguration)
def SetGpIo1LoopBack(self, Value):
PresentConfig = self.Read("App_I2cGpIoCntrl")
if (Value):
NewConfiguration = PresentConfig | 0x2
else:
NewConfiguration = PresentConfig & 0xFFFD
self.Write("App_I2cGpIoCntrl", NewConfiguration)
def SetGpIo1FpgaOutEn(self, Value):
PresentConfig = self.Read("App_I2cGpIoCntrl")
if (Value):
NewConfiguration = PresentConfig | 0x8
else:
NewConfiguration = PresentConfig & 0xFFF7
self.Write("App_I2cGpIoCntrl", NewConfiguration)
def SetGpIo2Value(self, Value):
PresentConfig = self.Read("App_I2cGpIoCntrl")
if (Value):
NewConfiguration = PresentConfig | 0x10
else:
NewConfiguration = PresentConfig & 0xFFEF
self.Write("App_I2cGpIoCntrl", NewConfiguration)
def SetGpIo2LoopBack(self, Value):
PresentConfig = self.Read("App_I2cGpIoCntrl")
if (Value):
NewConfiguration = PresentConfig | 0x20
else:
NewConfiguration = PresentConfig & 0xFFDF
self.Write("App_I2cGpIoCntrl", NewConfiguration)
def SetGpIo2FpgaOutEn(self, Value):
PresentConfig = self.Read("App_I2cGpIoCntrl")
if (Value):
NewConfiguration = PresentConfig | 0x80
else:
NewConfiguration = PresentConfig & 0xFF7F
self.Write("App_I2cGpIoCntrl", NewConfiguration)