Added 2 documents: the DDR3 parameter explanation from ALTERA (answer from a...

Added 2 documents: the DDR3 parameter explanation from ALTERA (answer from a help request) and the schematic of the board

.gitignore

@@ -48,3 +48,16 @@ Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/veril
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.rw64
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
+Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
+Doc/AlteraDocuments/EMIF_Altera.pdf
+Doc/AlteraDocuments/an520.pdf
+Doc/AlteraDocuments/arriav_handbook.pdf
+Doc/AlteraDocuments/ddr3AlteraDesign.pdf
+Doc/Datasheets/8Gb_DDR3L.pdf
+Hw/Assembly data/
+Hw/EDA-03133-V2-0_project.Annotation
+Hw/EDA-03133-V2-0_project.PrjPCB
+Hw/EDA-03133-V2-0_project.PrjPCBStructure
+Hw/Manufacturing/EDA-03133-V2_mfg.cam
+Hw/PCB-Layout/
+Hw/Schematics/