Creating the model for the VFC-HD2

.gitignore

@@ -8,3 +8,5 @@ Hw/EDA-03133-V2-0_sch.pdf
 Hw/Manufacturing/
 Hw/PCB-Layout/
 Hw/Schematics/
+*.bak
+*.pyc

Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v

@@ -2,6 +2,8 @@
 
 module I2CMasterNoBus #(  parameter    g_CycleLenght = 10'h3ff)
 (   input   Clk_ik,
+    input   Rst_irq,
+    
     input   SendStartBit_ip,
     input   SendByte_ip,
     input   GetByte_ip,

Hdl/Simulation/BasicVmeAccesses/modelsim/project/BasicVmeAccesses.cr.mti

+E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module I2CSlave
+
+Top level modules:
+	I2CSlave
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module AddrDecoderWBSys
+
+Top level modules:
+	AddrDecoderWBSys
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module SpiMasterWB
+
+Top level modules:
+	SpiMasterWB
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module I2CMasterNoBus
+
+Top level modules:
+	I2CMasterNoBus
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module generic_fifo_dc_gray
+
+Top level modules:
+	generic_fifo_dc_gray
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module I2CMaster
+
+Top level modules:
+	I2CMaster
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/user_io_checker.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/user_io_checker.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module user_io_checker
+
+Top level modules:
+	user_io_checker
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/VfcHdApplication.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/VfcHdApplication.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module VfcHdApplication
+
+Top level modules:
+	VfcHdApplication
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/VfcHdTop.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/VfcHdTop.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module VfcHdTop
+
+Top level modules:
+	VfcHdTop
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module Generic4OutputRegs
+
+Top level modules:
+	Generic4OutputRegs
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/UniqueIdReader.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/UniqueIdReader.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module UniqueIdReader
+
+Top level modules:
+	UniqueIdReader
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module fmc_test_wrapper
+
+Top level modules:
+	fmc_test_wrapper
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module VfcHdSystem
+
+Top level modules:
+	VfcHdSystem
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module PeriodCounter
+
+Top level modules:
+	PeriodCounter
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module AddrDecoderWBApp
+
+Top level modules:
+	AddrDecoderWBApp
+
+} {} {}} E:/VFC-HD/Hdl/Simulation/Models/VfcHd_v2_0.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/VfcHd_v2_0.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module VfcHd_v2_0
+
+Top level modules:
+	VfcHd_v2_0
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module InterruptManagerWb
+
+Top level modules:
+	InterruptManagerWb
+
+} {} {}} E:/VFC-HD/Hdl/Simulation/Models/MAX5483.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/MAX5483.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module MAX5483
+
+Top level modules:
+	MAX5483
+
+} {} {}} E:/VFC-HD/Hdl/Simulation/BasicVmeAccesses/tb_VfcBasicAccess.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/BasicVmeAccesses/tb_VfcBasicAccess.sv
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module tb_VfcBasicAccess
+
+Top level modules:
+	tb_VfcBasicAccess
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module VmeInterfaceWb
+
+Top level modules:
+	VmeInterfaceWb
+
+} {} {}} E:/VFC-HD/Hdl/Simulation/Models/VmeBusModule.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/Models/VmeBusModule.sv
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module VmeBusModule
+
+Top level modules:
+	VmeBusModule
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module generic_dpram
+
+Top level modules:
+	generic_dpram
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module Generic4InputRegs
+
+Top level modules:
+	Generic4InputRegs
+
+} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module Iir1stOrderLp
+
+Top level modules:
+	Iir1stOrderLp
+
+} {} {}} E:/VFC-HD/Hdl/Simulation/Models/ivt3205c25mhz.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/ivt3205c25mhz.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module ivt3205c25mhz
+
+Top level modules:
+	ivt3205c25mhz
+
+} {} {}} E:/VFC-HD/Hdl/Simulation/Models/sn74vmeh22501.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/sn74vmeh22501.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module sn74vmeh22501
+
+Top level modules:
+	sn74vmeh22501
+
+} {} {}} E:/VFC-HD/Hdl/Simulation/Models/si57x.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/si57x.v
+Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
+-- Compiling module si57x
+
+Top level modules:
+	si57x
+
+} {} {}}

Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/_primary.vhd

+library verilog;
+use verilog.vl_types.all;
+entity AddrDecoderWBApp is
+    port(
+        Clk_ik          : in     vl_logic;
+        Adr_ib21        : in     vl_logic_vector(20 downto 0);
+        Stb_i           : in     vl_logic;
+        Dat_ob32        : out    vl_logic_vector(31 downto 0);
+        Ack_o           : out    vl_logic;
+        DatI2cPllRef_ib32: in     vl_logic_vector(31 downto 0);
+        AckI2cPllRef_i  : in     vl_logic;
+        StbI2cPllRef_o  : out    vl_logic;
+        DatAppReleaseId_ib32: in     vl_logic_vector(31 downto 0);
+        AckAppReleaseId_i: in     vl_logic;
+        StbAppReleaseId_o: out    vl_logic;
+        DatPeriodCounter_ib32: in     vl_logic_vector(31 downto 0);
+        AckPeriodCounter_i: in     vl_logic;
+        StbPeriodCounter_o: out    vl_logic;
+        DatSpiMaster_ib32: in     vl_logic_vector(31 downto 0);
+        AckSpiMaster_i  : in     vl_logic;
+        StbSpiMaster_o  : out    vl_logic;
+        DatFmcTest_ib32 : in     vl_logic_vector(31 downto 0);
+        AckFmcTest_i    : in     vl_logic;
+        StbFmcTest_o    : out    vl_logic;
+        DatMgtTest_ib32 : in     vl_logic_vector(31 downto 0);
+        AckMgtTest_i    : in     vl_logic;
+        StbMgtTest_o    : out    vl_logic;
+        DatGpIoControl_ib32: in     vl_logic_vector(31 downto 0);
+        AckGpIoControl_i: in     vl_logic;
+        StbGpIoControl_o: out    vl_logic
+    );
+end AddrDecoderWBApp;

Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/_primary.vhd

+library verilog;
+use verilog.vl_types.all;
+entity AddrDecoderWBSys is
+    port(
+        Clk_ik          : in     vl_logic;
+        Adr_ib22        : in     vl_logic_vector(21 downto 0);
+        Stb_i           : in     vl_logic;
+        Dat_ob32        : out    vl_logic_vector(31 downto 0);
+        Ack_o           : out    vl_logic;
+        DatIntManager_ib32: in     vl_logic_vector(31 downto 0);
+        AckIntManager_i : in     vl_logic;
+        StbIntManager_o : out    vl_logic;
+        DatSpiMaster_ib32: in     vl_logic_vector(31 downto 0);
+        AckSpiMaster_i  : in     vl_logic;
+        StbSpiMaster_o  : out    vl_logic;
+        DatUniqueIdReader_ib32: in     vl_logic_vector(31 downto 0);
+        AckUniqueIdReader_i: in     vl_logic;
+        StbUniqueIdReader_o: out    vl_logic;
+        DatI2cIoExpAndMux_ib32: in     vl_logic_vector(31 downto 0);
+        AckI2cIoExpAndMux_i: in     vl_logic;
+        StbI2cIoExpAndMux_o: out    vl_logic;
+        DatI2cWrProm_ib32: in     vl_logic_vector(31 downto 0);
+        AckI2cWrProm_i  : in     vl_logic;
+        StbI2cWrProm_o  : out    vl_logic;
+        DatAppSlaveBus_ib32: in     vl_logic_vector(31 downto 0);
+        AckAppSlaveBus_i: in     vl_logic;
+        StbAppSlaveBus_o: out    vl_logic
+    );
+end AddrDecoderWBSys;

Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/_primary.vhd

+library verilog;
+use verilog.vl_types.all;
+entity Generic4InputRegs is
+    port(
+        Rst_irq         : in     vl_logic;
+        Cyc_i           : in     vl_logic;
+        Stb_i           : in     vl_logic;
+        Clk_ik          : in     vl_logic;
+        Adr_ib2         : in     vl_logic_vector(1 downto 0);
+        Dat_oab32       : out    vl_logic_vector(31 downto 0);
+        Ack_oa          : out    vl_logic;
+        Reg0Value_ib32  : in     vl_logic_vector(31 downto 0);
+        Reg1Value_ib32  : in     vl_logic_vector(31 downto 0);
+        Reg2Value_ib32  : in     vl_logic_vector(31 downto 0);
+        Reg3Value_ib32  : in     vl_logic_vector(31 downto 0)
+    );
+end Generic4InputRegs;

Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/_primary.vhd

+library verilog;
+use verilog.vl_types.all;
+entity Generic4OutputRegs is
+    generic(
+        Reg0Default     : integer := 0;
+        Reg1Default     : integer := 0;
+        Reg2Default     : integer := 0;
+        Reg3Default     : integer := 0
+    );
+    port(
+        Rst_irq         : in     vl_logic;
+        Clk_ik          : in     vl_logic;
+        Cyc_i           : in     vl_logic;
+        Stb_i           : in     vl_logic;
+        We_i            : in     vl_logic;
+        Adr_ib2         : in     vl_logic_vector(1 downto 0);
+        Dat_ib32        : in     vl_logic_vector(31 downto 0);
+        Dat_oab32       : out    vl_logic_vector(31 downto 0);
+        Ack_oa          : out    vl_logic;
+        Reg0Value_ob32  : out    vl_logic_vector(31 downto 0);
+        Reg1Value_ob32  : out    vl_logic_vector(31 downto 0);
+        Reg2Value_ob32  : out    vl_logic_vector(31 downto 0);
+        Reg3Value_ob32  : out    vl_logic_vector(31 downto 0)
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of Reg0Default : constant is 1;
+    attribute mti_svvh_generic_type of Reg1Default : constant is 1;
+    attribute mti_svvh_generic_type of Reg2Default : constant is 1;
+    attribute mti_svvh_generic_type of Reg3Default : constant is 1;
+end Generic4OutputRegs;

Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/_primary.vhd

+library verilog;
+use verilog.vl_types.all;
+entity I2CMaster is
+    generic(
+        g_CycleLenght   : vl_logic_vector(0 to 9) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1)
+    );
+    port(
+        Rst_irq         : in     vl_logic;
+        Clk_ik          : in     vl_logic;
+        Cyc_i           : in     vl_logic;
+        Stb_i           : in     vl_logic;
+        We_i            : in     vl_logic;
+        Adr_ib2         : in     vl_logic_vector(1 downto 0);
+        Dat_ib32        : in     vl_logic_vector(31 downto 0);
+        Dat_oab32       : out    vl_logic_vector(31 downto 0);
+        Ack_oa          : out    vl_logic;
+        Scl_ioz         : inout  vl_logic;
+        Sda_ioz         : inout  vl_logic
+    );
+    attribute mti_svvh_generic_type : integer;
+    attribute mti_svvh_generic_type of g_CycleLenght : constant is 1;
+end I2CMaster;