Commit 6243bf89 authored by Andrea Boccardi's avatar Andrea Boccardi
Browse files

Fixed a missing synch on VmeIackIn

parent 71a95233
......@@ -61,3 +61,4 @@ Hw/EDA-03133-V2-0_project.PrjPCBStructure
Hw/Manufacturing/EDA-03133-V2_mfg.cam
Hw/PCB-Layout/
Hw/Schematics/
Hdl/Simulation/BasicVmeAccesses/modelsim/project/BasicVmeAccesses.cr.mti
......@@ -120,7 +120,7 @@ module VfcHdSystem
wire VmeAccess, VmeDtAck_n;
wire [7:1] VmeIrq_nb7;
reg [1:0] VmeSysResetWb_d2 = 2'h0;
reg [1:0] ResetWb_xd2 = 2'h0;
wire WbCyc, WbStb, WbWe, WbAck;
wire [21:0] WbAdr_b22;
wire [31:0] WbDatMiSo_b32, WbDatMoSi_b32;
......@@ -148,7 +148,7 @@ wire [4:0] VmeGa_b5; //need to be accessed from the I2C exp
wire VmeGap_n; //need to be accessed from the I2C exp
wire WbAckI2cWrProm, WbStbI2cWrProm;
wire [31:0] WbDatI2cWrProm_b32;
reg Reset_rq;
//****************************
//Clocking
......@@ -165,9 +165,9 @@ wire Clk_k = GbitTrxClkRefR_ik;
//****************************
always @(posedge Clk_k) VmeSysReset_d2 <= #1 {VmeSysReset_d2[0], ~VmeSysReset_irn};
wire a_Reset_rq = VmeSysReset_d2[1];
always @(posedge WbClk_ik) VmeSysResetWb_d2 <= #1 {VmeSysResetWb_d2[0], ~VmeSysReset_irn};
assign Reset_orqp = VmeSysResetWb_d2[1];
always @(posedge Clk_k) Reset_rq = VmeSysReset_d2[1];
always @(posedge WbClk_ik) ResetWb_xd2 <= #1 {ResetWb_xd2[0], Reset_rq};
assign Reset_orqp = ResetWb_xd2[1];
//****************************
//VME interface & Wishbone Master
......@@ -189,7 +189,7 @@ VmeInterfaceWb #( .g_LowestGaAddressBit(24), .g_ClocksIn2us(250_000) )
i_VmeInterfaceWb
(
.Clk_ik(Clk_k),
.Rst_irq(a_Reset_rq),
.Rst_irq(Reset_rq),
.VmeGa_ib5(VmeGa_b5),
.VmeGap_in(VmeGap_n),
.VmeAs_in(VmeAs_in),
......@@ -261,7 +261,7 @@ InterruptManagerWb #(
.g_ReleaseMonth_b8(g_SystemReleaseMonth_b8),
.g_ReleaseYear_b8(g_SystemReleaseYear_b8))
i_InterruptManagerWb(
.Rst_irq(a_Reset_rq),
.Rst_irq(Reset_rq),
.Clk_ik(Clk_k),
.Cyc_i(WbCyc),
.Stb_i(WbStbIntManager),
......@@ -283,7 +283,7 @@ InterruptManagerWb #(
//SPI INTERFACES: Vadj pot, ADC
//****************************
SpiMasterWB i_SpiMaster(
.Rst_irq(a_Reset_rq),
.Rst_irq(Reset_rq),
.Clk_ik(Clk_k),
.Cyc_i(WbCyc),
.Stb_i(WbStbSpiMaster),
......@@ -312,7 +312,7 @@ assign VAdcSclk_ok = SpiClk_k;
UniqueIdReader #(.g_OneUsClkCycles(125))
i_UniqueIdReader(
.Rst_irq(a_Reset_rq),
.Rst_irq(Reset_rq),
.Clk_ik(Clk_k),
.Cyc_i(WbCyc),
.Stb_i(WbStbUniqueIdReader),
......@@ -345,7 +345,7 @@ UniqueIdReader #(.g_OneUsClkCycles(125))
I2CMaster #(.g_CycleLenght(10'd256))
i_I2cIoExpAndMux
(
.Rst_irq(a_Reset_rq),
.Rst_irq(Reset_rq),
.Clk_ik(Clk_k),
.Cyc_i(WbCyc),
.Stb_i(WbStbI2cIoExpAndMux),
......@@ -365,7 +365,7 @@ I2CMaster #(.g_CycleLenght(10'd256))
I2CMaster #(.g_CycleLenght(10'd256))
i_I2cWrProm
(
.Rst_irq(a_Reset_rq),
.Rst_irq(Reset_rq),
.Clk_ik(Clk_k),
.Cyc_i(WbCyc),
.Stb_i(WbStbI2cWrProm),
......
......@@ -63,7 +63,7 @@ wire [31:0] IntSourceFifoOut_b32;
wire IntSourceFifoFull, IntSourceFifoEmpty;
reg IntSourceFifoRead;
reg [31:0] ConfigReg_bq32 = 32'hFF;
reg [31:0] MaskReg_bq32 = 32'hFF;
reg [31:0] MaskReg_bq32 = 32'hFFFF_FFFF;
assign IntLevel_ob3 = ConfigReg_bq32[22:20];
assign IntVector_ob8 = ConfigReg_bq32[19:12];
......
......@@ -7,7 +7,7 @@ module VmeInterfaceWb
(
input Clk_ik,
input Rst_irq,
input [4:0] VmeGa_ib5,
input VmeGap_in,
input VmeAs_in,
......@@ -52,7 +52,7 @@ localparam s_Idle = 3'd0,
s_IntAck = 3'd5,
s_IAckPass = 3'd6;
reg [7:0] WbTimeoutCounter_c8 = 0;
reg [13:0] WbTimeoutCounter_c14 = 0;
reg [7:0] IntToAckCounter_c8 = 0;
reg [9:0] RoraTimeoutCounter_c10 = 10'h3ff;
reg [31:0] InternalDataReg_b31 = 'h0;
......@@ -69,28 +69,29 @@ wire a_VmeAsSynch = VmeAsShReg_b3[1];
reg [2:0] VmeDs0ShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeDs0ShReg_b3 <= #1 {VmeDs0ShReg_b3[1:0], VmeDs_inb2[0]};
wire NegedgeVmeDs0_a = VmeDs0ShReg_b3[2:1]==2'b10;
wire a_VmeDs0Synch = VmeDs0ShReg_b3[1];
reg [2:0] VmeDs1ShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeDs1ShReg_b3 <= #1 {VmeDs1ShReg_b3[1:0], VmeDs_inb2[1]};
wire NegedgeVmeDs1_a = VmeDs1ShReg_b3[2:1]==2'b10;
wire a_VmeDs1Synch = VmeDs1ShReg_b3[1];
reg [2:0] VmeIackInShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeIackInShReg_b3 <= #1 {VmeIackInShReg_b3[1:0], VmeIackIn_in};
wire a_VmeIackInSynch = VmeIackInShReg_b3[1];
reg [2:0] VmeIackShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeIackShReg_b3 <= #1 {VmeIackShReg_b3[1:0], VmeIack_in};
wire a_VmeIackSynch = VmeIackShReg_b3[1];
//#####################################
// Access recognition signals
//#####################################
wire VmeGaPError_a = ^{VmeGa_ib5, ~VmeGap_in};
wire VmeAmValid_a = (VmeAm_ib6==6'h0B) || (VmeAm_ib6==6'h09);
wire VmeRWAccess_a = ~a_VmeAsSynch && ~a_VmeDs0Synch && ~a_VmeDs1Synch && ~VmeLWord_in && VmeAmValid_a && VmeIack_in && (~VmeGaPError_a) && (VmeA_ib31[31:g_LowestGaAddressBit]=={ {(26-g_LowestGaAddressBit){1'b0}}, ~VmeGa_ib5});
//wire VmeIackCycle_a = ~a_VmeAsSynch && ~(a_VmeDs0Synch&&a_VmeDs1Synch) && ~a_VmeIackInSynch;
wire VmeIackCycle_a = ~a_VmeAsSynch && ~(a_VmeDs0Synch&&a_VmeDs1Synch) && ~VmeIack_in;
wire VmeGaPError_a = ^{VmeGa_ib5, ~VmeGap_in};
wire VmeAmValid_a = (VmeAm_ib6==6'h0B) || (VmeAm_ib6==6'h09);
wire VmeValidBaseAddr_a = (~VmeGaPError_a) && (VmeA_ib31[31:g_LowestGaAddressBit]=={ {(26-g_LowestGaAddressBit){1'b0}}, ~VmeGa_ib5});
wire VmeRWAccess_a = ~a_VmeAsSynch && ~a_VmeDs0Synch && ~a_VmeDs1Synch && ~VmeLWord_in && VmeAmValid_a && VmeIack_in && VmeValidBaseAddr_a;
wire VmeIackCycle_a = ~a_VmeAsSynch && ~(a_VmeDs0Synch&&a_VmeDs1Synch) && ~a_VmeIackSynch;
//#####################################
//State Machine
......@@ -107,24 +108,25 @@ always @* begin
if (VmeWr_in) NextState_ab3 = s_RdWaitWbAnswer;
else NextState_ab3 = s_WrCloseVmeCycle;
end else if (VmeIackCycle_a) begin
if (VmeIrq_onb7[VmeA_ib31[3:1]]==1'b1) NextState_ab3 = s_IAckPass;
else if (a_VmeIackInSynch) begin
if (VmeIrq_onb7[VmeA_ib31[3:1]]==1'b1 ) NextState_ab3 = s_IAckPass;
else if (a_VmeIackInSynch==1'b0) begin
if (~IntModeRora_i) NextState_ab3 = s_IntAck;
else if (&RoraTimeoutCounter_c10) NextState_ab3 = s_IntAck;
else NextState_ab3 = s_IAckPass;
end
end
s_RdWaitWbAnswer:
if (WbAck_i || &WbTimeoutCounter_c8) NextState_ab3 = s_RdCloseVmeCycle;
if (WbAck_i || &WbTimeoutCounter_c14) NextState_ab3 = s_RdCloseVmeCycle;
s_RdCloseVmeCycle:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_Idle;
s_WrCloseVmeCycle:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_WrWaitWbAnswer;
s_WrWaitWbAnswer:
if (WbAck_i || &WbTimeoutCounter_c8) NextState_ab3 = s_Idle;
if (WbAck_i || &WbTimeoutCounter_c14) NextState_ab3 = s_Idle;
s_IntAck:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_Idle;
s_IAckPass:
if (VmeIackIn_in) NextState_ab3 = s_Idle;
s_IAckPass:
if (a_VmeIackInSynch) NextState_ab3 = s_Idle;
default: NextState_ab3 = s_Idle;
endcase
end
......@@ -141,7 +143,6 @@ always @(posedge Clk_ik) begin
VmeIackOut_on <= #1 1'b1;
VmeIrq_onb7 <= #1 7'b1111111;
VmeDataBuffsOutEnable_e <= #1 1'b0;
// VmeDataBuffsOutMode_o <= #1 1'b0;
VmeAccess_o <= #1 1'b0;
VmeDtAck_on <= #1 1'b1;
WbCyc_o <= #1 1'b0;
......@@ -153,13 +154,12 @@ always @(posedge Clk_ik) begin
RoraTimeoutCounter_c10 <= #1 10'h3ff;
InternalDataReg_b31 <= #1 'h0;
VmeAddressInternal_b30 <= #1 'h0;
WbTimeoutCounter_c8 <= #1 'h0;
WbTimeoutCounter_c14 <= #1 'h0;
end else begin
//default assignments applyed in all states if not differently specified
VmeIackOut_on <= #1 1'b1;
VmeIrq_onb7 <= #1 7'b1111111;
VmeDataBuffsOutEnable_e <= #1 1'b0;
// VmeDataBuffsOutMode_o <= #1 1'b0;
VmeAccess_o <= #1 1'b0;
VmeDtAck_on <= #1 1'b1;
if (NegedgeVmeAs_a) VmeAddressInternal_b30 <= #1 VmeA_ib31[31:2];
......@@ -178,7 +178,7 @@ always @(posedge Clk_ik) begin
WbCyc_o <= #1 1'b0;
WbStb_o <= #1 1'b0;
WbWe_o <= #1 1'b0;
WbTimeoutCounter_c8 <= #1 'h0;
WbTimeoutCounter_c14 <= #1 'h0;
//state dependent assignments
case(State_qb3)
s_Idle: begin
......@@ -197,25 +197,23 @@ always @(posedge Clk_ik) begin
end
s_RdWaitWbAnswer: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
// VmeDataBuffsOutMode_o <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
WbCyc_o <= #1 1'b1;
WbStb_o <= #1 1'b1;
WbWe_o <= #1 1'b0;
WbTimeoutCounter_c8 <= #1 WbTimeoutCounter_c8 + 1'b1;
WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (WbAck_i) InternalDataReg_b31 <= #1 WbDat_ib32;
else if (&WbTimeoutCounter_c8) InternalDataReg_b31 <= #1 32'hFFFF_FFFF;
else if (&WbTimeoutCounter_c14) InternalDataReg_b31 <= #1 32'hFFFF_FFFF;
end
s_RdCloseVmeCycle: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
// VmeDataBuffsOutMode_o <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
VmeDtAck_on <= #1 1'b0;
if (NextState_ab3==s_Idle && VmeAm_ib6==6'h0B) VmeAddressInternal_b30 <= #1 VmeAddressInternal_b30 + 1'b1;
end
s_WrCloseVmeCycle: begin
VmeAccess_o <= #1 1'b1;
if (WbTimeoutCounter_c8==8'h1) begin
if (WbTimeoutCounter_c14==14'h1) begin
VmeDtAck_on <= #1 1'b0; //delaying of 1 cycle extra
WbDat_ob32 <= #1 VmeD_iob32;
WbCyc_o <= #1 1'b1;
......@@ -228,7 +226,7 @@ always @(posedge Clk_ik) begin
WbWe_o <= #1 WbWe_o;
WbStb_o <= #1 WbStb_o;
end
if (~WbAck_i) WbTimeoutCounter_c8 <= #1 WbTimeoutCounter_c8 + 1'b1;
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (NextState_ab3==s_WrWaitWbAnswer && VmeAm_ib6==6'h0B) VmeAddressInternal_b30 <= #1 VmeAddressInternal_b30 + 1'b1;
end
s_WrWaitWbAnswer: begin
......@@ -242,14 +240,13 @@ always @(posedge Clk_ik) begin
WbWe_o <= #1 WbWe_o;
WbStb_o <= #1 WbStb_o;
end
if (~WbAck_i) WbTimeoutCounter_c8 <= #1 WbTimeoutCounter_c8 + 1'b1;
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
end
s_IntAck: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
// VmeDataBuffsOutMode_o <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
if (~WbAck_i) WbTimeoutCounter_c8 <= #1 WbTimeoutCounter_c8 + 1'b1;
if (WbTimeoutCounter_c8==8'h7) VmeDtAck_on <= #1 1'b0; //delaying of 2 cycle extra
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (WbTimeoutCounter_c14==14'h7) VmeDtAck_on <= #1 1'b0; //delaying of 2 cycle extra
else VmeDtAck_on <= #1 VmeDtAck_on;
if (NextState_ab3 == s_Idle) begin
if (IntModeRora_i) RoraTimeoutCounter_c10 <= #1 'h0;
......@@ -257,7 +254,7 @@ always @(posedge Clk_ik) begin
end
end
s_IAckPass: begin
VmeIackOut_on <= #1 VmeIackIn_in;
VmeIackOut_on <= #1 a_VmeIackInSynch;
end
default: begin
end
......
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