Merge branch 'WR-dev-btrain-trans' into dlamprid-wrenable

Hdl/FpgaModules/ApplicationSpecific/BaseProject/AddrDecoderWbApp.v

@@ -17,7 +17,11 @@ module AddrDecoderWBApp(
     
     input   [31:0] DatStatReg_ib32,
     input   AckStatReg_i,
-    output  reg StbStatReg_o
+    output  reg StbStatReg_o,
+
+    input   [31:0] DatWrBtrain_ib32,
+    input   AckWrBtrain_i,
+    output  reg StbWrBtrain_o
     
  ); 
 
@@ -28,13 +32,15 @@ reg [1:0] SelectedModule_b2;
 localparam  c_SelNothing       = 2'd0,
             c_SelAppRevisionId = 2'd1,
             c_SelCtrlReg       = 2'd2,
-            c_SelStatReg       = 2'd3; 
+            c_SelStatReg       = 2'd3,
+            c_SelWRBtarin      = 2'd4; 
 
 always @* 
     casez(Adr_ib21)
         21'b0_0000_0000_0000_0000_00??: SelectedModule_b2 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
         21'b0_0000_0000_0000_0000_01??: SelectedModule_b2 = c_SelCtrlReg;       // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)    
         21'b0_0000_0000_0000_0000_10??: SelectedModule_b2 = c_SelStatReg;       // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
+        21'b0_0000_0000_0000_0001_????: SelectedModule_b2 = c_SelWRBtarin;      // FROM 00_0010 TO 00_001F (WB) == FROM 00_0040 TO 00_007C (VME) <-16 regs (64B)
         default:                        SelectedModule_b2 = c_SelNothing;
     endcase 
             
@@ -60,6 +66,11 @@ always @(posedge Clk_ik) begin
             Dat_ob32          <= #dly  DatStatReg_ib32;
             Ack_o             <= #dly  AckStatReg_i;        
         end
+        c_SelWRBtarin: begin
+            StbWrBtrain_o     <= #dly  Stb_i;
+            Dat_ob32          <= #dly  DatWrBtrain_ib32;
+            Ack_o             <= #dly  AckWrBtrain_i;
+        end   
     endcase
 end        
 

Hdl/FpgaModules/ApplicationSpecific/BaseProject/VfcHdApplication.v

@@ -169,12 +169,25 @@ wire WbStbCtrlReg, WbAckCtrlReg;
 wire [31:0] WbDatCtrlReg_b32;
 wire WbStbStatReg, WbAckStatReg;
 wire [31:0] WbDatStatReg_b32;
+//btrain wb i/f
+wire WbStbWrBtrain, WbAckWrBtrain;
+wire [31:0] WbDatWrBtrain_b32;
+
 
 wire [31:0] Reg0Value_b32;
 wire [31:0] Reg1Value_b32;
 wire [31:0] Reg2Value_b32;
 wire [31:0] Reg3Value_b32;
 
+// WR-Btrain stuff -- temporary loopback (lb)
+
+wire [207:0] LoobackData;
+wire         LoobackValid;
+wire         LoobackDreq;
+wire         LoobackLast;
+wire         LoobackFlash;
+
+wire [31:0]  Bvalue;
 //****************************
 //Fixed assignments
 //****************************
@@ -209,7 +222,11 @@ AddrDecoderWBApp i_AddrDecoderWbApp(
     
     .DatStatReg_ib32(WbDatStatReg_b32),
     .AckStatReg_i(WbAckStatReg),
-    .StbStatReg_o(WbStbStatReg));    
+    .StbStatReg_o(WbStbStatReg),
+    
+    .DatWrBtrain_ib32(WbDatWrBtrain_b32),
+    .AckWrBtrain_i(WbAckWrBtrain),
+    .StbWrBtrain_o(WbStbWrBtrain));
 
 //****************************
 //ReleaseID
@@ -272,5 +289,40 @@ Generic4InputRegs i_StatusRegs  (
     .Reg1Value_ib32  (Reg1Value_b32),
     .Reg2Value_ib32  (Reg2Value_b32),
     .Reg3Value_ib32  (Reg3Value_b32)); 
+
+//WR-Btrain
+WrBtrainWrapper #(
+    .g_st_data_width (208),
+    .g_wb_addr_width (25),
+    .g_wb_data_width (32))
+i_WrBtrainWrapper (
+    .clk_i           (Clk_k),
+    .rst_n_i         (~Reset_irqp),
+
+    .tx_data_o       (LoobackData),
+    .tx_valid_o      (LoobackValid),
+    .tx_dreq_i       (LoobackDreq),
+    .tx_last_o       (LoobackLast),
+    .tx_flush_o      (LoobackFlash),
+
+    .rx_data_i       (LoobackData),
+    .rx_valid_i      (LoobackValid),
+    .rx_first_i      (LoobackFlash),
+    .rx_dreq_o       (LoobackDreq),
+    .rx_last_i       (LoobackLast),
+
+    .Bvalue_o        (),
+
+    .wb_adr_i        (WbSlaveAdr_ib25),
+    .wb_dat_i        (WbSlaveDat_ib32),
+    .wb_dat_o        (WbDatWrBtrain_b32),
+    .wb_sel_i        (3'b111),
+    .wb_we_i         (WbSlaveWr_i),
+    .wb_cyc_i        (WbSlaveCyc_i),
+    .wb_stb_i        (WbStbWrBtrain),
+    .wb_ack_o        (WbAckWrBtrain),
+    .wb_err_o        (),
+    .wb_rty_o        (),
+    .wb_stall_o      ());
     
 endmodule

Hdl/FpgaModules/ApplicationSpecific/WrBtrain/WrBtrainWrapper.vhd

+-------------------------------------------------------------------------------
+-- Title      : Btrain over White Rabbit
+-- Project    : Btrain
+-------------------------------------------------------------------------------
+-- File       : WrBtrainWrapper.vhd
+-- Author     : Maciej Lipinski
+-- Company    : CERN
+-- Created    : 2016-07-01
+-- Platform   : FPGA-generics
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+--
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2016 CERN BE-CO-HT
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2016-07-01  1.0     mlipinsk         Created
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.WRBtrain_pkg.all;
+use work.wishbone_pkg.all;
+
+library work;
+
+entity WrBtrainWrapper is
+  generic (
+    g_st_data_width     : integer:=c_STREAMER_DATA_WIDTH; -- wr streamer data width
+    g_wb_addr_width     : integer:=25;                    -- wishbone address width
+    g_wb_data_width     : integer:=32                     -- wishbone data width
+    );
+  port(
+    clk_i               : in std_logic;
+    rst_n_i             : in std_logic;
+
+    ----------------------------------------------------------------
+    -- Interface with wr_transmission
+    ----------------------------------------------------------------
+    -- tx
+    tx_data_o  : out std_logic_vector(g_st_data_width-1 downto 0);
+    tx_valid_o : out std_logic;
+    tx_dreq_i  : in std_logic;
+    tx_last_o  : out std_logic;
+    tx_flush_o : out std_logic;
+    -- rx
+    rx_data_i  : in std_logic_vector(g_st_data_width-1 downto 0);
+    rx_valid_i : in std_logic;
+    rx_first_i : in std_logic;
+    rx_dreq_o  : out std_logic;
+    rx_last_i  : in std_logic;
+    ----------------------------------------------------------------
+    -- Interface with Btrain FMC
+    ----------------------------------------------------------------
+    -- 32-bit value of magnetic field received from Btrain master via WR
+    Bvalue_o           : out std_logic_vector(31 downto 0);
+    -- HIGH indicates that the value in the register have been received (basically, it is low
+    -- between reset/powerup and first reception)
+    BvalueValid_o      : out std_logic;
+    -- single period strobe to which indates update of the Bvalue (first cycle of new value)
+    BvalueUpdated_p1_o : out std_logic;
+    ----------------------------------------------------------------
+    -- Wishbone interface
+    ----------------------------------------------------------------
+    wb_adr_i   : in  std_logic_vector(g_wb_addr_width-1 downto 0)   := (others => '0');
+    wb_dat_i   : in  std_logic_vector(g_wb_data_width-1 downto 0)      := (others => '0');
+    wb_dat_o   : out std_logic_vector(g_wb_data_width-1 downto 0);
+    wb_sel_i   : in  std_logic_vector(g_wb_addr_width/8-1 downto 0) := (others => '0');
+    wb_we_i    : in  std_logic                                               := '0';
+    wb_cyc_i   : in  std_logic                                               := '0';
+    wb_stb_i   : in  std_logic                                               := '0';
+    wb_ack_o   : out std_logic;
+    wb_err_o   : out std_logic;
+    wb_rty_o   : out std_logic;
+    wb_stall_o : out std_logic
+  );
+end WrBtrainWrapper;
+
+architecture Behavioral of WrBtrainWrapper is
+
+  ------------------------------------------------------------------------------
+  ---Wishbone access to WRPC's: RAM, peripherals, vuart, etc..
+  ------------------------------------------------------------------------------
+  signal wb_slave_out : t_wishbone_slave_out;
+  signal wb_slave_in  : t_wishbone_slave_in;
+
+  ------------------------------------------------------------------------------
+  ---Btrain data records
+  ------------------------------------------------------------------------------
+  signal rx_BFramePayloads    : t_BFramePayload;
+  signal rx_Frame_valid_pX    : std_logic;
+  signal tx_FrameHeader       : t_FrameHeader;
+  signal tx_BFramePayloads    : t_BFramePayload;
+  
+
+begin
+
+  U_WR_BTRAIN_STUFF: WRBTrain 
+    generic map(
+      g_data_width               => g_st_data_width,
+      g_slave_granularity        => WORD
+      )
+    port map(
+      clk_i                      => clk_i,
+      rst_n_i                    => rst_n_i,
+
+      tx_data_o                  => tx_data_o,
+      tx_valid_o                 => tx_valid_o,
+      tx_dreq_i                  => tx_dreq_i,
+      tx_last_o                  => tx_last_o,
+      tx_flush_o                 => tx_flush_o,
+      -- rx
+      rx_data_i                  => rx_data_i,
+      rx_valid_i                 => rx_valid_i,
+      rx_first_i                 => rx_first_i,
+      rx_dreq_o                  => rx_dreq_o,
+      rx_last_i                  => rx_last_i,
+
+      rx_FrameHeader_o           => open,
+      rx_BFramePayloads_o        => rx_BFramePayloads,
+      rx_IFramePayloads_o        => open,
+      rx_Frame_valid_pX_o        => rx_Frame_valid_pX,
+
+      tx_FrameHeader_i           => tx_FrameHeader,
+      tx_BFramePayloads_i        => tx_BFramePayloads,
+      tx_IFramePayloads_i        => c_IFramePayload_zero,
+
+      wb_slave_i                 => wb_slave_in,
+      wb_slave_o                 => wb_slave_out
+  );
+  
+  -- process to provide output signals for the BI FMC
+  process(clk_i)
+    begin
+      if rising_edge(clk_i) then 
+        if (rst_n_i='0') then
+          Bvalue_o               <= (others =>'0');
+          BvalueValid_o          <= '0';
+          BvalueUpdated_p1_o     <= '0';
+         else
+           if(rx_Frame_valid_pX='1') then
+              Bvalue_o           <= rx_BFramePayloads.B;
+              BvalueValid_o      <= '1';
+              BvalueUpdated_p1_o <= '1';
+           else
+              BvalueUpdated_p1_o <= '0';
+           end if;
+         end if;
+      end if;
+    end process;
+  ------------------------------------------------------------------------------
+  --- records to vectors
+  ------------------------------------------------------------------------------
+  wb_slave_in.adr(g_wb_addr_width-1 downto 0)   <= wb_adr_i;
+  wb_slave_in.dat(g_wb_data_width-1 downto 0)   <= wb_dat_i;
+  wb_slave_in.sel(g_wb_addr_width/8-1 downto 0) <= wb_sel_i;
+  wb_slave_in.we                                <= wb_we_i;
+  wb_slave_in.cyc                               <= wb_cyc_i;
+  wb_slave_in.stb                               <= wb_stb_i;
+  wb_dat_o                                      <= wb_slave_out.dat(g_wb_data_width-1 downto 0);
+  wb_ack_o                                      <= wb_slave_out.ack;
+  wb_stall_o                                    <= wb_slave_out.stall;
+
+  wb_slave_in.adr(c_wishbone_address_width-1   downto g_wb_addr_width)   <= (others => '0');
+  wb_slave_in.sel(c_wishbone_address_width/8-1 downto g_wb_addr_width/8) <= (others => '0');
+
+ 
+
+  ------------------------------------------------------------------------------
+  --- temporary dummy assigment
+  ------------------------------------------------------------------------------
+  tx_FrameHeader.bit_14to15   <= (others => '0');
+  tx_FrameHeader.d_low_marker <= '0';
+  tx_FrameHeader.f_low_marker <= '0';
+  tx_FrameHeader.zero_cycle   <= '0';
+  tx_FrameHeader.C0           <= '0';
+  tx_FrameHeader.error        <= '0';
+  tx_FrameHeader.sim_eff      <= '0';
+  tx_FrameHeader.frame_type   <= c_ID_BkFrame;
+
+  tx_BFramePayloads.B         <= x"cafebabe";
+  tx_BFramePayloads.Bdot      <= x"deadbeef";
+  tx_BFramePayloads.oldB      <= x"10123456";
+  tx_BFramePayloads.measB     <= x"20123456";
+  tx_BFramePayloads.simB      <= x"30123456";
+  tx_BFramePayloads.synB      <= x"40123456";
+
+end Behavioral;
+

Hdl/Simulation/WrBtrain/modelsim/run_cmp.do

+#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#
+#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#
+# Maciej Lipinski (CERN BE-CO-HT) 01/07/2016 #
+#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#
+#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#
+
+# Defining Quartus II path:
+set QUARTUS_II_PATH C:\altera\15.1\quartus
+
+# Define here the paths used for the different folders:
+set DUT_PATH ../../../FpgaModules/ApplicationSpecific/BaseProject/
+set VFC_PATH ../../../FpgaModules/
+set MODELS_PATH ../../Models/
+set TB_PATH ../
+set WRBTRAIN_PATH ../../../FpgaModules/ApplicationSpecific/WrBtrain/
+# Clearing the transcript window:
+.main clear
+
+echo ""
+echo "########################"
+echo "# Starting Compilation #"
+echo "########################"
+
+###############################################
+# Verilog Compile Process
+###############################################
+
+proc compile_verilog {sc lib name} {
+	file stat $name result
+	if {$sc < $result(mtime)} {
+	    set ok [vlog -work $lib $name]
+	}
+}
+
+proc compile_vhdl {sc lib name} {
+	file stat $name result
+	if {$sc < $result(mtime)} {
+	    set ok [vcom -2008 -work $lib $name]
+	}
+}
+###############################################
+# Defining Last Compilation
+###############################################
+
+echo ""
+echo "-> Enabling Smart or Full Compilation..."
+echo ""
+
+# Checking whether a previous smart compilation exists:
+if {![info exists sc]} {
+    set sc 0
+    set no_sc 1;
+} 
+
+if "$no_sc == 1" {
+	echo "Smart compilation not possible or not enabled. Running full compilation..."
+	# Deleting pre-existing libraries
+	if {[file exists work]} {vdel -all -lib work}	
+	# Creating and mapping working directory:
+	vlib work
+    vmap work work
+	set no_sc 0;
+} else {
+	echo "Smart compilation enabled. Only out of date files will be compiled..."
+	puts [clock format $sc -format {Previous compilation time: %A, %d of %B, %Y - %H:%M:%S}]
+}
+
+###############################################
+# Compiling simulation files
+###############################################
+
+echo ""
+echo "-> Starting Compilation..."
+echo ""
+    
+# Device Under Test files:
+compile_verilog $sc work $DUT_PATH/AddrDecoderWbApp.v
+compile_verilog $sc work $DUT_PATH/VfcHdApplication.v
+
+# VFC HD hierarchy:
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_dpram.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_fifo_dc_gray.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/Generic4InputRegs.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/Generic4OutputRegs.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2CMaster.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2CMasterNoBus.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/SpiMasterWB.v
+compile_verilog $sc work $VFC_PATH/SystemSpecific/VmeInterface/InterruptManagerWb.v
+compile_verilog $sc work $VFC_PATH/SystemSpecific/VmeInterface/VmeInterfaceWb.v
+compile_verilog $sc work $VFC_PATH/SystemSpecific/AddrDecoderWbSys.v
+compile_verilog $sc work $VFC_PATH/SystemSpecific/I2cMuxAndExpMaster.v
+compile_verilog $sc work $VFC_PATH/SystemSpecific/UniqueIdReader.v
+compile_verilog $sc work $VFC_PATH/SystemSpecific/VfcHdSystem.v
+compile_verilog $sc work $VFC_PATH/VfcHdTop.v 
+
+# VFC HD models files:
+compile_verilog $sc work $MODELS_PATH/I2CSlave.v
+compile_verilog $sc work $MODELS_PATH/ivt3205c25mhz.v
+compile_verilog $sc work $MODELS_PATH/MAX5483.v
+compile_verilog $sc work $MODELS_PATH/pca9534.v
+compile_verilog $sc work $MODELS_PATH/pca9544a.v
+compile_verilog $sc work $MODELS_PATH/si57x.v
+compile_verilog $sc work $MODELS_PATH/sn74vmeh22501.v
+compile_verilog $sc work $MODELS_PATH/VfcHd_v2_0.v
+compile_verilog $sc work $MODELS_PATH/VmeBusModule.sv
+
+# WR-Btrain stuff:
+
+# stuff needed from general cores and wr-cores
+compile_vhdl    $sc work $WRBTRAIN_PATH/general-cores/modules/genrams/genram_pkg.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/general-cores/modules/wishbone/wishbone_pkg.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/wr-cores/modules/fabric/wr_fabric_pkg.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+
+# stuff needed from Btrain cores
+
+compile_vhdl    $sc work $WRBTRAIN_PATH/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/WRBtrain_wbgen2_pkg.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/WRBTrain_pkg.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/rxCtrlBtrain.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/SynchroGen.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/txCtrlBtrain.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/WRBtrain_wb.vhd
+compile_vhdl    $sc work $WRBTRAIN_PATH/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/WRBTrain.vhd
+
+# dedicated VFC-HD wrapper
+compile_vhdl    $sc work $WRBTRAIN_PATH/WrBtrainWrapper.vhd
+
+# Test Bench files:
+compile_verilog $sc work $TB_PATH/tb_WrBtrainAccess.sv
+
+###############################################
+# Top file
+###############################################
+
+echo ""
+echo "-> Setting Top File..."
+echo ""
+
+set top_level work.tb_BaseProjecAppAcceses
+
+###############################################
+# Acquiring Compilation Time
+###############################################
+
+echo ""
+set sc [clock seconds];
+puts [clock format $sc -format {Setting last compilation time to: %A, %d of %B, %Y - %H:%M:%S}]
+
+echo ""
+echo "-> Compilation Done..."
+echo ""
+echo ""
\ No newline at end of file

Hdl/Simulation/WrBtrain/modelsim/run_sim.do

+#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+# Manoel Barros Marin (CERN BE-BI-QP) 02/03/2016
+#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+#@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+
+# Cleaning the transcript window:
+.main clear
+
+###############################################
+# Running simulation
+###############################################
+
+echo ""
+echo "Starting Simulation..."
+echo ""
+
+vsim -gui -novopt work.tb_WrBtrainAccess
+do wave.do
+run -all
+
+echo ""
+echo ""
\ No newline at end of file

Hdl/Simulation/WrBtrain/tb_WrBtrainAccess.sv

+//============================================================================================\\
+//################################   Test Bench Information   ################################\\
+//============================================================================================\\
+//                                                                                         
+// Company: CERN (BE-BI) 
+//                                                        
+// File Name: <tb_ModuleName>.v  
+// 
+// File versions history:
+//
+//       DATE          VERSION      AUTHOR             DESCRIPTION
+//     - <date>        <version>    <author>           <description>               
+//
+// Language: Verilog 2005                                                              
+//
+// Module Under Test: <Module Name (ModuleName.v)>
+//                                                                                       
+// Targeted device:
+//
+//     - Vendor: <FPGA manufacturer if vendor specific code>
+//     - Model:  <FPGA Model if model specific>
+//
+// Description:
+//
+//     <Brief description of the test bench.>                                                                                                       
+//                                                                                                   
+//============================================================================================\\
+//############################################################################################\\
+//============================================================================================\\
+
+`timescale 1ns/100ps
+
+module tb_WrBtrainAccess;
+//=======================================  Declarations  =====================================\\    
+
+//==== Local parameters ====\\ 
+
+localparam c_VmeAccessVerbose = 1'b1; 
+
+// Ga Control:
+localparam c_UseGa   = 1'b0;
+localparam c_NoGa_b5 = 5'h6;
+
+// Base Address:
+localparam c_VfcSlot4BaseAddress = 32'h0600_0000;  // Comment: The address is for now fixed
+
+// System Memory Addresses:
+localparam c_SysIntSource      = 32'h0000_0000,  //Comment: Interrupt Source 
+           c_SysIntConfig      = 32'h0000_0004,  //Comment: Interrupt Configuration 
+           c_SysIntMask        = 32'h0000_0008,  //Comment: Interrupt source mask 
+           c_SysReleaseId      = 32'h0000_000C,  //Comment: Release ID of the system block 
+           c_SysIoExpStatus    = 32'h0000_0010,  //Comment: I2C mux and IO expander controller status  
+           c_SysIoExpCommand   = 32'h0000_0014,  //Comment: I2C mux and IO expander controller command reg            
+           c_SysUidStatus      = 32'h0000_0020,  //Comment: Unique Id and Temperature controller Status            
+           c_SysUidCommand     = 32'h0000_0024,  //Comment: Unique Id and Temperature controller Command reg 
+           c_SysWrPrmStatus    = 32'h0000_0030,  //Comment: WR PROM I2C controller status  
+           c_SysWrPrmCommand   = 32'h0000_0034,  //Comment: WR PROM I2C controller command reg 
+           c_SysSpiStatus      = 32'h0000_0040,  //Comment: Spi Master Status  
+           c_SysSpiConfig1     = 32'h0000_0044,  //Comment: Spi Master Config 1  
+           c_SysSpiConfig2     = 32'h0000_0048,  //Comment: Spi Master Config 2 
+           c_SysSpiShiftOut    = 32'h0000_004C,  //Comment: Spi Master data to shift out 
+           c_SysSpiShiftIn     = 32'h0000_0050;  //Comment: Spi Master data shifted in 
+
+// Application Memory Addresses:
+localparam c_AppAddrOffset     = 32'h0080_0000;                    // Comment: Address offset of the Aplication  
+//--
+localparam c_AppReleaseId      = c_AppAddrOffset + 32'h0000_0000,  //Comment: Interrupt Source 
+           c_AppCtrlReg        = c_AppAddrOffset + 32'h0000_0010,  //Comment: Interrupt Configuration 
+           c_AppStatReg        = c_AppAddrOffset + 32'h0000_0020,  //Comment: Interrupt source mask
+           c_AppWrBtrain       = c_AppAddrOffset + 32'h0000_0040;  //Comment: WR Btrain stuff
+//==== Wires & Regs ====\\ 
+wire As_n;
+wire [5:0] AM_b6;
+wire [31:1] A_b31;
+wire LWord;
+wire [1:0] Ds_nb2;
+wire Wr_n;
+wire [31:0] D_b32;
+wire DtAck_n;
+wire [7:1] Irq_nb7;
+wire Iack_n;
+wire [20:1] IackIn_nb;
+wire [20:1] IackOut_nb;
+wire SysResetN_irn;
+wire SysClk_k;
+wire [ 4:0] Ga_nmb5 [20:1];
+wire [20:1] Gap_nbm;
+logic PushButton = 0;
+logic [7:0] LastVmeAccessExitCode_b8;
+logic [31:0] LastVmeReadData_b32;
+
+//=====================================  Status & Control  ====================================\\    
+
+task Read (input [31:0] Address_b32);