Commit 6c46595e authored by Manoel Barros Marin's avatar Manoel Barros Marin
Browse files

Merge branch 'master' of https://gitlab.cern.ch/bi/VFC-HD

parents c2a26b19 5f71c57d
*.bak
*.pyc
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
Doc/AlteraDocuments/EMIF_Altera.pdf
Doc/AlteraDocuments/an520.pdf
Doc/AlteraDocuments/arriav_handbook.pdf
Doc/AlteraDocuments/ddr3AlteraDesign.pdf
Doc/Datasheets/8Gb_DDR3L.pdf
Hw/Assembly data/
Hw/EDA-03133-V2-0_project.Annotation
Hw/EDA-03133-V2-0_project.PrjPCB
Hw/EDA-03133-V2-0_project.PrjPCBStructure
Hw/Manufacturing/EDA-03133-V2_mfg.cam
Hw/PCB-Layout/
Hw/Schematics/
E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CSlave
Top level modules:
I2CSlave
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module AddrDecoderWBSys
Top level modules:
AddrDecoderWBSys
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module SpiMasterWB
Top level modules:
SpiMasterWB
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CMasterNoBus
Top level modules:
I2CMasterNoBus
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module generic_fifo_dc_gray
Top level modules:
generic_fifo_dc_gray
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CMaster
Top level modules:
I2CMaster
} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/user_io_checker.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/user_io_checker.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module user_io_checker
Top level modules:
user_io_checker
} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/VfcHdApplication.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/VfcHdApplication.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VfcHdApplication
Top level modules:
VfcHdApplication
} {} {}} E:/VFC-HD/Hdl/FpgaModules/VfcHdTop.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/VfcHdTop.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VfcHdTop
Top level modules:
VfcHdTop
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module Generic4OutputRegs
Top level modules:
Generic4OutputRegs
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/UniqueIdReader.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/UniqueIdReader.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module UniqueIdReader
Top level modules:
UniqueIdReader
} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module fmc_test_wrapper
Top level modules:
fmc_test_wrapper
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/VfcHd_v2_0.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/VfcHd_v2_0.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VfcHd_v2_0
Top level modules:
VfcHd_v2_0
} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module AddrDecoderWBApp
Top level modules:
AddrDecoderWBApp
} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module PeriodCounter
Top level modules:
PeriodCounter
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VfcHdSystem
Top level modules:
VfcHdSystem
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/MAX5483.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/MAX5483.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module MAX5483
Top level modules:
MAX5483
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module InterruptManagerWb
Top level modules:
InterruptManagerWb
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/VmeBusModule.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/Models/VmeBusModule.sv
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VmeBusModule
Top level modules:
VmeBusModule
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VmeInterfaceWb
Top level modules:
VmeInterfaceWb
} {} {}} E:/VFC-HD/Hdl/Simulation/BasicVmeAccesses/tb_VfcBasicAccess.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/BasicVmeAccesses/tb_VfcBasicAccess.sv
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module tb_VfcBasicAccess
Top level modules:
tb_VfcBasicAccess
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module Generic4InputRegs
Top level modules:
Generic4InputRegs
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module generic_dpram
Top level modules:
generic_dpram
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/sn74vmeh22501.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/sn74vmeh22501.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module sn74vmeh22501
Top level modules:
sn74vmeh22501
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/ivt3205c25mhz.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/ivt3205c25mhz.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module ivt3205c25mhz
Top level modules:
ivt3205c25mhz
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module Iir1stOrderLp
Top level modules:
Iir1stOrderLp
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/si57x.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/si57x.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module si57x
Top level modules:
si57x
} {} {}}
m255
K3
13
cModel Technology
dE:\LhcBpm\simulation
vAddrDecoderWBApp
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8E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v
FE:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v
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Z1 OL;L;10.1c;51
Z2 o-work work -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF
n@addr@decoder@w@b@app
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!s108 1453133487.750000
!s107 E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v|
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v|
vAddrDecoderWBSys
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8E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
FE:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
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n@addr@decoder@w@b@sys
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!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v|
vfmc_test_wrapper
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8E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v
FE:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v
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R1
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!s100 lWdci1g0=4IM4a:eXA[1D2
!s108 1453133487.891000
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!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v|
vGeneric4InputRegs
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8E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
FE:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
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R1
R2
n@generic4@input@regs
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!s108 1453133487.376000
!s107 E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v|
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v|
vGeneric4OutputRegs
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8E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v
FE:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v
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R1
R2
n@generic4@output@regs
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!s108 1453133487.407000
!s107 E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v|
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v|
vgeneric_dpram
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R4
8E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v
FE:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v
L0 107
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R2
!s100 >1IE@EnR<<CaAb<bQiG2^1
!s108 1453133487.626000
!s107 E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v|
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vgeneric_fifo_dc_gray
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8E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v
FE:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v
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R2
!s100 =MkX0o7S<HaA^_Lc;5DW83
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!s107 E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v|
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v|
vI2CMaster
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8E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v
FE:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v
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R2
n@i2@c@master
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!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v|
vI2CMasterNoBus
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n@i2@c@master@no@bus
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vI2CSlave
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FE:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
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vIir1stOrderLp
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vivt3205c25mhz
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