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Commit 71911ca6 authored by Manoel Barros Marin's avatar Manoel Barros Marin
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- Added VFC Base Project simulation 

- Fixed issue with Ourput reg in Base project
parent c3d05c98
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Hdl/FpgaModules/ApplicationSpecific/BaseProject/VfcHdApplication.v
View file @ 71911ca6
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'hb1,
g_ApplicationReleaseDay_b8 = 8'h01,
#(parameter g_ApplicationVersion_b8 = 8'hb1,
g_ApplicationReleaseDay_b8 = 8'h01,
g_ApplicationReleaseMonth_b8 = 8'h03,
g_ApplicationReleaseYear_b8 = 8'h16)
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
......@@ -219,13 +219,13 @@ Generic4InputRegs i_RevisionAndMisc(
//Control Register Bank:
Generic4OutputRegs #(
.Reg0Default (32'hBABEB00B),
.Reg0AutoClrMask (32'hF),
.Reg0AutoClrMask (32'hFFFFFFFF),
.Reg1Default (32'hCAFEAC1D),
.Reg1AutoClrMask (32'hF),
.Reg1AutoClrMask (32'hFFFFFFFF),
.Reg2Default (32'hACDCDEAD),
.Reg2AutoClrMask (32'hF),
.Reg2AutoClrMask (32'hFFFFFFFF),
.Reg3Default (32'hFEEDBEEF),
.Reg3AutoClrMask (32'hF))
.Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs (
.Rst_irq (Reset_irqp),
.Clk_ik (Clk_k),
......@@ -243,11 +243,11 @@ i_ControlRegs (
.Reg3Value_ob32 (Reg3Value_b32));
//Status Registers Bank:
Generic4InputRegs i_Status (
Generic4InputRegs i_StatusRegs (
.Rst_irq (Reset_irqp),
.Cyc_i (Clk_k),
.Stb_i (WbSlaveCyc_i),
.Clk_ik (WbStbStatReg),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbStatReg),
.Clk_ik (Clk_k),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatStatReg_b32),
.Ack_oa (WbAckStatReg),
......
Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
View file @ 71911ca6
`timescale 1ns/100ps
module Generic4InputRegs (
input Rst_irq,
input Cyc_i,
input Stb_i,
input Clk_ik,
input [1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output reg Ack_oa,
// Mod by M. Barros Marin (02/03/16): Re-written
input [31:0] Reg0Value_ib32,
input [31:0] Reg1Value_ib32,
input [31:0] Reg2Value_ib32,
input [31:0] Reg3Value_ib32);
module Generic4InputRegs (
input Rst_irq,
input Cyc_i,
input Stb_i,
input Clk_ik,
input [ 1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output reg Ack_oa,
input [31:0] Reg0Value_ib32,
input [31:0] Reg1Value_ib32,
input [31:0] Reg2Value_ib32,
input [31:0] Reg3Value_ib32
);
always @(posedge Clk_ik) Ack_oa <= #1 Stb_i&&Cyc_i;
always @(posedge Clk_ik)
if (~Ack_oa) begin
case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ib32;
2'b01: Dat_oab32 = Reg1Value_ib32;
2'b10: Dat_oab32 = Reg2Value_ib32;
2'b11: Dat_oab32 = Reg3Value_ib32;
default: Dat_oab32 = Reg0Value_ib32;
endcase
if (Rst_irq) begin
Dat_oab32 <= #1 32'h0;
Ack_oa <= #1 1'b0;
end else begin
if (~Ack_oa) begin
case (Adr_ib2)
2'b00: Dat_oab32 <= #1 Reg0Value_ib32;
2'b01: Dat_oab32 <= #1 Reg1Value_ib32;
2'b10: Dat_oab32 <= #1 Reg2Value_ib32;
2'b11: Dat_oab32 <= #1 Reg3Value_ib32;
default: Dat_oab32 <= #1 Reg0Value_ib32;
endcase
end
Ack_oa <= #1 Stb_i && Cyc_i;
end
endmodule
\ No newline at end of file
Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v
View file @ 71911ca6
`timescale 1ns/100ps
// Mod by M. Barros Marin (04/02/16): Added auto-clear
// Mod by M. Barros Marin (02/03/16): Re-written
module Generic4OutputRegs
#( parameter
Reg0Default = 32'h0,
Reg0AutoClrMask = 32'hF,
Reg1Default = 32'h0,
Reg1AutoClrMask = 32'hF,
Reg2Default = 32'h0,
Reg2AutoClrMask = 32'hF,
Reg3Default = 32'h0,
Reg3AutoClrMask = 32'hF
#( parameter Reg0Default = 32'h0,
Reg0AutoClrMask = 32'hFFFFFFFF,
Reg1Default = 32'h0,
Reg1AutoClrMask = 32'hFFFFFFFF,
Reg2Default = 32'h0,
Reg2AutoClrMask = 32'hFFFFFFFF,
Reg3Default = 32'h0,
Reg3AutoClrMask = 32'hFFFFFFFF
)(
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output Ack_oa,
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [ 1:0] Adr_ib2,
input [31:0] Dat_ib32,
output [31:0] Dat_oab32,
output reg Ack_oa,
output [31:0] Reg0Value_ob32,
output [31:0] Reg1Value_ob32,
output [31:0] Reg2Value_ob32,
output [31:0] Reg3Value_ob32
);
reg [31:0] Reg_q4b32 [3:0];
output reg [31:0] Reg0Value_ob32,
output reg [31:0] Reg1Value_ob32,
output reg [31:0] Reg2Value_ob32,
output reg [31:0] Reg3Value_ob32);
initial begin
Reg0Value_ob32 = Reg0Default;
Reg1Value_ob32 = Reg1Default;
Reg2Value_ob32 = Reg2Default;
Reg3Value_ob32 = Reg3Default;
end
always @(posedge Clk_ik)
if (Rst_irq) Reg0Value_ob32 <= #1 Reg0Default;
else Reg0Value_ob32 <= #1 (Cyc_i && We_i && Stb_i && Adr_ib2==2'b00) ? Dat_ib32 : (Reg0Value_ob32 & Reg0AutoClrMask);
always @(posedge Clk_ik)
if (Rst_irq) Reg1Value_ob32 <= #1 Reg1Default;
else Reg1Value_ob32 <= #1 (Cyc_i && We_i && Stb_i && Adr_ib2==2'b01) ? Dat_ib32 : (Reg1Value_ob32 & Reg1AutoClrMask);
always @(posedge Clk_ik)
if (Rst_irq) Reg2Value_ob32 <= #1 Reg2Default;
else Reg2Value_ob32 <= #1 (Cyc_i && We_i && Stb_i && Adr_ib2==2'b10) ? Dat_ib32 : (Reg2Value_ob32 & Reg2AutoClrMask);
always @(posedge Clk_ik)
if (Rst_irq) Reg3Value_ob32 <= #1 Reg3Default;
else Reg3Value_ob32 <= #1 (Cyc_i && We_i && Stb_i && Adr_ib2==2'b11) ? Dat_ib32 : (Reg3Value_ob32 & Reg3AutoClrMask);
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ob32;
2'b01: Dat_oab32 = Reg1Value_ob32;
2'b10: Dat_oab32 = Reg2Value_ob32;
2'b11: Dat_oab32 = Reg3Value_ob32;
default: Dat_oab32 = Reg0Value_ob32;
endcase
endmodule
if (Rst_irq) begin
Reg_q4b32[0] <= #1 Reg0Default;
Reg_q4b32[1] <= #1 Reg1Default;
Reg_q4b32[2] <= #1 Reg2Default;
Reg_q4b32[3] <= #1 Reg3Default;
Ack_oa <= #1 1'b0;
end else begin
Reg_q4b32[0] <= #1 Reg_q4b32[0] & Reg0AutoClrMask;
Reg_q4b32[1] <= #1 Reg_q4b32[1] & Reg1AutoClrMask;
Reg_q4b32[2] <= #1 Reg_q4b32[2] & Reg2AutoClrMask;
Reg_q4b32[3] <= #1 Reg_q4b32[3] & Reg3AutoClrMask;
if (Cyc_i && We_i && Stb_i) Reg_q4b32[Adr_ib2] <= #1 Dat_ib32;
Ack_oa <= #1 Stb_i&&Cyc_i;
end
assign Reg0Value_ob32 = Reg_q4b32[0];
assign Reg1Value_ob32 = Reg_q4b32[1];
assign Reg2Value_ob32 = Reg_q4b32[2];
assign Reg3Value_ob32 = Reg_q4b32[3];
assign Dat_oab32 = Reg_q4b32[Adr_ib2];
endmodule
\ No newline at end of file
Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
View file @ 71911ca6
`timescale 1ns/100ps
module VfcHdSystem
#(parameter g_SystemVersion_b8 = 8'ha0,
g_SystemReleaseDay_b8 = 8'h12,
g_SystemReleaseMonth_b8 = 8'h06,
g_SystemReleaseYear_b8 = 8'h15)
#(parameter g_SystemVersion_b8 = 8'ha1,
g_SystemReleaseDay_b8 = 8'h02,
g_SystemReleaseMonth_b8 = 8'h03,
g_SystemReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
......
Hdl/Simulation/BaseProjectAppAcceses/modelsim/project/BaseProjectAppAcceses_sim.mpf 0 → 100644
View file @ 71911ca6
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
; Altera Primitive libraries
;
; VHDL Section
;
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
maxii = $MODEL_TECH/../altera/vhdl/maxii
maxv = $MODEL_TECH/../altera/vhdl/maxv
fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
sgate = $MODEL_TECH/../altera/vhdl/sgate
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
arriav = $MODEL_TECH/../altera/vhdl/arriav
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
;
; Verilog Section
;
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100 ps
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).