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Dimitris Lampridis
VFC-HD
Commits
74166919
Commit
74166919
authored
Sep 19, 2016
by
Manoel Barros Marin
Browse files
Merge branch 'GbtFpga'
parents
ed9a3538
ce495aea
Changes
629
Expand all
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Inline
Side-by-side
Hdl/FpgaModules/ApplicationSpecific/Gbt
Fpga
BaseProject/AddrDecoderWbApp.v
→
Hdl/FpgaModules/ApplicationSpecific/GbtBaseProject/AddrDecoderWbApp.v
View file @
74166919
...
...
@@ -17,25 +17,43 @@ module AddrDecoderWBApp(
input
[
31
:
0
]
DatStatReg_ib32
,
input
AckStatReg_i
,
output
reg
StbStatReg_o
output
reg
StbStatReg_o
,
input
[
31
:
0
]
DatPllRef_ib32
,
input
AckPllRef_i
,
output
reg
StbPllRef_o
,
input
[
31
:
0
]
DatGbtCtrlReg_ib32
,
input
AckGbtCtrlReg_i
,
output
reg
StbGbtCtrlReg_o
,
input
[
31
:
0
]
DatGbtStatReg_ib32
,
input
AckGbtStatReg_i
,
output
reg
StbGbtStatReg_o
);
localparam
dly
=
1
;
reg
[
1
:
0
]
SelectedModule_b
2
;
reg
[
2
:
0
]
SelectedModule_b
3
;
localparam
c_SelNothing
=
2'd0
,
c_SelAppRevisionId
=
2'd1
,
c_SelCtrlReg
=
2'd2
,
c_SelStatReg
=
2'd3
;
localparam
c_SelNothing
=
3'd0
,
c_SelAppRevisionId
=
3'd1
,
c_SelCtrlReg
=
3'd2
,
c_SelStatReg
=
3'd3
,
c_SelPllRef
=
3'd4
,
c_SelGbtCtrlReg
=
3'd5
,
c_SelGbtStatReg
=
3'd6
;
always
@*
casez
(
Adr_ib21
)
21'b0_0000_0000_0000_0000_00??
:
SelectedModule_b2
=
c_SelAppRevisionId
;
// FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_01??
:
SelectedModule_b2
=
c_SelCtrlReg
;
// FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_10??
:
SelectedModule_b2
=
c_SelStatReg
;
// FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
default:
SelectedModule_b2
=
c_SelNothing
;
21'b0_0000_0000_0000_0000_00??
:
SelectedModule_b3
=
c_SelAppRevisionId
;
// FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_01??
:
SelectedModule_b3
=
c_SelCtrlReg
;
// FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_10??
:
SelectedModule_b3
=
c_SelStatReg
;
// FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_110?
:
SelectedModule_b3
=
c_SelPllRef
;
// FROM 00_000C TO 00_000D (WB) == FROM 00_0030 TO 00_0034 (VME) <- 2 regs ( 8B)
21'b0_0000_0000_0000_0001_00??
:
SelectedModule_b3
=
c_SelGbtCtrlReg
;
// FROM 00_0010 TO 00_0013 (WB) == FROM 00_0040 TO 00_004C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0001_01??
:
SelectedModule_b3
=
c_SelGbtStatReg
;
// FROM 00_0014 TO 00_0017 (WB) == FROM 00_0050 TO 00_005C (VME) <- 4 regs (16B)
default:
SelectedModule_b3
=
c_SelNothing
;
endcase
always
@
(
posedge
Clk_ik
)
begin
...
...
@@ -44,7 +62,8 @@ always @(posedge Clk_ik) begin
StbAppReleaseId_o
<=
#
dly
1'b0
;
StbCtrlReg_o
<=
#
dly
1'b0
;
StbStatReg_o
<=
#
dly
1'b0
;
case
(
SelectedModule_b2
)
StbPllRef_o
<=
#
dly
1'b0
;
case
(
SelectedModule_b3
)
c_SelAppRevisionId:
begin
StbAppReleaseId_o
<=
#
dly
Stb_i
;
Dat_ob32
<=
#
dly
DatAppReleaseId_ib32
;
...
...
@@ -60,6 +79,21 @@ always @(posedge Clk_ik) begin
Dat_ob32
<=
#
dly
DatStatReg_ib32
;
Ack_o
<=
#
dly
AckStatReg_i
;
end
c_SelPllRef:
begin
StbPllRef_o
<=
#
dly
Stb_i
;
Dat_ob32
<=
#
dly
DatPllRef_ib32
;
Ack_o
<=
#
dly
AckPllRef_i
;
end
c_SelGbtCtrlReg:
begin
StbGbtCtrlReg_o
<=
#
dly
Stb_i
;
Dat_ob32
<=
#
dly
DatGbtCtrlReg_ib32
;
Ack_o
<=
#
dly
AckGbtCtrlReg_i
;
end
c_SelGbtStatReg:
begin
StbGbtStatReg_o
<=
#
dly
Stb_i
;
Dat_ob32
<=
#
dly
DatGbtStatReg_ib32
;
Ack_o
<=
#
dly
AckGbtStatReg_i
;
end
endcase
end
...
...
Hdl/FpgaModules/ApplicationSpecific/GbtBaseProject/VfcHdApplication.v
0 → 100644
View file @
74166919
This diff is collapsed.
Click to expand it.
Hdl/FpgaModules/ApplicationSpecific/GbtFpgaBaseProject/VfcHdApplication.v
deleted
100644 → 0
View file @
ed9a3538
`timescale
1
ns
/
100
ps
module
VfcHdApplication
#(
parameter
g_ApplicationVersion_b8
=
8'h01
,
g_ApplicationReleaseDay_b8
=
8'h18
,
g_ApplicationReleaseMonth_b8
=
8'h07
,
g_ApplicationReleaseYear_b8
=
8'h16
)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
input
BstSfpRx_i
,
// Comment: Differential signal
output
BstSfpTx_o
,
// Comment: Differential signal
input
EthSfpRx_i
,
// Comment: Differential signal
output
EthSfpTx_o
,
// Comment: Differential signal
// SFP Gbit:
input
[
4
:
1
]
AppSfpRx_ib4
,
// Comment: Differential signal
output
[
4
:
1
]
AppSfpTx_ob4
,
// Comment: Differential signal
// DDR3 SO-DIMM:
output
[
2
:
0
]
DdrBa_ob3
,
output
[
7
:
0
]
DdrDm_ob8
,
inout
[
7
:
0
]
DdrDqs_iob8
,
// Comment: Differential signal
inout
[
63
:
0
]
DdrDq_iob64
,
output
[
15
:
0
]
DdrA_ob16
,
output
[
1
:
0
]
DdrCk_okb2
,
// Comment: Differential signal
output
[
1
:
0
]
DdrCkE_ohb2
,
output
DdrReset_orn
,
output
DdrRas_on
,
output
DdrCas_on
,
output
DdrWe_on
,
output
[
1
:
0
]
DdrCs_onb2
,
output
[
1
:
0
]
DdrOdt_ob2
,
input
DdrTempEvent_in
,
output
DdrI2cScl_ok
,
inout
DdrI2cSda_io
,
// TestIo:
inout
TestIo1_io
,
inout
TestIo2_io
,
// FMC connector:
inout
[
33
:
0
]
FmcLaP_iob34
,
inout
[
33
:
0
]
FmcLaN_iob34
,
inout
[
23
:
0
]
FmcHaP_iob24
,
inout
[
23
:
0
]
FmcHaN_iob24
,
inout
[
21
:
0
]
FmcHbP_iob22
,
inout
[
21
:
0
]
FmcHbN_iob22
,
input
FmcPrsntM2C_in
,
output
FmcTck_ok
,
output
FmcTms_o
,
output
FmcTdi_o
,
input
FmcTdo_i
,
output
FmcTrstL_orn
,
inout
FmcScl_iok
,
inout
FmcSda_io
,
input
FmcPgM2C_in
,
output
FmcPgC2M_on
,
input
FmcClk0M2CCmos_ik
,
input
FmcClk1M2CCmos_ik
,
inout
FmcClk2Bidir_iok
,
// Comment: Differential signal
inout
FmcClk3Bidir_iok
,
// Comment: Differential signal
input
FmcClkDir_i
,
output
[
9
:
0
]
FmcDpC2M_ob10
,
// Comment: Differential signal
input
[
9
:
0
]
FmcDpM2C_ib10
,
input
FmcGbtClk0M2CLeft_ik
,
// Comment: Differential signal
input
FmcGbtClk1M2CLeft_ik
,
// Comment: Differential signal
input
FmcGbtClk0M2CRight_ik
,
// Comment: Differential signal
input
FmcGbtClk1M2CRight_ik
,
// Comment: Differential signal
// Clock sources and control:
output
OeSi57x_oe
,
input
Si57xClk_ik
,
output
ClkFb_ok
,
input
ClkFb_ik
,
input
Clk20VCOx_ik
,
output
PllDac20Sync_o
,
output
PllDac25Sync_o
,
output
PllDacSclk_ok
,
output
PllDacDin_o
,
output
PllRefScl_ok
,
inout
PllRefSda_io
,
input
PllRefInt_i
,
output
PllSourceMuxOut_ok
,
input
PllRefClkOut_ik
,
// Comment: Differential reference for the Gbit lines
input
GbitTrxClkRefR_ik
,
// Comment: Differential reference for the Gbit lines ~125MHz
// SW1:
input
[
1
:
0
]
Switch_ib2
,
// P2 RTM:
inout
[
19
:
0
]
P2DataP_iob20
,
//Comment: The 0 is a clock capable input
inout
[
19
:
0
]
P2DataN_iob20
,
// P0 Timing:
input
[
7
:
0
]
P0HwHighByte_ib8
,
input
[
7
:
0
]
P0HwLowByte_ib8
,
output
DaisyChain1Cntrl_o
,
output
DaisyChain2Cntrl_o
,
input
VmeP0BunchClk_ik
,
input
VmeP0Tclk_ik
,
// GPIO:
inout
[
4
:
1
]
GpIo_iob4
,
// Specials:
input
PushButtonN_in
,
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
// Reset:
input
Reset_irqp
,
// Comment: Reset Synchronous with the WbClk_ik
output
ResetRequest_oqp
,
// Comment: Request to issue a reset
// WishBone:
output
WbClk_ok
,
input
WbSlaveCyc_i
,
input
WbSlaveStb_i
,
input
[
24
:
0
]
WbSlaveAdr_ib25
,
input
WbSlaveWr_i
,
input
[
31
:
0
]
WbSlaveDat_ib32
,
output
[
31
:
0
]
WbSlaveDat_ob32
,
output
WbSlaveAck_o
,
output
WbMasterCyc_o
,
output
WbMasterStb_o
,
output
[
24
:
0
]
WbMasterAdr_ob25
,
output
WbMasterWr_o
,
output
[
31
:
0
]
WbMasterDat_ob32
,
input
[
31
:
0
]
WbMasterDat_ib32
,
input
WbMasterAck_i
,
// LED control:
output
[
1
:
0
]
TopLed_ob2
,
output
[
3
:
0
]
BottomLed_ob4
,
// BST input:
input
BstOn_i
,
input
BunchClk_ik
,
input
TurnClk_ip
,
input
[
5
:
0
]
BstByteAddress_ib5
,
input
[
7
:
0
]
BstByte_ib8
,
// Interrupt:
output
[
23
:
0
]
InterruptRequest_opb24
,
// Ethernet streamer:
output
StreamerClk_ok
,
output
[
31
:
0
]
StreamerData_ob32
,
output
SreamerDav_o
,
output
StreamerPckt_o
,
input
StreamerWait_i
,
// GPIO direction:
output
GpIo1DirOut_o
,
output
GpIo2DirOut_o
,
output
GpIo34DirOut_o
);
//****************************
//Declarations
//****************************
wire
Clk_k
;
wire
WbStbAppReleaseId
,
WbAckAppReleaseId
;
wire
[
31
:
0
]
WbDatAppReleaseId_b32
;
wire
WbStbCtrlReg
,
WbAckCtrlReg
;
wire
[
31
:
0
]
WbDatCtrlReg_b32
;
wire
WbStbStatReg
,
WbAckStatReg
;
wire
[
31
:
0
]
WbDatStatReg_b32
;
wire
WbStbPllRef
,
WbAckPllRef
;
wire
[
31
:
0
]
WbDatPllRef_b32
;
wire
[
31
:
0
]
Reg0Value_b32
;
//****************************
//Fixed assignments
//****************************
assign
OeSi57x_oe
=
1'b1
;
//****************************
//Clocking
//****************************
assign
Clk_k
=
GbitTrxClkRefR_ik
;
//~125MHz
assign
WbClk_ok
=
Clk_k
;
//****************************
//WB address decoder
//****************************
AddrDecoderWBApp
i_AddrDecoderWbApp
(
.
Clk_ik
(
Clk_k
),
.
Adr_ib21
(
WbSlaveAdr_ib25
[
20
:
0
]),
.
Stb_i
(
WbSlaveStb_i
),
.
Dat_ob32
(
WbSlaveDat_ob32
),
.
Ack_o
(
WbSlaveAck_o
),
//--
.
DatAppReleaseId_ib32
(
WbDatAppReleaseId_b32
),
.
AckAppReleaseId_i
(
WbAckAppReleaseId
),
.
StbAppReleaseId_o
(
WbStbAppReleaseId
),
//--
.
DatCtrlReg_ib32
(
WbDatCtrlReg_b32
),
.
AckCtrlReg_i
(
WbAckCtrlReg
),
.
StbCtrlReg_o
(
WbStbCtrlReg
),
//--
.
DatStatReg_ib32
(
WbDatStatReg_b32
),
.
AckStatReg_i
(
WbAckStatReg
),
.
StbStatReg_o
(
WbStbStatReg
));
//****************************
//Release ID
//****************************
Generic4InputRegs
i_AppReleaseId
(
.
Rst_irq
(
Reset_irqp
),
.
Clk_ik
(
Clk_k
),
.
Cyc_i
(
WbSlaveCyc_i
),
.
Stb_i
(
WbStbAppReleaseId
),
.
Adr_ib2
(
WbSlaveAdr_ib25
[
1
:
0
]),
.
Dat_oab32
(
WbDatAppReleaseId_b32
),
.
Ack_oa
(
WbAckAppReleaseId
),
.
Reg0Value_ib32
(
"VFC-"
),
.
Reg1Value_ib32
(
"HD G"
),
.
Reg2Value_ib32
(
"BT "
),
.
Reg3Value_ib32
(
{
g_ApplicationVersion_b8
,
g_ApplicationReleaseDay_b8
,
g_ApplicationReleaseMonth_b8
,
g_ApplicationReleaseYear_b8
}
));
//****************************
//Example registers
//****************************
//Control register bank:
Generic4OutputRegs
#(
.
Reg0Default
(
32'hBABEB00B
),
.
Reg0AutoClrMask
(
32'hFFFFFFFF
),
.
Reg1Default
(
32'h00000000
),
.
Reg1AutoClrMask
(
32'hFFFFFFFF
),
.
Reg2Default
(
32'h00000000
),
.
Reg2AutoClrMask
(
32'hFFFFFFFF
),
.
Reg3Default
(
32'h00000000
),
.
Reg3AutoClrMask
(
32'hFFFFFFFF
))
i_ControlRegs
(
.
Clk_ik
(
Clk_k
),
.
Rst_irq
(
Reset_irqp
),
.
Cyc_i
(
WbSlaveCyc_i
),
.
Stb_i
(
WbStbCtrlReg
),
.
We_i
(
WbSlaveWr_i
),
.
Adr_ib2
(
WbSlaveAdr_ib25
[
1
:
0
]),
.
Dat_ib32
(
WbSlaveDat_ib32
),
.
Dat_oab32
(
WbDatCtrlReg_b32
),
.
Ack_oa
(
WbAckCtrlReg
),
//--
.
Reg0Value_ob32
(
Reg0Value_b32
),
.
Reg1Value_ob32
(),
.
Reg2Value_ob32
(),
.
Reg3Value_ob32
());
//Status registers bank:
Generic4InputRegs
i_StatusRegs
(
.
Clk_ik
(
Clk_k
),
.
Rst_irq
(
Reset_irqp
),
.
Cyc_i
(
WbSlaveCyc_i
),
.
Stb_i
(
WbStbStatReg
),
.
Adr_ib2
(
WbSlaveAdr_ib25
[
1
:
0
]),
.
Dat_oab32
(
WbDatStatReg_b32
),
.
Ack_oa
(
WbAckStatReg
),
//--
.
Reg0Value_ib32
(
Reg0Value_b32
),
.
Reg1Value_ib32
(
32'hCAFEAC1D
),
.
Reg2Value_ib32
(
32'hACDCDEAD
),
.
Reg3Value_ib32
(
32'hFEEDBEEF
));
//****************************
//PLL Ref (Si5338) I2C control
//****************************
I2cMasterWb
#(
.
g_CycleLenght
(
10'd256
))
i_I2cPllRef
(
.
Clk_ik
(
Clk_k
),
.
Rst_irq
(
Reset_irqp
),
.
Cyc_i
(
WbSlaveCyc_i
),
.
Stb_i
(
WbStbStatReg
),
.
We_i
(
WbSlaveWr_i
),
.
Adr_ib2
(
WbSlaveAdr_ib25
[
1
:
0
]),
.
Dat_ib32
(
WbSlaveDat_ib32
),
.
Dat_oab32
(
WbDatPllRef_b32
),
.
Ack_oa
(
WbAckPllRef
),
.
Scl_ioz
(
PllRefScl_ok
),
.
Sda_ioz
(
PllRefSda_io
));
//****************************
// GBT-FPGA example design
//****************************
endmodule
\ No newline at end of file
Hdl/FpgaModules/GeneralPurpose/GlitchFilter.v
0 → 100644
View file @
74166919
//============================================================================================\\
//################################## Module Information ##################################\\
//============================================================================================\\
//
// Company: CERN (BE-BI)
//
// File Name: GlitchFilter.v
//
// File versions history:
//
// DATE VERSION AUTHOR DESCRIPTION
// - 10/08/16 1.0 M. Barros Marin First module definition.
//
// Language: Verilog 2005
//
// Targeted device:
//
// - Vendor: Agnostic
// - Model: Agnostic
//
// Description:
//
// Module for filtering possible glitches in a serial data stream.
//
//============================================================================================\\
//############################################################################################\\
//============================================================================================\\
`timescale
1
ns
/
100
ps
module
GlitchFilter
//======================================== I/O ports =======================================\\
(
//==== Clocks & Resets ====\\
input
Clk_ik
,
input
Reset_ira
,
//==== Data Path ====\\
input
Input_i
,
output
reg
Output_oq
);
//======================================= Declarations =====================================\\
//==== Wires & Regs ====\\
// Data path:
reg
[
3
:
0
]
Lsr_qb4
;
// Control path:
wire
SetOutput
;
wire
ClrOutput
;
//======================================= User Logic =======================================\\
//==== Data Path ====\\
// Serial data input Left Shift Register (LSR):
always
@
(
posedge
Clk_ik
or
posedge
Reset_ira
)
if
(
Reset_ira
)
Lsr_qb4
<=
#
1
4'h0
;
else
Lsr_qb4
<=
#
1
{
Lsr_qb4
[
2
:
0
],
Input_i
}
;
// Output Set/Clr register:
always
@
(
posedge
Clk_ik
or
posedge
Reset_ira
)
if
(
Reset_ira
)
Output_oq
<=
#
1
1'b0
;
else
if
(
SetOutput
)
Output_oq
<=
#
1
1'b1
;
else
if
(
ClrOutput
)
Output_oq
<=
#
1
1'b0
;
//==== Control Path ====\\
// Output Register Set control:
assign
SetOutput
=
&
Lsr_qb4
;
// Output Register Clear control:
assign
ClrOutput
=
~|
Lsr_qb4
;
endmodule
\ No newline at end of file
Hdl/FpgaModules/GeneralPurpose/HeartBeat.v
0 → 100644
View file @
74166919
//============================================================================================\\
//################################## Module Information ##################################\\
//============================================================================================\\
//
// Company: CERN (BE-BI)
//
// File Name: HeartBeat.v
//
// File versions history:
//
// DATE VERSION AUTHOR DESCRIPTION
// - 08/09/16 1.0 M. Barros Marin First module definition.
//
// Language: Verilog 2005
//
// Targeted device:
//
// - Vendor: Agnostic
// - Model: Agnostic
//
// Description:
//
// - Module for toggling an LED with a periodicity of 1s.
//
//============================================================================================\\
//############################################################################################\\
//============================================================================================\\
`timescale
100
ps
/
10
ps
module
HeartBeat
//==================================== Global Parameters ===================================\\
#(
parameter
g_ClkFrequency_b32
=
32'h02625A00
)
// Comment: Toggling period: 1s@40MHz.
//======================================== I/O ports =======================================\\
(
//==== Clock & Reset ====\\
input
Clk_ik
,
input
Reset_ira
,
//==== Control Path ====\\
output
reg
HeartBeat_oq
);
//======================================= Declarations =====================================\\
//==== Wires & Regs ====\\
reg
[
31
:
0
]
HeartBeatCntr_c32
;
//======================================= User Logic =======================================\\
//======================\\
//==== Control Path ====\\
//======================\\
always
@
(
posedge
Clk_ik
or
posedge
Reset_ira
)
if
(
Reset_ira
)
begin
HeartBeatCntr_c32
<=
#
1
32'h0
;
HeartBeat_oq
<=
#
1
1'b0
;
end
else
begin
if
(
HeartBeatCntr_c32
==
g_ClkFrequency_b32
-
1
)
begin
HeartBeatCntr_c32
<=
#
1
32'h0
;
HeartBeat_oq
<=
#
1
~
HeartBeat_oq
;
end
else
begin
HeartBeatCntr_c32
<=
#
1
HeartBeatCntr_c32
+
1
;
end
end
endmodule
\ No newline at end of file
Hdl/FpgaModules/GeneralPurpose/Ip_Altera/8b10b/decoder_8b10b_mod.v
0 → 100644
View file @
74166919
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 04-10-2006
// an 8b10b decoder, based on files from Martin R and IBM paper
//=============================== MBM (23/08/16) ==========================\\
// Comment: - Although from Altera, this module is VENDOR AGNOSTIC, so it \\
// can be synthesized for any FPGA model. \\
// - The Device specific (Stratix V) part of this module has been \\
// removed in order to simplify the readability of the code. \\
//=========================================================================\\
module
decoder_8b10b
(
clk
,
rst
,
din_ena
,
// 10b data ready
din_dat
,
// 10b data input
din_rd
,
// running disparity input
dout_val
,
// data out valid
dout_dat
,
// data out
dout_k
,
// special code
dout_kerr
,
// coding mistake detected
dout_rderr
,
// running disparity mistake detected
dout_rdcomb
,
// running disparity output (comb)