Commit 763c4d71 authored by Manoel Barros Marin's avatar Manoel Barros Marin
Browse files

- Removed Test Project

- Modified Base application
- Fixed reset bug in system
- Fixed bug in DpramGenericToWb
- Fixed bug in DpramWbToGeneric
- Added Generic16InputRegs
- Renamed several general purpose and system modules
- Reorganiced simulation folders
- Removed compiled modules in I2cMuxAndExpMaster (Configuration scripts missing)
- Added bitstream and PROM files
- Added BaseScript.py
- Modified Class_VfcHd
- Other minot modifications
parent b60789e3
......@@ -63,6 +63,7 @@ initial begin
@(posedge Clk125MHz_kq);
ControlReg1_q = 1'b1;
$display($time, " -> Trigger");
repeat(10000)@(posedge Clk125MHz_kq);
#50000
$display($time, " -> Simulation Stop");
$stop;
......
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'hb2,
g_ApplicationReleaseDay_b8 = 8'h28,
g_ApplicationReleaseMonth_b8 = 8'h04,
#(parameter g_ApplicationVersion_b8 = 8'hC2,
g_ApplicationReleaseDay_b8 = 8'h07,
g_ApplicationReleaseMonth_b8 = 8'h07,
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
......@@ -155,9 +155,6 @@ wire WbStbStatReg, WbAckStatReg;
wire [31:0] WbDatStatReg_b32;
wire [31:0] Reg0Value_b32;
wire [31:0] Reg1Value_b32;
wire [31:0] Reg2Value_b32;
wire [31:0] Reg3Value_b32;
//****************************
//Fixed assignments
......@@ -207,9 +204,9 @@ Generic4InputRegs i_RevisionAndMisc(
.Adr_ib2(WbSlaveAdr_ib25[1:0]),
.Dat_oab32(WbDatAppReleaseId_b32),
.Ack_oa(WbAckAppReleaseId),
.Reg0Value_ib32("VFC "),
.Reg1Value_ib32("HD: "),
.Reg2Value_ib32("base"),
.Reg0Value_ib32("VFC-"),
.Reg1Value_ib32("HD b"),
.Reg2Value_ib32("ase "),
.Reg3Value_ib32({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
//****************************
......@@ -220,11 +217,11 @@ Generic4InputRegs i_RevisionAndMisc(
Generic4OutputRegs #(
.Reg0Default (32'hBABEB00B),
.Reg0AutoClrMask (32'hFFFFFFFF),
.Reg1Default (32'hCAFEAC1D),
.Reg1Default (32'h00000000),
.Reg1AutoClrMask (32'hFFFFFFFF),
.Reg2Default (32'hACDCDEAD),
.Reg2Default (32'h00000000),
.Reg2AutoClrMask (32'hFFFFFFFF),
.Reg3Default (32'hFEEDBEEF),
.Reg3Default (32'h00000000),
.Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs (
.Rst_irq (Reset_irqp),
......@@ -238,9 +235,9 @@ i_ControlRegs (
.Ack_oa (WbAckCtrlReg),
//--
.Reg0Value_ob32 (Reg0Value_b32),
.Reg1Value_ob32 (Reg1Value_b32),
.Reg2Value_ob32 (Reg2Value_b32),
.Reg3Value_ob32 (Reg3Value_b32));
.Reg1Value_ob32 (),
.Reg2Value_ob32 (),
.Reg3Value_ob32 ());
//Status Registers Bank:
Generic4InputRegs i_StatusRegs (
......@@ -253,8 +250,8 @@ Generic4InputRegs i_StatusRegs (
.Ack_oa (WbAckStatReg),
//--
.Reg0Value_ib32 (Reg0Value_b32),
.Reg1Value_ib32 (Reg1Value_b32),
.Reg2Value_ib32 (Reg2Value_b32),
.Reg3Value_ib32 (Reg3Value_b32));
.Reg1Value_ib32 (32'hCAFEAC1D),
.Reg2Value_ib32 (32'hACDCDEAD),
.Reg3Value_ib32 (32'hFEEDBEEF));
endmodule
\ No newline at end of file
`timescale 1ns/100ps
module AddrDecoderWBApp(
input Clk_ik,
input [20:0] Adr_ib21,
input Stb_i,
output reg [31:0] Dat_ob32,
output reg Ack_o,
input [31:0] DatI2cPllRef_ib32,
input AckI2cPllRef_i,
output reg StbI2cPllRef_o,
input [31:0] DatAppReleaseId_ib32,
input AckAppReleaseId_i,
output reg StbAppReleaseId_o,
input [31:0] DatPeriodCounter_ib32,
input AckPeriodCounter_i,
output reg StbPeriodCounter_o,
input [31:0] DatSpiMaster_ib32,
input AckSpiMaster_i,
output reg StbSpiMaster_o,
input [31:0] DatFmcTest_ib32,
input AckFmcTest_i,
output reg StbFmcTest_o,
input [31:0] DatMgtTest_ib32,
input AckMgtTest_i,
output reg StbMgtTest_o,
input [31:0] DatGpIoControl_ib32,
input AckGpIoControl_i,
output reg StbGpIoControl_o
);
localparam dly = 1;
reg [7:0] SelectedModule_b8;
localparam c_SelNothing = 8'h0,
c_SelI2cPllRef = 8'd1,
c_SelPeriodCounter = 8'd2,
c_SelSpiMaster = 8'd3,
c_SelFmcTest = 8'd4,
c_SelMgtTest = 8'd5,
c_SelGpIoControl = 8'd6,
c_SelAppRevisionId = 8'd7;
always @*
casez(Adr_ib21)
21'b0_0000_0000_0000_0000_00??: SelectedModule_b8 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0000_01??: SelectedModule_b8 = c_SelPeriodCounter; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0000_1???: SelectedModule_b8 = c_SelSpiMaster; // FROM 00_0008 TO 00_000F (WB) == FROM 00_0020 TO 00_003C (VME) <- 8 regs ( 32B)
21'b0_0000_0000_0000_0001_00??: SelectedModule_b8 = c_SelGpIoControl; // FROM 00_0010 TO 00_0013 (WB) == FROM 00_0040 TO 00_004C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0001_01??: SelectedModule_b8 = c_SelI2cPllRef; // FROM 00_0014 TO 00_0017 (WB) == FROM 00_0050 TO 00_005C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_001?_????: SelectedModule_b8 = c_SelFmcTest; // FROM 00_0020 TO 00_003F (WB) == FROM 00_0080 TO 00_00FC (VME) <- 32 regs (128B)
21'b0_0000_0000_0000_1???_????: SelectedModule_b8 = c_SelMgtTest; // FROM 00_0080 TO 00_00FF (WB) == FROM 00_0200 TO 00_03FC (VME) <- 128 regs (512B)
default: SelectedModule_b8 = c_SelNothing;
endcase
always @(posedge Clk_ik) begin
Ack_o <= #dly 1'b0;
Dat_ob32 <= #dly 32'h0;
StbI2cPllRef_o <= #dly 1'b0;
StbPeriodCounter_o <= #dly 1'b0;
StbSpiMaster_o <= #dly 1'b0;
StbMgtTest_o <= #dly 1'b0;
StbFmcTest_o <= #dly 1'b0;
StbGpIoControl_o <= #dly 1'b0;
StbAppReleaseId_o <= #dly 1'b0;
case(SelectedModule_b8)
c_SelAppRevisionId: begin
StbAppReleaseId_o <= #dly Stb_i;
Dat_ob32 <= #dly DatAppReleaseId_ib32;
Ack_o <= #dly AckAppReleaseId_i;
end
c_SelI2cPllRef: begin
StbI2cPllRef_o <= #dly Stb_i;
Dat_ob32 <= #dly DatI2cPllRef_ib32;
Ack_o <= #dly AckI2cPllRef_i;
end
c_SelPeriodCounter: begin
StbPeriodCounter_o <= #dly Stb_i;
Dat_ob32 <= #dly DatPeriodCounter_ib32;
Ack_o <= #dly AckPeriodCounter_i;
end
c_SelSpiMaster: begin
StbSpiMaster_o <= #dly Stb_i;
Dat_ob32 <= #dly DatSpiMaster_ib32;
Ack_o <= #dly AckSpiMaster_i;
end
c_SelFmcTest: begin
StbFmcTest_o <= #dly Stb_i;
Dat_ob32 <= #dly DatFmcTest_ib32;
Ack_o <= #dly AckFmcTest_i;
end
c_SelMgtTest: begin
StbMgtTest_o <= #dly Stb_i;
Dat_ob32 <= #dly DatMgtTest_ib32;
Ack_o <= #dly AckMgtTest_i;
end
c_SelGpIoControl: begin
StbGpIoControl_o <= #dly Stb_i;
Dat_ob32 <= #dly DatGpIoControl_ib32;
Ack_o <= #dly AckGpIoControl_i;
end
endcase
end
endmodule
`timescale 1ns/100ps
//Manoel Barros Marin, BE-BI-QP (CERN) - 04/06/15
module user_io_checker # (
//***********
//Parameters:
//***********
parameter g_BusWidth = 80,
g_ReadDly = 30, //10cycles@125MHz = 240ns
g_TestDly = 10) (
//*****
//I/Os:
//*****
input Reset_ir,
input Clk_ik,
input Trigger_i,
input [g_BusWidth-1:0] Data_ib,
output [g_BusWidth-1:0] Data_ob,
output reg Busy_o,
output [g_BusWidth-1:0] BusErrors_ob,
output reg BusCorrect_o
);
//*************
//Declarations:
//*************
localparam s_Idle = 6'b000001,
s_SendMarchingZero = 6'b000010,
s_CheckMarchingZero = 6'b000100,
s_SendMarchingOne = 6'b001000,
s_CheckMarchingOne = 6'b010000,
s_TestDone = 6'b100000;
reg [ 5:0] State_qb6, NextState_qb6;
reg [ 7:0] Timer_qb8;
reg [g_BusWidth-1:0] DataO_qb;
reg [g_BusWidth-1:0] DataI_qb;
reg [g_BusWidth-1:0] ZerosErrors_qb;
reg [g_BusWidth-1:0] OnesErrors_qb;
reg [g_BusWidth-1:0] BusErrors_qb;
integer i;
//***********
//User Logic:
//***********
//FSM:
always @(posedge Clk_ik) State_qb6 <= #1 Reset_ir ? s_Idle : NextState_qb6;
always @* begin
NextState_qb6 = State_qb6;
case(State_qb6)
s_Idle: begin
if (Trigger_i) begin
NextState_qb6 = s_SendMarchingZero;
end
end
s_SendMarchingZero: begin
if (Timer_qb8 == g_ReadDly-1) begin
NextState_qb6 = s_CheckMarchingZero;
end
end
s_CheckMarchingZero: begin
if (i == g_BusWidth-1) begin
NextState_qb6 = s_SendMarchingOne;
end else begin
NextState_qb6 = s_SendMarchingZero;
end
end
s_SendMarchingOne: begin
if (Timer_qb8 == g_ReadDly-1) begin
NextState_qb6 = s_CheckMarchingOne;
end
end
s_CheckMarchingOne: begin
if (i == g_BusWidth) begin
NextState_qb6 = s_TestDone;
end else begin
NextState_qb6 = s_SendMarchingOne;
end
end
s_TestDone: begin
end
default: begin
NextState_qb6 = s_Idle;
end
endcase
end
always @(posedge Clk_ik)
if (Reset_ir) begin
i <= #1 0;
Busy_o <= #1 1'b0;
Timer_qb8 <= #1 8'b0;
DataO_qb <= #1 {g_BusWidth{1'b1}};
ZerosErrors_qb <= #1 {g_BusWidth{1'b0}};
OnesErrors_qb <= #1 {g_BusWidth{1'b0}};
BusErrors_qb <= #1 {g_BusWidth{1'b0}};
BusCorrect_o <= #1 1'b0;
end else begin
case(State_qb6)
s_Idle: begin
i <= #1 0;
Busy_o <= #1 1'b0;
Timer_qb8 <= #1 8'b0;
DataO_qb <= #1 {g_BusWidth{1'b1}};
ZerosErrors_qb <= #1 {g_BusWidth{1'b0}};
OnesErrors_qb <= #1 {g_BusWidth{1'b0}};
BusErrors_qb <= #1 {g_BusWidth{1'b0}};
BusCorrect_o <= #1 1'b0;
end
s_SendMarchingZero: begin
Busy_o <= #1 1'b1;
if (i > 0) begin
DataO_qb[i-1] <= #1 1'b1;
end
DataO_qb[i] <= #1 1'b0;
Timer_qb8 <= #1 Timer_qb8+1;
end
s_CheckMarchingZero: begin
Timer_qb8 <= #1 8'b0;
if (DataI_qb[i] != DataO_qb[i]) begin
ZerosErrors_qb[i] <= #1 'b1;
end
if (NextState_qb6 == s_SendMarchingOne) begin
i <= #1 1'b0;
DataO_qb <= #1 {g_BusWidth{1'b0}};
end else begin
i <= #1 i+1;
end
end
s_SendMarchingOne: begin
if (i > 0) begin
DataO_qb[i-1] <= #1 1'b0;
end
DataO_qb[i] <= #1 1'b1;
Timer_qb8 <= #1 Timer_qb8+1;
end
s_CheckMarchingOne: begin
Timer_qb8 <= #1 8'b0;
if (DataI_qb[i] != DataO_qb[i]) begin
OnesErrors_qb[i] <= #1 'b1;
end
if (NextState_qb6 == s_TestDone) begin
i <= #1 1'b0;
end else begin
i <= #1 i+1;
end
end
s_TestDone: begin
if (Timer_qb8 == g_TestDly-1) begin
Busy_o <= #1 1'b0;
BusErrors_qb <= #1 ZerosErrors_qb | OnesErrors_qb;
BusCorrect_o <= #1 ~|(ZerosErrors_qb | OnesErrors_qb);
end else begin
Timer_qb8 <= #1 Timer_qb8+1;
end
end
endcase
end
assign Data_ob = DataO_qb;
assign BusErrors_ob = BusErrors_qb;
//Sequential Logic:
always @(posedge Clk_ik)
if (Reset_ir) begin
DataI_qb <= #1 {g_BusWidth{1'b0}};
end else begin
DataI_qb <= #1 Data_ib;
end
endmodule
\ No newline at end of file
`timescale 1ns / 1ps
// Manoel Barros Marin, BE-BI-QP (CERN) - 11/05/15
// (Original design: Houssem Laroussi)
module prbs_chck_40b # (
//***********
//Parameters:
//***********
parameter g_Words2Sync = 8'h3F,
parameter g_Words2lossOfSync = 8'h7F) (
//*****
//I/Os:
//*****
input Clk_ik,
input Reset_ir,
input RxAligned_i,
input [39:0] RxData_ib40,
input ErrorCntrReset_i,
output reg Synchronized_o,
output reg [39:0] BitErrors_ob40,
output reg [63:0] WordsCntr_ocb64,
output reg [63:0] ErrorCntr_ocb64,
output reg ErrorFlag_o
);
//*************
//Declarations:
//*************
//FSM:
localparam l_InitialDly = 4'hf;
localparam s_Idle = 3'b001,
s_Sync = 3'b010,
s_Check = 3'b100;
reg [ 2:0] State_qb3, NextState_qb3;
reg [ 3:0] InitialDlyCntr_qb4;
reg SeedReady_q;
reg [ 7:0] Words2SyncCntr_qb8;
reg [ 7:0] LossOfSyncCntr_cb8;
//Sequential Logic:
reg [39:0] RxData_qb40 [1:2];
reg [39:0] RecPattern_qb40;
reg LFb;
reg [30:0] Lsr_qb31; // PRBS-31
reg [ 5:0] i;
reg [ 4:0] j;
//***********
//User Logic:
//***********
//FSM:
always @(posedge Clk_ik) State_qb3 <= #1 Reset_ir ? s_Idle : NextState_qb3;
always @* begin
NextState_qb3 = State_qb3;
case(State_qb3)
s_Idle: begin
if (RxAligned_i) begin
NextState_qb3 = s_Sync;
end
end
s_Sync: begin
if (Words2SyncCntr_qb8 == g_Words2Sync-1) begin
NextState_qb3 = s_Check;
end else if (LossOfSyncCntr_cb8 == g_Words2lossOfSync-1) begin
NextState_qb3 = s_Idle;
end
end
s_Check: begin
if (LossOfSyncCntr_cb8 == g_Words2lossOfSync-1) begin
NextState_qb3 = s_Idle;
end
end
default: begin
NextState_qb3 = s_Idle;
end
endcase
end
always @(posedge Clk_ik)
if (Reset_ir) begin
InitialDlyCntr_qb4 <= #1 4'b0;
SeedReady_q <= #1 1'b0;
Synchronized_o <= #1 1'b0;
WordsCntr_ocb64 <= #1 64'b0;
ErrorFlag_o <= #1 1'b0;
BitErrors_ob40 <= #1 40'b0;
ErrorCntr_ocb64 <= #1 64'b0;
Words2SyncCntr_qb8 <= #1 8'b0;
LossOfSyncCntr_cb8 <= #1 8'b0;
end else begin
case(State_qb3)
s_Idle: begin
InitialDlyCntr_qb4 <= #1 4'b0;
SeedReady_q <= #1 1'b0;
Synchronized_o <= #1 1'b0;
WordsCntr_ocb64 <= #1 64'b0;
ErrorFlag_o <= #1 1'b0;
BitErrors_ob40 <= #1 40'b0;
ErrorCntr_ocb64 <= #1 64'b0;
Words2SyncCntr_qb8 <= #1 8'b0;
LossOfSyncCntr_cb8 <= #1 8'b0;
end
s_Sync: begin
if (InitialDlyCntr_qb4 == l_InitialDly-1) begin
SeedReady_q <= #1 1'b1;
if (RxData_qb40[2] == RecPattern_qb40) begin
Words2SyncCntr_qb8 <= #1 Words2SyncCntr_qb8+1;
LossOfSyncCntr_cb8 <= #1 8'b0;
end else begin
Words2SyncCntr_qb8 <= #1 8'b0;
LossOfSyncCntr_cb8 <= #1 LossOfSyncCntr_cb8+1;
end
end else begin
InitialDlyCntr_qb4 <= #1 InitialDlyCntr_qb4+1;
end
end
s_Check: begin
Synchronized_o <= #1 1'b1;
WordsCntr_ocb64 <= #1 WordsCntr_ocb64+1;
BitErrors_ob40 <= #1 RxData_qb40[2]^RecPattern_qb40;
if (RxData_qb40[2] != RecPattern_qb40) begin
ErrorFlag_o <= #1 1'b1;
ErrorCntr_ocb64 <= #1 ErrorCntr_ocb64+1;
LossOfSyncCntr_cb8 <= #1 LossOfSyncCntr_cb8+1;
end else begin
ErrorFlag_o <= #1 1'b0;
LossOfSyncCntr_cb8 <= #1 8'b0;
if(ErrorCntrReset_i) begin
ErrorCntr_ocb64 <= #1 64'b0;
end
end
end
endcase
end
//Sequential Logic:
always @(posedge Clk_ik)
if (Reset_ir) begin
RxData_qb40[1] <= #1 40'b0;
RxData_qb40[2] <= #1 40'b0;
//---
RecPattern_qb40 <= #1 40'b0;
LFb <= #1 1'b0;
Lsr_qb31 <= #1 31'b0;
i <= #1 6'b0;
j <= #1 5'b0;
end else begin
RxData_qb40[2] <= #1 RxData_qb40[1];
RxData_qb40[1] <= #1 RxData_ib40;
//---
if (SeedReady_q) begin
repeat (40) begin
RecPattern_qb40[i] = Lsr_qb31[30];
LFb = Lsr_qb31[30]^Lsr_qb31[27]; // See Xilinx XAPP210
Lsr_qb31 = {Lsr_qb31[29:0],LFb};
i = i+1;
end
i = 1'b0;
end else begin
repeat (31) begin
Lsr_qb31[30-j] = RxData_ib40[j];
j = j+1;
end
j = 1'b0;
RecPattern_qb40 <= #1 40'b0;
LFb <= #1 1'b0;
end
end
endmodule
\ No newline at end of file
`timescale 1ns / 1ps
//Manoel Barros Marin, BE-BI-QP (CERN) - 11/05/15
// (Original design: Paschalis Vichoudis)
module prbs_gen_40b # (
//***********