- Added FrontEndSpecific README file

- Modified .gitignore

.gitignore

-*.bak
-*.pyc
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.asm64
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.rw64
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.asm64
@@ -48,19 +46,8 @@ Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/veril
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.rw64
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
 Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
-Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
-Doc/AlteraDocuments/EMIF_Altera.pdf
-Doc/AlteraDocuments/an520.pdf
-Doc/AlteraDocuments/arriav_handbook.pdf
-Doc/AlteraDocuments/ddr3AlteraDesign.pdf
-Doc/Datasheets/8Gb_DDR3L.pdf
-Hw/Assembly data/
-Hw/EDA-03133-V2-0_project.Annotation
-Hw/EDA-03133-V2-0_project.PrjPCB
-Hw/EDA-03133-V2-0_project.PrjPCBStructure
-Hw/Manufacturing/EDA-03133-V2_mfg.cam
-Hw/PCB-Layout/
-Hw/Schematics/
+*.bak
+*.pyc
 *.rpt
 *.qws
 *.qdf
@@ -77,18 +64,12 @@ Hw/Schematics/
 *.hier_info
 *.hif
 *.html
-*.txt
 *.ammdb
 *.ddb
 *.sci
 *.stp
 *.tdf
-*.qip
 *.sopcinfo
-*.v
-*.tcl
-*.sv
-*.vhd
 *.dpi
 *.hb_info
 *.sig
@@ -96,3 +77,4 @@ Hw/Schematics/
 *.done
 *.summary
 *.smsg
+Hdl/Synthesis/BoardTest/QuartusPrj/db/

Hdl/FpgaModules/FrontEndSpecific/README.txt

+This folder is intended to store the HDL files of the FPGA-based Digital Front-End if existing.
\ No newline at end of file