Commit 809a55aa authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WRBtrain]: switched to dedicated wrbtrain repository

parent 3dd3145d
......@@ -4,6 +4,6 @@
[submodule "Hdl/FpgaModules/SystemSpecific/wr-cores"]
path = Hdl/FpgaModules/SystemSpecific/WhiteRabbit/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "Hdl/FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit"]
path = Hdl/FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit
url = ssh://git@gitlab.cern.ch:7999/BTrain-TEAM/PS-BTrain-over-WhiteRabbit.git
[submodule "Hdl/FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit"]
path = Hdl/FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit
url = ssh://git@gitlab.cern.ch:7999/BTrain-TEAM/Btrain-over-WhiteRabbit.git
......@@ -163,38 +163,38 @@ i_WrBtrainWrapper (
assign VfmcEnableN_oen = 1'b0;
assign FmcLaP_ob34[0] = ~WrBtrainBvalue[31];
assign FmcLaP_ob34[2] = WrBtrainBvalue[30];
assign FmcLaN_ob34[0] = WrBtrainBvalue[29];
assign FmcLaN_ob34[2] = WrBtrainBvalue[28];
assign FmcLaP_ob34[3] = WrBtrainBvalue[27];
assign FmcLaP_ob34[4] = WrBtrainBvalue[26];
assign FmcLaN_ob34[3] = WrBtrainBvalue[25];
assign FmcLaN_ob34[4] = WrBtrainBvalue[24];
assign FmcLaP_ob34[8] = WrBtrainBvalue[23];
assign FmcLaP_ob34[7] = WrBtrainBvalue[22];
assign FmcLaN_ob34[8] = WrBtrainBvalue[21];
assign FmcLaN_ob34[7] = WrBtrainBvalue[20];
assign FmcLaP_ob34[12] = WrBtrainBvalue[19];
assign FmcLaP_ob34[11] = WrBtrainBvalue[18];
assign FmcLaN_ob34[12] = WrBtrainBvalue[17];
assign FmcLaN_ob34[11] = WrBtrainBvalue[16];
assign FmcLaP_ob34[16] = WrBtrainBvalue[15];
assign FmcLaP_ob34[15] = WrBtrainBvalue[14];
assign FmcLaN_ob34[16] = WrBtrainBvalue[13];
assign FmcLaN_ob34[15] = WrBtrainBvalue[12];
assign FmcLaP_ob34[20] = WrBtrainBvalue[11];
assign FmcLaP_ob34[19] = WrBtrainBvalue[10];
assign FmcLaN_ob34[20] = WrBtrainBvalue[9];
assign FmcLaN_ob34[19] = WrBtrainBvalue[8];
assign FmcLaP_ob34[22] = WrBtrainBvalue[7];
assign FmcLaP_ob34[21] = WrBtrainBvalue[6];
assign FmcLaN_ob34[22] = WrBtrainBvalue[5];
assign FmcLaN_ob34[21] = WrBtrainBvalue[4];
assign FmcLaP_ob34[25] = WrBtrainBvalue[3];
assign FmcLaP_ob34[24] = WrBtrainBvalue[2];
assign FmcLaN_ob34[25] = WrBtrainBvalue[1];
assign FmcLaN_ob34[24] = WrBtrainBvalue[0];
assign FmcLaP_ob34[0] = WrBtrainBvalue[31];
assign FmcLaP_ob34[2] = WrBtrainBvalue[30];
assign FmcLaN_ob34[0] = WrBtrainBvalue[29];
assign FmcLaN_ob34[2] = WrBtrainBvalue[28];
assign FmcLaP_ob34[3] = WrBtrainBvalue[27];
assign FmcLaP_ob34[4] = WrBtrainBvalue[26];
assign FmcLaN_ob34[3] = WrBtrainBvalue[25];
assign FmcLaN_ob34[4] = WrBtrainBvalue[24];
assign FmcLaP_ob34[8] = WrBtrainBvalue[23];
assign FmcLaP_ob34[7] = WrBtrainBvalue[22];
assign FmcLaN_ob34[8] = WrBtrainBvalue[21];
assign FmcLaN_ob34[7] = WrBtrainBvalue[20];
assign FmcLaP_ob34[12] = WrBtrainBvalue[19];
assign FmcLaP_ob34[11] = WrBtrainBvalue[18];
assign FmcLaN_ob34[12] = WrBtrainBvalue[17];
assign FmcLaN_ob34[11] = WrBtrainBvalue[16];
assign FmcLaP_ob34[16] = WrBtrainBvalue[15];
assign FmcLaP_ob34[15] = WrBtrainBvalue[14];
assign FmcLaN_ob34[16] = WrBtrainBvalue[13];
assign FmcLaN_ob34[15] = WrBtrainBvalue[12];
assign FmcLaP_ob34[20] = WrBtrainBvalue[11];
assign FmcLaP_ob34[19] = WrBtrainBvalue[10];
assign FmcLaN_ob34[20] = WrBtrainBvalue[9];
assign FmcLaN_ob34[19] = WrBtrainBvalue[8];
assign FmcLaP_ob34[22] = WrBtrainBvalue[7];
assign FmcLaP_ob34[21] = WrBtrainBvalue[6];
assign FmcLaN_ob34[22] = WrBtrainBvalue[5];
assign FmcLaN_ob34[21] = WrBtrainBvalue[4];
assign FmcLaP_ob34[25] = WrBtrainBvalue[3];
assign FmcLaP_ob34[24] = WrBtrainBvalue[2];
assign FmcLaN_ob34[25] = WrBtrainBvalue[1];
assign FmcLaN_ob34[24] = WrBtrainBvalue[0];
assign FmcLaP_ob34[28] = WrBtrainBvalueUpdated;
assign FmcLaP_ob34[29] = WrBtrainBvalueValid;
......
Subproject commit 8ee58f8016915f205c8b56e459a625712592e9bd
Subproject commit 3a10c23e80700930de0172ea8d196465e05331e6
......@@ -45,9 +45,9 @@ library work;
entity WrBtrainWrapper is
generic (
g_st_data_width : integer:=c_STREAMER_DATA_WIDTH; -- wr streamer data width
g_wb_addr_width : integer:=25; -- wishbone address width
g_wb_data_width : integer:=32 -- wishbone data width
g_st_data_width : integer:=c_BTRAIN_STREAMER_DATA_WIDTH; -- wr streamer data width
g_wb_addr_width : integer:=25; -- wishbone address width
g_wb_data_width : integer:=32 -- wishbone data width
);
port(
clk_i : in std_logic;
......@@ -138,7 +138,6 @@ begin
U_WR_BTRAIN_STUFF: WRBTrain
generic map(
g_data_width => g_st_data_width,
g_slave_granularity => WORD
)
port map(
......@@ -148,14 +147,14 @@ begin
tx_data_o => tx_data_o,
tx_valid_o => tx_valid_o,
tx_dreq_i => tx_dreq_i,
tx_last_o => tx_last_o,
tx_flush_o => tx_flush_o,
tx_last_p1_o => tx_last_o,
tx_flush_p1_o => tx_flush_o,
-- rx
rx_data_i => rx_data_i,
rx_valid_i => rx_valid_i,
rx_first_i => rx_first_i,
rx_first_p1_i => rx_first_i,
rx_dreq_o => rx_dreq_o,
rx_last_i => rx_last_i,
rx_last_p1_i => rx_last_i,
rx_FrameHeader_o => open,
rx_BFramePayloads_o => rx_BFramePayloads,
......@@ -201,6 +200,8 @@ begin
wb_dat_o <= wb_slave_out.dat(g_wb_data_width-1 downto 0);
wb_ack_o <= wb_slave_out.ack;
wb_stall_o <= wb_slave_out.stall;
wb_err_o <= '0';
wb_rty_o <= '0';
wb_slave_in.adr(c_wishbone_address_width-1 downto g_wb_addr_width) <= (others => '0');
wb_slave_in.sel(c_wishbone_address_width/8-1 downto g_wb_addr_width/8) <= (others => '0');
......
......@@ -985,13 +985,14 @@ set_instance_assignment -name SLEW_RATE 1 -to FmcLaP_ob34[0]
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/WRBtrain_wb.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/txCtrlBtrain.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/SynchroGen.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/rxCtrlBtrain.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/WRBTrain.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/WRBtrain_wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/PS-BTrain-over-WhiteRabbit/hdl/rtl/WRBtrainStuff/WRBTrain_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit/hdl/rtl/BtrainFrameEncoderDecoder/BvalueSimGen.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit/hdl/rtl/BtrainFrameEncoderDecoder/WRBtrain_wb.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit/hdl/rtl/BtrainFrameEncoderDecoder/txCtrlBtrain.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit/hdl/rtl/BtrainFrameEncoderDecoder/SynchroGen.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit/hdl/rtl/BtrainFrameEncoderDecoder/rxCtrlBtrain.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit/hdl/rtl/BtrainFrameEncoderDecoder/WRBTrain.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit/hdl/rtl/BtrainFrameEncoderDecoder/WRBtrain_wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/ApplicationSpecific/WrBtrain/Btrain-over-WhiteRabbit/hdl/rtl/BtrainFrameEncoderDecoder/WRBTrain_pkg.vhd"
set_global_assignment -name VHDL_FILE ../../../FpgaModules/ApplicationSpecific/WrBtrain/WrBtrainWrapper.vhd
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/gc_escape_detector.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/timing/pulse_stamper.vhd"
......@@ -1145,5 +1146,5 @@ set_global_assignment -name QIP_FILE "../../../FpgaModules/SystemSpecific/WhiteR
set_global_assignment -name SIP_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/platform/altera/wr_arria5_pll_default/arria5_dmtd_pll_default.sip"
set_global_assignment -name QIP_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/platform/altera/wr_arria5_pll_default/arria5_sys_pll_default.qip"
set_global_assignment -name SIP_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/platform/altera/wr_arria5_pll_default/arria5_sys_pll_default.sip"
set_global_assignment -name SLD_FILE db/VfcHd_BaseProject_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SLD_FILE db/VfcHd_BaseProject_auto_stripped.stp
\ No newline at end of file
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