Commit 839efd62 authored by Manoel Barros Marin's avatar Manoel Barros Marin
Browse files

- Upgraded to Quartus Prime 16

- External Reset controllers
- Fixed bug in TX PLL IP core from Altera
- 4x GX operational
parent 204202a5
......@@ -365,19 +365,19 @@ Generic4InputRegs i_StatusRegs (
// I2C control:
I2cMasterWb #(
.g_CycleLenght (10'd256))
.g_CycleLenght (10'd256))
i_I2cPllRef (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbPllRef),
.We_i (WbSlaveWr_i),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_oab32 (WbDatPllRef_b32),
.Ack_oa (WbAckPllRef),
.Scl_ioz (PllRefScl_ok),
.Sda_ioz (PllRefSda_io));
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbPllRef),
.We_i (WbSlaveWr_i),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_oab32 (WbDatPllRef_b32),
.Ack_oa (WbAckPllRef),
.Scl_ioz (PllRefScl_ok),
.Sda_ioz (PllRefSda_io));
// Clocks forwarding:
assign TestIo1_io = PllRefClkOut_ik;
......@@ -387,23 +387,23 @@ assign TestIo2_io = GbtTxFrameClk40Mhz_k;
// Dummy MGT test
//****************************
//wire [ 3:0] txAnalogReset_from_gxRstCtrl;
//wire [ 3:0] txDigitalReset_from_gxRstCtrl;
//wire [ 0:0] TxPllLocked;
//wire [ 3:0] txCalBusy_from_gxStd;
//wire [ 3:0] rxAnalogReset_from_gxRstCtrl;
//wire [ 3:0] rxDigitalReset_from_gxRstCtrl;
//wire [ 3:0] rxIsLockedToData_from_gxStd;
//wire [ 3:0] rxCalBusy_from_gxStd;
//wire TxPll_clkout;
//wire pllPowerDown_from_txPll;
wire [ 3:0] txAnalogReset_from_gxRstCtrl;
wire [ 3:0] txDigitalReset_from_gxRstCtrl;
wire [ 0:0] TxPllLocked;
wire [ 3:0] txCalBusy_from_gxStd;
wire [ 3:0] rxAnalogReset_from_gxRstCtrl;
wire [ 3:0] rxDigitalReset_from_gxRstCtrl;
wire [ 3:0] rxIsLockedToData_from_gxStd;
wire [ 3:0] rxCalBusy_from_gxStd;
wire TxPll_clkout;
wire pllPowerDown_from_txPll;
//wire [279:0] reconfToXCVR;
//wire [239:0] XCVRToReconf;
//wire [ 69:0] reconfToTxPll;
//wire [ 45:0] TxPllToReconf;
wire [ 3:0] tx_usrclk;
wire [ 3:0] rx_usrclk;
reg [ 39:0] TxData_q40 ;
reg [ 39:0] TxData_q40;
wire [159:0] TxData_b160;
wire [159:0] RxData_b160;
reg [ 39:0] RxData_q40 [3:0];
......@@ -480,28 +480,142 @@ assign TxData_b160 = {TxData_q40,TxData_q40,TxData_q40,TxData_q40};
// .TX_PARALLEL_DATA (TxData_b160),
// .RX_PARALLEL_DATA (RxData_b160));
gx_std_x4_dummy i_4xGxDummy (
.phy_mgmt_clk (PllRefClkOut_ik),
.phy_mgmt_clk_reset (Reset_irqp),
.phy_mgmt_address (9'h0),
.phy_mgmt_read (1'b0),
.phy_mgmt_readdata (),
.phy_mgmt_waitrequest (),
.phy_mgmt_write (1'b0),
.phy_mgmt_writedata (31'h0),
.tx_ready (),
.rx_ready (),
.pll_ref_clk (PllRefClkOut_ik),
.tx_serial_data ({AppSfpTx_ob4[4],AppSfpTx_ob4[3],AppSfpTx_ob4[2],AppSfpTx_ob4[1]}),
.pll_locked (),
.rx_serial_data ({AppSfpRx_ib4[4],AppSfpRx_ib4[3],AppSfpRx_ib4[2],AppSfpRx_ib4[1]}),
.rx_bitslip (4'h0),
.tx_clkout (tx_usrclk[0]),
.rx_clkout (rx_usrclk),
.tx_parallel_data (TxData_b160),
.rx_parallel_data (RxData_b160),
.reconfig_from_xcvr (),
.reconfig_to_xcvr (350'h0));
//gx_std_x4_dummy i_4xGxDummy (
// .phy_mgmt_clk (PllRefClkOut_ik),
// .phy_mgmt_clk_reset (Reset_irqp),
// .phy_mgmt_address (9'h0),
// .phy_mgmt_read (1'b0),
// .phy_mgmt_readdata (),
// .phy_mgmt_waitrequest (),
// .phy_mgmt_write (1'b0),
// .phy_mgmt_writedata (31'h0),
// .tx_ready (),
// .rx_ready (),
// .pll_ref_clk (PllRefClkOut_ik),
// .tx_serial_data ({AppSfpTx_ob4[4],AppSfpTx_ob4[3],AppSfpTx_ob4[2],AppSfpTx_ob4[1]}),
// .pll_locked (),
// .rx_serial_data ({AppSfpRx_ib4[4],AppSfpRx_ib4[3],AppSfpRx_ib4[2],AppSfpRx_ib4[1]}),
// .rx_bitslip (4'h0),
// .tx_clkout (tx_usrclk[0]),
// .rx_clkout (rx_usrclk),
// .tx_parallel_data (TxData_b160),
// .rx_parallel_data (RxData_b160),
// .reconfig_from_xcvr (),
// .reconfig_to_xcvr (350'h0));
generate for (i=0;i<4;i=i+1) begin: GenGxRstCtrl
alt_av_mgt_resetctrl i_GxRstCtrl (
.CLK_I (PllRefClkOut_ik),
.TX_RESET_I (Reset_irqp),
.RX_RESET_I (Reset_irqp),
.TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl[i]),
.TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl[i]),
.TX_READY_O (),
.PLL_LOCKED_I (TxPllLocked),
.TX_CAL_BUSY_I (txCalBusy_from_gxStd[i]),
.RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl[i]),
.RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl[i]),
.RX_READY_O (),
.RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd[i]),
.RX_CAL_BUSY_I (rxCalBusy_from_gxStd[i]));
end endgenerate
//alt_av_mgt_resetctrl i_GxRstCtrl0 (
// .CLK_I (PllRefClkOut_ik),
// .TX_RESET_I (Reset_irqp),
// .RX_RESET_I (Reset_irqp),
// .TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl(0)),
// .TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl(0)),
// .TX_READY_O (),
// .PLL_LOCKED_I (TxPllLocked),
// .TX_CAL_BUSY_I (txCalBusy_from_gxStd(0)),
// .RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl(0)),
// .RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl(0)),
// .RX_READY_O (),
// .RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd(0)),
// .RX_CAL_BUSY_I (rxCalBusy_from_gxStd(0)));
//
//alt_av_mgt_resetctrl i_GxRstCtrl1 (
// .CLK_I (PllRefClkOut_ik),
// .TX_RESET_I (Reset_irqp),
// .RX_RESET_I (Reset_irqp),
// .TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl(1)),
// .TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl(1)),
// .TX_READY_O (),
// .PLL_LOCKED_I (TxPllLocked),
// .TX_CAL_BUSY_I (txCalBusy_from_gxStd(1)),
// .RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl(1)),
// .RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl(1)),
// .RX_READY_O (),
// .RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd(1)),
// .RX_CAL_BUSY_I (rxCalBusy_from_gxStd(1)));
//
//alt_av_mgt_resetctrl i_GxRstCtrl2 (
// .CLK_I (PllRefClkOut_ik),
// .TX_RESET_I (Reset_irqp),
// .RX_RESET_I (Reset_irqp),
// .TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl(2)),
// .TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl(2)),
// .TX_READY_O (),
// .PLL_LOCKED_I (TxPllLocked),
// .TX_CAL_BUSY_I (txCalBusy_from_gxStd(2)),
// .RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl(2)),
// .RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl(2)),
// .RX_READY_O (),
// .RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd(2)),
// .RX_CAL_BUSY_I (rxCalBusy_from_gxStd(2)));
//
//alt_av_mgt_resetctrl i_GxRstCtrl3 (
// .CLK_I (PllRefClkOut_ik),
// .TX_RESET_I (Reset_irqp),
// .RX_RESET_I (Reset_irqp),
// .TX_ANALOGRESET_O (txAnalogReset_from_gxRstCtrl(3)),
// .TX_DIGITALRESET_O (txDigitalReset_from_gxRstCtrl(3)),
// .TX_READY_O (),
// .PLL_LOCKED_I (TxPllLocked),
// .TX_CAL_BUSY_I (txCalBusy_from_gxStd(3)),
// .RX_ANALOGRESET_O (rxAnalogReset_from_gxRstCtrl(3)),
// .RX_DIGITALRESET_O (rxDigitalReset_from_gxRstCtrl(3)),
// .RX_READY_O (),
// .RX_IS_LOCKEDTODATA_I (rxIsLockedToData_from_gxStd(3)),
// .RX_CAL_BUSY_I (rxCalBusy_from_gxStd(3)));
alt_av_mgt_txpll i_TxPll (
.RESET_I (Reset_irqp || GbtBankManualResetTx_1_r),
.MGT_REFCLK_I (PllRefClkOut_ik),
.FEEDBACK_CLK_I (1'b0),
.FEEDBACK_CLK_O (),
.EXTGXTXPLL_CLK_O (TxPll_clkout),
.POWER_DOWN_O (pllPowerDown_from_txPll),
.LOCKED_O (TxPllLocked),
.RECONFIG_I (70'h0),
.RECONFIG_O ());
alt_av_gx_std_x4 i_4xGx (
.pll_powerdown ({pllPowerDown_from_txPll, pllPowerDown_from_txPll, pllPowerDown_from_txPll, pllPowerDown_from_txPll}),
.tx_analogreset (txAnalogReset_from_gxRstCtrl),
.tx_digitalreset (txDigitalReset_from_gxRstCtrl),
.tx_serial_data ({AppSfpTx_ob4[4],AppSfpTx_ob4[3],AppSfpTx_ob4[2],AppSfpTx_ob4[1]}),
.ext_pll_clk ({TxPll_clkout, TxPll_clkout, TxPll_clkout, TxPll_clkout}),
.rx_analogreset (rxAnalogReset_from_gxRstCtrl),
.rx_digitalreset (rxDigitalReset_from_gxRstCtrl),
.rx_cdr_refclk (PllRefClkOut_ik),
.rx_serial_data ({AppSfpRx_ib4[4],AppSfpRx_ib4[3],AppSfpRx_ib4[2],AppSfpRx_ib4[1]}),
.rx_is_lockedtoref (),
.rx_is_lockedtodata (rxIsLockedToData_from_gxStd),
.rx_seriallpbken (4'h0),
.tx_std_coreclkin ({tx_usrclk[0], tx_usrclk[0], tx_usrclk[0], tx_usrclk[0]}),
.rx_std_coreclkin (rx_usrclk),
.tx_std_clkout (tx_usrclk),
.rx_std_clkout (rx_usrclk),
.tx_std_polinv (4'h0),
.rx_std_polinv (4'h0),
.tx_cal_busy (txCalBusy_from_gxStd),
.rx_cal_busy (rxCalBusy_from_gxStd),
.reconfig_to_xcvr (280'h0),
.reconfig_from_xcvr (),
.tx_parallel_data (TxData_b160),
.rx_parallel_data (RxData_b160));
always @(posedge rx_usrclk[0])
if (Reset_irqp) RxData_q40[0] <= #1 40'h0;
......
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone V" variation_name="ObufDdr" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
<global>
<pin name="datain_h[0..0]" direction="input" scope="external" />
<pin name="datain_l[0..0]" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="dataout[0..0]" direction="output" scope="external" />
</global>
</pinplan>
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "15.1"
set_global_assignment -name IP_TOOL_VERSION "16.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ObufDdr.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ObufDdr.ppf"]
......@@ -9,16 +9,16 @@
// ALTDDIO_OUT
//
// Simulation Library Files(s):
// altera_mf
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Standard Edition
// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
......@@ -105,4 +105,3 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.cmp FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ObufDdr.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
......@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
......
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_TOOL_VERSION "15.1"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_TOOL_VERSION "16.0"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "gbt_tx_frameclk_pll" -name MISC_FILE [file join $::quartus(qip_path) "gbt_tx_frameclk_pll.cmp"]
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_TARGETED_DEVICE_FAMILY "Arria V"
......@@ -11,19 +11,19 @@ set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pl
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_VERSION "MTUuMQ=="
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_VERSION "MTYuMA=="
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_NAME "Z2J0X3R4X2ZyYW1lY2xrX3BsbF8wMDAy"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_VERSION "MTUuMQ=="
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_VERSION "MTYuMA=="
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUFHVEZDN0gzRjM1STM=::ZGV2aWNl"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::MQ==::RGV2aWNlIFNwZWVkIEdyYWRl"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::Mg==::RGV2aWNlIFNwZWVkIEdyYWRl"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MTIwLjA=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
......@@ -334,5 +334,5 @@ set_global_assignment -library "gbt_tx_frameclk_pll" -name VERILOG_FILE [file jo
set_global_assignment -library "gbt_tx_frameclk_pll" -name QIP_FILE [file join $::quartus(qip_path) "gbt_tx_frameclk_pll/gbt_tx_frameclk_pll_0002.qip"]
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_TOOL_VERSION "15.1"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_TOOL_VERSION "16.0"
set_global_assignment -entity "gbt_tx_frameclk_pll_0002" -library "gbt_tx_frameclk_pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "lib_gbt_tx_frameclk_pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "lib_gbt_tx_frameclk_pll" -name IP_TOOL_VERSION "15.1"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "lib_gbt_tx_frameclk_pll" -name IP_TOOL_VERSION "16.0"
set_global_assignment -entity "gbt_tx_frameclk_pll" -library "lib_gbt_tx_frameclk_pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lib_gbt_tx_frameclk_pll" -name SPD_FILE [file join $::quartus(sip_path) "gbt_tx_frameclk_pll.spd"]
......
-- megafunction wizard: %Altera PLL v15.1%
-- megafunction wizard: %Altera PLL v16.0%
-- GENERATION: XML
-- gbt_tx_frameclk_pll.vhd
-- Generated using ACDS version 15.1 185
-- Generated using ACDS version 16.0 211
library IEEE;
use IEEE.std_logic_1164.all;
......@@ -64,12 +64,12 @@ end architecture rtl; -- of gbt_tx_frameclk_pll
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="15.1" >
-- Retrieval info: <instance entity-name="altera_pll" version="16.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Arria V" />
-- Retrieval info: <generic name="device" value="5AGTFC7H3F35I3" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="2" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="120.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
......
......@@ -12,37 +12,75 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 15.1 185 win32 2016.07.18.17:01:05
# ACDS 16.0 211 win32 2016.08.03.10:21:27
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
# This script can be used to simulate the following IP:
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# gbt_tx_frameclk_pll
# To create a top-level simulation script which compiles other
# IP, and manages other system issues, copy the following template
# and adapt it to your needs:
#
# # Start of template
# # If the copied and modified template file is "aldec.do", run it as:
# # vsim -c -do aldec.do
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "aldec.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated sim script
# source rivierapro_setup.tcl
# # Compile eda/sim_lib contents first
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# # Override the top-level name (so that elab is useful)
# set TOP_LEVEL_NAME top
# # Compile the standalone IP.
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# # Compile the user top-level
# vlog -sv2k5 ../../top.sv
# # Elaborate the design.
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog -sv2k5 <your compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# # Run the simulation
# #
# # Run the simulation.
# run
# # Report success to the shell
# #
# # Report success to the shell.
# exit -code 0
# # End of template
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If gbt_tx_frameclk_pll is one of several IP cores in your
# Quartus project, you can generate a simulation script
......@@ -73,7 +111,7 @@ if ![info exists QSYS_SIMDIR] {
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/altera/15.1/quartus/"
set QUARTUS_INSTALL_DIR "C:/altera/16.0/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
......
......@@ -12,41 +12,83 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 15.1 185 win32 2016.07.18.17:01:05
# ACDS 16.0 211 win32 2016.08.03.10:21:27
# ----------------------------------------
# ncsim - auto-generated simulation script
# ----------------------------------------
# This script can be used to simulate the following IP:
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# gbt_tx_frameclk_pll
# To create a top-level simulation script which compiles other
# IP, and manages other system issues, copy the following template
# and adapt it to your needs:
#
# # Start of template
# # If the copied and modified template file is "ncsim.sh", run it as:
# # ./ncsim.sh
# #
# # Do the file copy, dev_com and com steps
# source ncsim_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# # Compile the top level module
# ncvlog -sv "$QSYS_SIMDIR/../top.sv"
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "ncsim.sh", and modify text as directed.
#
# # Do the elaboration and sim steps
# # Override the top-level name
# # Override the user-defined sim options, so the simulation
# # runs forever (until $finish()).
# source ncsim_setup.sh \
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated files
# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
# # into the location from which you launch the simulator, or incorporate
# # into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# # - If necessary, specify USER_DEFINED_COMPILE_OPTIONS.
# #
# source <script generation output directory>/cadence/ncsim_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# ncvlog <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/cadence/ncsim_setup.sh \
# SKIP_FILE_COPY=1 \