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Commit 83cdd8ef authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[WR-dev] Added WB slave interface to the wrapper. Synthesis and PAR ok, does... 

[WR-dev] Added WB slave interface to the wrapper. Synthesis and PAR ok, does not meet timing. Not tested
parent 650cf6c0
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Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
View file @ 83cdd8ef
......@@ -29,7 +29,12 @@ module AddrDecoderWBSys(
input [31:0] DatAppSlaveBus_ib32,
input AckAppSlaveBus_i,
output reg StbAppSlaveBus_o
output reg StbAppSlaveBus_o,
//WR stuff
input [31:0] DatWrpcSlaveBus_ib32,
input AckWrpcSlaveBus_i,
output reg StbWrpcSlaveBus_o
);
localparam dly = 1;
......@@ -42,7 +47,8 @@ localparam c_SelNothing = 8'h0,
c_SelUniqueIdReader = 8'd3,
c_SelI2cWrProm = 8'd4,
c_SelSpiMaster = 8'd5,
c_SelAppSlaveBus = 8'd6;
c_SelAppSlaveBus = 8'd6,
c_SelWrPtpCore = 8'd7;
always @*
casez(Adr_ib22)
......@@ -50,7 +56,8 @@ always @*
22'b00000000000000000001??: SelectedModule_b8 = c_SelIoExpAndMux; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
22'b00000000000000000010??: SelectedModule_b8 = c_SelUniqueIdReader; // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
22'b00000000000000000011??: SelectedModule_b8 = c_SelI2cWrProm; // FROM 00_000C TO 00_000F (WB) == FROM 00_0030 TO 00_003C (VME) <- 4 regs (16B)
22'b0000000000000000010???: SelectedModule_b8 = c_SelSpiMaster; // FROM 00_0010 TO 00_0017 (WB) == FROM 00_0040 TO 00_005C (VME) <- 8 regs (32B)
22'b0000000000000000010???: SelectedModule_b8 = c_SelSpiMaster; // FROM 00_0010 TO 00_0017 (WB) == FROM 00_0040 TO 00_005C (VME) <- 8 regs (32B)
22'b000001????????????????: SelectedModule_b8 = c_SelWrPtpCore; // FROM 01_0000 TO 01_FFFF (WB) == FROM 04_0000 TO 07_FFFC (VME) <- 64K regs (256KB)
22'b1?????????????????????: SelectedModule_b8 = c_SelAppSlaveBus; // FROM 20_0000 TO 3F_FFFF (WB) == FROM 80_0000 TO FF_FFFC (VME) <- 2M regs (8MB)
default: SelectedModule_b8 = c_SelNothing;
endcase
......
Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
View file @ 83cdd8ef
......@@ -170,6 +170,11 @@ wire VmeGap_n; //need to be accessed from the I2C exp
wire WbAckI2cWrProm, WbStbI2cWrProm;
wire [31:0] WbDatI2cWrProm_b32;
reg Reset_rq;
//WR stuff
wire WbStbWrpcSlaveBus;
wire [31:0] WbDatWrpcSlaveBus_b32;
wire WbAckWrpcSlaveBus;
wire [31:0] WbAdr_b32;
//****************************
//Clocking
......@@ -274,7 +279,11 @@ AddrDecoderWBSys i_AddressDecoderWbSys(
//---
.DatI2cWrProm_ib32(WbDatI2cWrProm_b32),
.AckI2cWrProm_i(WbAckI2cWrProm),
.StbI2cWrProm_o(WbStbI2cWrProm));
.StbI2cWrProm_o(WbStbI2cWrProm),
.DatWrpcSlaveBus_ib32(WbDatWrpcSlaveBus_b32),
.AckWrpcSlaveBus_i(WbAckWrpcSlaveBus),
.StbWrpcSlaveBus_o(WbStbWrpcSlaveBus));
InterruptManagerWb #(
.g_FpgaVersion_b8(g_SystemVersion_b8),
......@@ -401,10 +410,10 @@ I2CMaster #(.g_CycleLenght(10'd256))
.Sda_ioz(WrPromSda_io));
//****************************
//WR PTP core Wrapper
//****************************
WrpcWrapper #(.g_simulation(0), .g_dpram_initf(""))
//****************************
//WR PTP core Wrapper
//****************************
WrpcWrapper #(.g_simulation(0), .g_dpram_initf(""))
i_WrpcWrapper
(
.clk_125m_i(GbitTrxClkRefR_ik),
......@@ -415,8 +424,23 @@ WrpcWrapper #(.g_simulation(0), .g_dpram_initf(""))
.plldac_din_o(PllDacDin_o),
.plldac_sclk_o(PllDacSclk_ok),
.wr_sfp_tx_o(EthSfpTx_o),
.wr_sfp_rx_i(EthSfpRx_i));
.wr_sfp_rx_i(EthSfpRx_i),
.wb_adr_i(WbAdr_b32),
.wb_dat_i(WbDatMoSi_b32),
.wb_dat_o(WbDatWrpcSlaveBus_b32),
.wb_sel_i(4'b1111),
.wb_we_i(WbWe),
.wb_cyc_i(WbCyc),
.wb_stb_i(WbStbWrpcSlaveBus),
.wb_ack_o(WbAckWrpcSlaveBus),
.wb_int_o(),
.wb_err_o(),
.wb_rty_o(),
.wb_stall_o()
);
assign WbAdr_b32[15:0] = WbAdr_b22[15:0];
assign WbAdr_b32[31:16] = 16'h0000;
//****************************
//SYS <=> APP Wishbone interface
......
Hdl/FpgaModules/SystemSpecific/WrpcWrapper.vhd
View file @ 83cdd8ef
......@@ -36,6 +36,7 @@ library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_altera_pkg.all;
use work.wishbone_pkg.all;
entity WrpcWrapper is
......@@ -69,7 +70,23 @@ entity WrpcWrapper is
---------------------------------------------------------------------------
wr_sfp_tx_o : out std_logic;
wr_sfp_rx_i : in std_logic);
wr_sfp_rx_i : in std_logic;
-------------------------------------------------------------------------
--External WB interface
-------------------------------------------------------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic);
end entity WrpcWrapper;
......@@ -139,6 +156,10 @@ architecture struct of WrpcWrapper is
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
-- External WB interface
signal wb_slave_out : t_wishbone_slave_out;
signal wb_slave_in : t_wishbone_slave_in;
begin -- architecture struct
-----------------------------------------------------------------------------
......@@ -268,36 +289,36 @@ begin -- architecture struct
phy_rx_enc_err_i => phy_rx_enc_err,
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen);
--phy_loopen_vec_o => phy_loopen_vec_o,
--phy_tx_prbs_sel_o => phy_tx_prbs_sel_o,
--phy_sfp_tx_fault_i => phy_sfp_tx_fault_i,
--phy_sfp_los_i => phy_sfp_los_i,
--phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
--led_act_o => led_act_o,
--led_link_o => led_link_o,
--scl_o => scl_o,
--scl_i => scl_i,
--sda_o => sda_o,
--sda_i => sda_i,
--sfp_scl_o => sfp_scl_o,
--sfp_scl_i => sfp_scl_i,
--sfp_sda_o => sfp_sda_o,
--sfp_sda_i => sfp_sda_i,
--sfp_det_i => sfp_det_i,
--btn1_i => btn1_i,
--btn2_i => btn2_i,
--spi_sclk_o => spi_sclk_o,
--spi_ncs_o => spi_ncs_o,
--spi_mosi_o => spi_mosi_o,
--spi_miso_i => spi_miso_i,
--uart_rxd_i => uart_rxd_i,
--uart_txd_o => uart_txd_o,
--owr_pwren_o => owr_pwren_o,
--owr_en_o => owr_en_o,
--owr_i => owr_i,
--slave_i => slave_i,
--slave_o => slave_o,
phy_loopen_o => phy_loopen,
--phy_loopen_vec_o => phy_loopen_vec_o,
--phy_tx_prbs_sel_o => phy_tx_prbs_sel_o,
--phy_sfp_tx_fault_i => phy_sfp_tx_fault_i,
--phy_sfp_los_i => phy_sfp_los_i,
--phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
--led_act_o => led_act_o,
--led_link_o => led_link_o,
--scl_o => scl_o,
--scl_i => scl_i,
--sda_o => sda_o,
--sda_i => sda_i,
--sfp_scl_o => sfp_scl_o,
--sfp_scl_i => sfp_scl_i,
--sfp_sda_o => sfp_sda_o,
--sfp_sda_i => sfp_sda_i,
--sfp_det_i => sfp_det_i,
--btn1_i => btn1_i,
--btn2_i => btn2_i,
--spi_sclk_o => spi_sclk_o,
--spi_ncs_o => spi_ncs_o,
--spi_mosi_o => spi_mosi_o,
--spi_miso_i => spi_miso_i,
--uart_rxd_i => uart_rxd_i,
--uart_txd_o => uart_txd_o,
--owr_pwren_o => owr_pwren_o,
--owr_en_o => owr_en_o,
--owr_i => owr_i,
slave_i => wb_slave_in,
slave_o => wb_slave_out);
--aux_master_o => aux_master_o,
--aux_master_i => aux_master_i,
--wrf_src_o => wrf_src_o,
......@@ -323,4 +344,20 @@ begin -- architecture struct
--rst_aux_n_o => rst_aux_n_o,
--link_ok_o => link_ok_o);
wb_slave_in.cyc <= wb_cyc_i;
wb_slave_in.stb <= wb_stb_i;
wb_slave_in.adr <= wb_adr_i;
wb_slave_in.sel <= wb_sel_i;
wb_slave_in.we <= wb_we_i;
wb_slave_in.dat <= wb_dat_i;
wb_ack_o <= wb_slave_out.ack;
wb_err_o <= wb_slave_out.err;
wb_rty_o <= wb_slave_out.rty;
wb_stall_o <= wb_slave_out.stall;
wb_int_o <= wb_slave_out.int;
wb_dat_o <= wb_slave_out.dat;
end architecture struct;
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