Commit 8d68e1d0 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev] exposed WR-Btrain FMC signals to top-level HDL file

parent 31e051cf
......@@ -160,6 +160,10 @@ module VfcHdApplication
input [207:0] WrBtrainRxData_i,
input WrBtrainRxValid_i,
output WrBtrainRxDreq_o,
//WR Btrain signals to FMC
output [31:0] WrBtrainBvalue_o,
output WrBtrainBvalueValid_o,
output WrBtrainBvalueUpdated_p1_o,
//WRPC timecode input
input WrpcTmTimeValid_i,
input [39:0] WrpcTmTai_i,
......@@ -315,7 +319,9 @@ i_WrBtrainWrapper (
.rx_dreq_o (WrBtrainRxDreq_o),
.rx_last_i (WrBtrainRxLast_i),
.Bvalue_o (),
.Bvalue_o (WrBtrainBvalue_o),
.BvalueValid_o (WrBtrainBvalueValid_o),
.BvalueUpdated_p1_o (WrBtrainBvalueUpdated_p1_o),
.wb_adr_i (WbSlaveAdr_ib25),
.wb_dat_i (WbSlaveDat_ib32),
......
......@@ -109,6 +109,7 @@ always @* begin
Dat_ob32 <= #dly DatWrpcSlaveBus_ib32;
Ack_o <= #dly AckWrpcSlaveBus_i;
end
default:;
endcase
end
......
......@@ -159,7 +159,7 @@ module VfcHdSystem
wire VmeAccess, VmeDtAck_n;
wire [7:1] VmeIrq_nb7;
reg [1:0] ResetWb_xd2 = 2'h0;
//reg [1:0] ResetWb_xd2 = 2'h0;
wire WbCyc, WbStb, WbWe, WbAck;
wire [21:0] WbAdr_b22;
wire [31:0] WbDatMiSo_b32, WbDatMoSi_b32;
......@@ -167,7 +167,7 @@ wire IntEnable, IntModeRoRa, IntSourceToRead, NewIntRequest;
wire [2:0] IntLevel_b3;
wire [7:0] IntVector_b8;
wire [31:0] IntRequestBus_ab32;
reg [1:0] VmeSysReset_d2 = 2'h0;
//reg [1:0] VmeSysReset_d2 = 2'h0;
wire WbAckIntManager, WbStbIntManager;
wire [31:0] WbDatMiSoIntManager_b32;
wire WbAckSpiMaster, WbStbSpiMaster;
......
......@@ -88,10 +88,10 @@ module VfcHdTop
output VAdcDin_o,
output VAdcCs_o,
output VAdcSclk_ok,
/* -----\/----- EXCLUDED -----\/-----
//FMC connector
inout [33:0]FmcLaP_iob34,
inout [33:0]FmcLaN_iob34,
output [33:0]FmcLaP_iob34,
output [33:0]FmcLaN_iob34,
/* -----\/----- EXCLUDED -----\/-----
inout [23:0]FmcHaP_iob24,
inout [23:0]FmcHaN_iob24,
inout [21:0]FmcHbP_iob22,
......@@ -212,6 +212,11 @@ wire WrpcTmTimeValid;
wire [39:0] WrpcTmTai;
wire [27:0] WrpcTmCycles;
wire WrpcSysClk_k;
wire WrpcLedLink;
wire WrpcLedAct;
wire [31:0]WrBtrainBvalue;
wire WrBtrainBvalueValid;
wire WrBtrainBvalueUpdated;
//@@@@@@@@@@@@@@@@@@@
......@@ -339,8 +344,8 @@ VfcHdSystem i_VfcHdSystem(
.WrpcTmTai_o(WrpcTmTai),
.WrpcTmCycles_o(WrpcTmCycles),
// WRPC status LEDs
.WrpcLedLink_o(),
.WrpcLedAct_o(),
.WrpcLedLink_o(WrpcLedLink),
.WrpcLedAct_o(WrpcLedAct),
.WrpcSysClk_ok(WrpcSysClk_k));
......@@ -479,11 +484,94 @@ VfcHdApplication i_VfcHdApplication
.WrBtrainRxData_i(WrBtrainRxData),
.WrBtrainRxValid_i(WrBtrainRxValid),
.WrBtrainRxDreq_o(WrBtrainRxDreq),
//WR Btrain signals to FMC
.WrBtrainBvalue_o(WrBtrainBvalue),
.WrBtrainBvalueValid_o(WrBtrainBvalueValid),
.WrBtrainBvalueUpdated_p1_o(WrBtrainBvalueUpdated),
//WRPC timecode input
.WrpcTmTimeValid_i(WrpcTmTimeValid),
.WrpcTmTai_i(WrpcTmTai),
.WrpcTmCycles_i(WrpcTmCycles),
.WrpcSysClk_ik(WrpcSysClk_k));
//@@@@@@@@@@@@@@@@@@@
//FMC signal mapping
//@@@@@@@@@@@@@@@@@@@
assign FmcLaP_iob34[0] = WrBtrainBvalue[31];
assign FmcLaP_iob34[2] = WrBtrainBvalue[30];
assign FmcLaN_iob34[0] = WrBtrainBvalue[29];
assign FmcLaN_iob34[2] = WrBtrainBvalue[28];
assign FmcLaP_iob34[3] = WrBtrainBvalue[27];
assign FmcLaP_iob34[4] = WrBtrainBvalue[26];
assign FmcLaN_iob34[3] = WrBtrainBvalue[25];
assign FmcLaN_iob34[4] = WrBtrainBvalue[24];
assign FmcLaP_iob34[8] = WrBtrainBvalue[23];
assign FmcLaP_iob34[7] = WrBtrainBvalue[22];
assign FmcLaN_iob34[8] = WrBtrainBvalue[21];
assign FmcLaN_iob34[7] = WrBtrainBvalue[20];
assign FmcLaP_iob34[12] = WrBtrainBvalue[19];
assign FmcLaP_iob34[11] = WrBtrainBvalue[18];
assign FmcLaN_iob34[12] = WrBtrainBvalue[17];
assign FmcLaN_iob34[11] = WrBtrainBvalue[16];
assign FmcLaP_iob34[16] = WrBtrainBvalue[15];
assign FmcLaP_iob34[15] = WrBtrainBvalue[14];
assign FmcLaN_iob34[16] = WrBtrainBvalue[13];
assign FmcLaN_iob34[15] = WrBtrainBvalue[12];
assign FmcLaP_iob34[20] = WrBtrainBvalue[11];
assign FmcLaP_iob34[19] = WrBtrainBvalue[10];
assign FmcLaN_iob34[20] = WrBtrainBvalue[9];
assign FmcLaN_iob34[19] = WrBtrainBvalue[8];
assign FmcLaP_iob34[22] = WrBtrainBvalue[7];
assign FmcLaP_iob34[21] = WrBtrainBvalue[6];
assign FmcLaN_iob34[22] = WrBtrainBvalue[5];
assign FmcLaN_iob34[21] = WrBtrainBvalue[4];
assign FmcLaP_iob34[25] = WrBtrainBvalue[3];
assign FmcLaP_iob34[24] = WrBtrainBvalue[2];
assign FmcLaN_iob34[25] = WrBtrainBvalue[1];
assign FmcLaN_iob34[24] = WrBtrainBvalue[0];
assign FmcLaP_iob34[28] = WrBtrainBvalueValid;
assign FmcLaP_iob34[29] = WrBtrainBvalueUpdated;
assign FmcLaN_iob34[28] = WrpcLedAct;
assign FmcLaN_iob34[29] = WrpcLedLink;
assign FmcLaP_iob34[31] = WrpcTmTimeValid;
assign FmcLaP_iob34[30] = 1'b0; // BT_UP_o
assign FmcLaN_iob34[31] = 1'b0; // BT_DN_o
// unused, driven to ground
assign FmcLaP_iob34[1] = 1'b0;
assign FmcLaN_iob34[1] = 1'b0;
assign FmcLaP_iob34[5] = 1'b0;
assign FmcLaN_iob34[5] = 1'b0;
assign FmcLaP_iob34[6] = 1'b0;
assign FmcLaN_iob34[6] = 1'b0;
assign FmcLaP_iob34[9] = 1'b0;
assign FmcLaN_iob34[9] = 1'b0;
assign FmcLaP_iob34[10] = 1'b0;
assign FmcLaN_iob34[10] = 1'b0;
assign FmcLaP_iob34[13] = 1'b0;
assign FmcLaN_iob34[13] = 1'b0;
assign FmcLaP_iob34[14] = 1'b0;
assign FmcLaN_iob34[14] = 1'b0;
assign FmcLaP_iob34[17] = 1'b0;
assign FmcLaN_iob34[17] = 1'b0;
assign FmcLaP_iob34[18] = 1'b0;
assign FmcLaN_iob34[18] = 1'b0;
assign FmcLaP_iob34[23] = 1'b0;
assign FmcLaN_iob34[23] = 1'b0;
assign FmcLaP_iob34[26] = 1'b0;
assign FmcLaN_iob34[26] = 1'b0;
assign FmcLaP_iob34[27] = 1'b0;
assign FmcLaN_iob34[27] = 1'b0;
assign FmcLaN_iob34[30] = 1'b0;
assign FmcLaP_iob34[32] = 1'b0;
assign FmcLaN_iob34[32] = 1'b0;
assign FmcLaP_iob34[33] = 1'b0;
assign FmcLaN_iob34[33] = 1'b0;
endmodule
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