Commit 9b851188 authored by unknown's avatar unknown
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save

parent 3a8c6a9d
......@@ -48,7 +48,7 @@ module I2cExpAndMuxMaster
output reg [7:0] ByteOut_ob8,
output reg AckError_op,
// IO Expanders parameters:
input [2:0] IoExpAddr_i,
input [2:0] IoExpAddr_ib3,
input [1:0] IoExpRegAddr_ib2,
input [7:0] IoExpData_ib8,
// I2C Mux parameters:
......@@ -57,12 +57,8 @@ module I2cExpAndMuxMaster
// FIFO access programming interface:
output FifoFull_o,
output FifoEmpty_o,
input [10:0] FifoCommand_ib11,
input FifoCommandWr_i,
output reg FifoWriteDone_op,
output reg FifoWriteAck_o,
output reg FifoReadDone_op,
output reg [7:0] FifoByteRead_ob8,
input [10:0] FifoCommand_ib11,
//==== I2C Bus ====\\
inout Scl_ioz,
inout Sda_ioz
......@@ -89,7 +85,7 @@ localparam s_Idle = 4'h0,
localparam c_IoExpWriteSeq = 3'd0,
c_IoExpReadSeq = 3'd1,
c_I2cMuxIntReadSeq = 3'd2,
c_I2cMuxEnChSeq = 3'd3,
c_I2cMuxEnChSeq = 3'd3,
c_FifoSeq = 3'd4;
// Commands:
localparam c_SendStartBit = 3'd1,
......@@ -120,7 +116,8 @@ reg [7:0] IoExpData_qb8;
reg [10:0] IoExpWriteSeq_b11, IoExpReadSeq_b11;
reg I2cMuxAddress_q;
reg [1:0] I2cMuxChannel_qb2;
reg [10:0] I2cMuxReadSeq_b11, I2cMuxEnChSeq_b11;
reg [10:0] I2cMuxReadSeq_b11, I2cMuxEnChSeq_b11;
reg [3:0] CommandPointer_c4;
//======================================= User Logic =======================================\\
......@@ -139,35 +136,38 @@ always @(posedge Clk_ik)
end
// Writing a value in a register of one IO expander
always @(posedge Clk_ik) case(CommandPointer_b4)
always @(posedge Clk_ik) case(CommandPointer_c4)
4'd0: IoExpWriteSeq_b11 <= #1 {c_SendStartBit, 8'h0};
4'd1: IoExpWriteSeq_b11 <= #1 {c_SendByte, 4'b0100, IoExpAddr_qb3, 1'b0}; //Comment: Selection of the Slave in write mode
4'd2: IoExpWriteSeq_b11 <= #1 {c_SendByte, 6'b0, IoExpRegAddr_qb2}; //Comment: Writing the Register address
4'd3: IoExpWriteSeq_b11 <= #1 {c_SendByte, IoExpData_qb8}; //Comment: Writing the Register Value
4'd4: IoExpWriteSeq_b11 <= #1 {c_SendStopBit, 8'h0};
default: IoExpWriteSeq_b11 <= #1 {c_GoToIdle, 8'h0};
endcase
// Reading a value from a register of one IO expander
always @(posedge Clk_ik) case(CommandPointer_b4)
always @(posedge Clk_ik) case(CommandPointer_c4)
4'd0: IoExpReadSeq_b11 <= #1 {c_SendStartBit, 8'h0};
4'd1: IoExpReadSeq_b11 <= #1 {c_SendByte, 4'b0100, IoExpAddr_qb3, 1'b0}; //Comment: Selection of the Slave in write mode
4'd2: IoExpReadSeq_b11 <= #1 {c_SendByte, 6'b0, IoExpRegAddr_qb2}; //Comment: Writing the Register address
4'd3: IoExpReadSeq_b11 <= #1 {c_SendStartBit, 8'h0}; //Comment: Repeated start (new cycle)
4'd4: IoExpReadSeq_b11 <= #1 {c_SendByte, 4'b0100, IoExpAddr_qb3, 1'b1}; //Comment: Selection of the Slave in read mode
4'd5: IoExpReadSeq_b11 <= #1 {c_GetByte, 8h1}; //Comment: Read of the last Byte (single read)
4'd5: IoExpReadSeq_b11 <= #1 {c_GetByte, 8'h1}; //Comment: Read of the last Byte (single read)
4'd6: IoExpReadSeq_b11 <= #1 {c_SendStopBit, 8'h0};
default: IoExpReadSeq_b11 <= #1 {c_GoToIdle, 8'h0};
endcase
// Reading the value of the interrupt and configuration status of one I2C mux
always @(posedge Clk_ik) case(CommandPointer_b4)
always @(posedge Clk_ik) case(CommandPointer_c4)
4'd0: I2cMuxReadSeq_b11 = {c_SendStartBit, 8'h0};
4'd1: I2cMuxReadSeq_b11 = {c_SendByte, 6'h38, I2cMuxAddress_q, 1'b1}; //Comment: Selection of the Slave in read mode
4'd2: I2cMuxReadSeq_b11 = {c_GetByte, 8h1}; //Comment: Read of the last Byte (single read)
4'd2: I2cMuxReadSeq_b11 = {c_GetByte, 8'h1}; //Comment: Read of the last Byte (single read)
4'd3: I2cMuxReadSeq_b11 = {c_SendStopBit, 8'h0};
default: I2cMuxReadSeq_b11 = {c_GoToIdle, 8'h0};
endcase
// Enabling one channel of a I2C mux (and disabling all the others)
always @(posedge Clk_ik) case(CommandPointer_b4)
always @(posedge Clk_ik) case(CommandPointer_c4)
4'd0: I2cMuxEnChSeq_b11 = {c_SendStartBit, 8'h0};
4'd1: I2cMuxEnChSeq_b11 = {c_SendByte, 6'h38, ~I2cMuxAddress_q, 1'b0}; //Comment: Selection of the other Slave in Write mode
4'd2: I2cMuxEnChSeq_b11 = {c_SendByte, 5'b0, 3'b0}; //Comment: Disabling all channels
......@@ -177,6 +177,7 @@ always @(posedge Clk_ik) case(CommandPointer_b4)
4'd6: I2cMuxEnChSeq_b11 = {c_SendByte, 5'b0, 1'b1, I2cMuxChannel_qb2}; //Comment: Enabling the desired channel
4'd7: I2cMuxEnChSeq_b11 = {c_SendStopBit, 8'h0};
default: I2cMuxEnChSeq_b11 = {c_GoToIdle, 8'h0};
endcase
// User custom sequence (always to be closed by a back to idle command!)
generic_fifo_dc_gray #(.dw(11), .aw(4))
......@@ -205,62 +206,52 @@ always @* begin
s_StartExecution: if (Command_b3 == c_SendStartBit) NextState_ab4 = s_StartSda1;
else if (Command_b3 == c_SendByte) NextState_ab4 = s_SendScl0;
else if (Command_b3 == c_GetByte) NextState_ab4 = s_GetScl0;
else if (Command_b3 == c_SendStopBit) NextState_ab4 = s_StopSda0,
else if (Command_b3 == c_SendStopBit) NextState_ab4 = s_StopSda0;
else if (Command_b3 == c_GoToIdle) NextState_ab4 = s_Idle;
// Start bit sequence
s_StartSda1: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_StartScl1;
s_StartScl1: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_StartSda0;
s_StartSda0: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_StartScl0;
s_StartScl0: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_FetchCommand;
s_StartSda1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StartScl1;
s_StartScl1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StartSda0;
s_StartSda0: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StartScl0;
s_StartScl0: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_FetchCommand;
// Byte sending sequence
s_SendScl0: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = (BitCounter_c4==4'd9) ? s_FetchCommand : s_SendScl1;
s_SendScl1: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_SendScl0;
s_SendScl0: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = (BitCounter_c4==4'd9) ? s_FetchCommand : s_SendScl1;
s_SendScl1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_SendScl0;
// Byte getting sequence
s_GetScl0 : if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = (BitCounter_c4==4'd9) ? s_FetchCommand : s_GetScl1;
s_GetScl1 : if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_GetScl0;
s_GetScl0 : if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = (BitCounter_c4==4'd9) ? s_FetchCommand : s_GetScl1;
s_GetScl1 : if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_GetScl0;
// Stop bit sequence
s_StopSda0: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_StopScl1;
s_StopScl1: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_StopSda1;
s_StopSda1: if (SclCounter_c10==g_SclHalfPeriod) NextState_ab4 = s_FetchCommand;
s_StopSda0: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StopScl1;
s_StopScl1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_StopSda1;
s_StopSda1: if (SclCounter_c10 == g_SclHalfPeriod) NextState_ab4 = s_FetchCommand;
// Protection from bad state condition
default: NextState_ab4 = s_Idle;
endcase
end
always @(posedge Clk_ik) begin
// Default assignments
Busy_o <= #1 NextState_ab4 != s_Idle;
IoExpWrOn_oq <= #1 Busy_o && ActiveSequence_b3 == c_IoExpWriteSeq;
IoExpRdOn_oq <= #1 Busy_o && ActiveSequence_b3 == c_IoExpReadSeq;
I2cEnChOn_oq <= #1 Busy_o && ActiveSequence_b3 == c_I2cMuxIntReadSeq;
I2cMuxRdIntOn_oq <= #1 Busy_o && ActiveSequence_b3 == c_I2cMuxEnChSeq;
FifoAccessOn_oq <= #1 Busy_o && ActiveSequence_b3 == c_FifoSeq;
// Default assignments
SclOe_e <= #1 1'b0;
SdaOe_e <= #1 1'b0;
I2cMuxWriteDone_op <= #1 1'b0;
I2cMuxReadDone_op <= #1 1'b0;
IoExpWriteDone_op <= #1 1'b0;
IoExpReadDone_op <= #1 1'b0;
FifoWriteDone_op <= #1 1'b0;
FifoReadDone_op <= #1 1'b0;
FifoRead <= #1 1'b0;
NewByteRead_op <= #1 1'b0;
AckError_op <= #1 1'b0;
AckError_op <= #1 1'b0;
if (NextState_ab4 == s_Idle) begin
Busy_o <= #1 1'b0;
IoExpWrOn_oq <= #1 1'b0;
IoExpRdOn_oq <= #1 1'b0;
I2cEnChOn_oq <= #1 1'b0;
I2cMuxRdIntOn_oq <= #1 1'b0;
FifoAccessOn_oq <= #1 1'b0;
end
// Reset conditions (if different from default)
if (Rst_irq) begin
BitCounter_c4 <= #1 4'b0;
SclCounter_c10 <= #1 10'b0;
I2CAck <= #1 1'b0;
ShReg_b8 <= #1 8'b0;
Command_b3 <= #1 3'b0;
I2cMuxWriteAck_o <= #1 1'b0;
I2cMuxByteRead_ob8 <= #1 8'b0;
IoExpWriteAck_o <= #1 1'b0;
IoExpByteRead_ob8 <= #1 8'b0;
FifoWriteAck_o <= #1 1'b0;
FifoByteRead_ob8 <= #1 8'b0;
Command_b3 <= #1 3'b0;
Busy_o <= #1 1'b1;
CommandPointer_b4 <= #1 4'h0;
CommandPointer_c4 <= #1 4'h0;
ActiveSequence_b3 <= #1 3'b0;
IoExpWrOn_oq <= #1 1'b0;
IoExpRdOn_oq <= #1 1'b0;
......@@ -268,22 +259,42 @@ always @(posedge Clk_ik) begin
I2cMuxRdIntOn_oq <= #1 1'b0;
FifoAccessOn_oq <= #1 1'b0;
ByteOut_ob8 <= #1 8'b0;
Busy_o <= #1 1'b0;
IoExpWrOn_oq <= #1 1'b0;
IoExpRdOn_oq <= #1 1'b0;
I2cEnChOn_oq <= #1 1'b0;
I2cMuxRdIntOn_oq <= #1 1'b0;
FifoAccessOn_oq <= #1 1'b0;
end else case(State_qb4)
// Waiting for a request
s_Idle : begin
CommandPointer_b4 <= #1 4'h0;
if (IoExpWrReq_i) ActiveSequence_b3 <= #1 c_IoExpWriteSeq;
else if (IoExpRdReq_i) ActiveSequence_b3 <= #1 c_IoExpReadSeq;
else if (I2cMuxIntRdReq_i) ActiveSequence_b3 <= #1 c_I2cMuxIntReadSeq;
else if (I2cMuxEnChReq_i) ActiveSequence_b3 <= #1 c_I2cMuxEnChSeq;
else if (FifoAccessReq_i) ActiveSequence_b3 <= #1 c_FifoSeq;
CommandPointer_c4 <= #1 4'h0;
if (NextState_ab4 != s_Idle) begin
Busy_o <= #1 1'b1;
if (IoExpWrReq_i) begin
ActiveSequence_b3 <= #1 c_IoExpWriteSeq;
IoExpWrOn_oq <= #1 1'b1;
end else if (IoExpRdReq_i) begin
ActiveSequence_b3 <= #1 c_IoExpReadSeq;
IoExpRdOn_oq <= #1 1'b1;
end else if (I2cMuxIntRdReq_i) begin
ActiveSequence_b3 <= #1 c_I2cMuxIntReadSeq;
I2cEnChOn_oq <= #1 1'b1;
end else if (I2cMuxEnChReq_i) begin
ActiveSequence_b3 <= #1 c_I2cMuxEnChSeq;
I2cMuxRdIntOn_oq <= #1 1'b1;
end else if (FifoAccessReq_i) begin
ActiveSequence_b3 <= #1 c_FifoSeq;
FifoAccessOn_oq <= #1 1'b0;
end
end
end
// Fetching and decoding the command
s_FetchCommand: begin
NewByteRead_op <= #1 Command_b3 == c_GetByte;
ByteOut_ob8 <= #1 ShReg_b8;
AckError_op <= #1 Command_b3 == c_SendByte && I2CAck;
CommandPointer_b4 <= #1 CommandPointer_b4 + 1'b1;
CommandPointer_c4 <= #1 CommandPointer_c4 + 1'b1;
FifoRead <= #1 ~FifoEmpty_o && ActiveSequence_b3==c_FifoSeq;
case (ActiveSequence_b3)
c_IoExpWriteSeq: {Command_b3, ShReg_b8} <= #1 IoExpWriteSeq_b11;
......@@ -381,11 +392,7 @@ always @(posedge Clk_ik) begin
// Protection from bad state condition
default: begin
SclOe_e <= #1 1'b0;
SdaOe_e <= #1 1'b0;
BitCounter_c4 <= #1 'h0;
SclCounter_c10 <= #1 'h0;
I2CAck <= #1 CommandReg_qb32[0];
ShReg_b8 <= #1 CommandReg_qb32[7:0];
SdaOe_e <= #1 1'b0;
end
endcase
end
......
[ViewState]
Mode=
Vid=
FolderType=Generic
......@@ -82,19 +82,12 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
fmc_test_wrapper
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VfcHdSystem
Top level modules:
VfcHdSystem
} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/VfcHd_v2_0.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/VfcHd_v2_0.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module PeriodCounter
-- Compiling module VfcHd_v2_0
Top level modules:
PeriodCounter
VfcHd_v2_0
} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......@@ -103,19 +96,19 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
AddrDecoderWBApp
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/VfcHd_v2_0.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/VfcHd_v2_0.v
} {} {}} E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VfcHd_v2_0
-- Compiling module PeriodCounter
Top level modules:
VfcHd_v2_0
PeriodCounter
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module InterruptManagerWb
-- Compiling module VfcHdSystem
Top level modules:
InterruptManagerWb
VfcHdSystem
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/MAX5483.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/MAX5483.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......@@ -124,33 +117,33 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
MAX5483
} {} {}} E:/VFC-HD/Hdl/Simulation/BasicVmeAccesses/tb_VfcBasicAccess.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/BasicVmeAccesses/tb_VfcBasicAccess.sv
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module tb_VfcBasicAccess
-- Compiling module InterruptManagerWb
Top level modules:
tb_VfcBasicAccess
InterruptManagerWb
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/VmeBusModule.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/Models/VmeBusModule.sv
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VmeInterfaceWb
-- Compiling module VmeBusModule
Top level modules:
VmeInterfaceWb
VmeBusModule
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/VmeBusModule.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/Models/VmeBusModule.sv
} {} {}} E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module VmeBusModule
-- Compiling module VmeInterfaceWb
Top level modules:
VmeBusModule
VmeInterfaceWb
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v
} {} {}} E:/VFC-HD/Hdl/Simulation/BasicVmeAccesses/tb_VfcBasicAccess.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/BasicVmeAccesses/tb_VfcBasicAccess.sv
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module generic_dpram
-- Compiling module tb_VfcBasicAccess
Top level modules:
generic_dpram
tb_VfcBasicAccess
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......@@ -159,12 +152,19 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
Generic4InputRegs
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module Iir1stOrderLp
-- Compiling module generic_dpram
Top level modules:
Iir1stOrderLp
generic_dpram
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/sn74vmeh22501.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/sn74vmeh22501.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module sn74vmeh22501
Top level modules:
sn74vmeh22501
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/ivt3205c25mhz.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/ivt3205c25mhz.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......@@ -173,12 +173,12 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
ivt3205c25mhz
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/sn74vmeh22501.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/sn74vmeh22501.v
} {} {}} E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module sn74vmeh22501
-- Compiling module Iir1stOrderLp
Top level modules:
sn74vmeh22501
Iir1stOrderLp
} {} {}} E:/VFC-HD/Hdl/Simulation/Models/si57x.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/si57x.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......
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