Commit 9dc0ee45 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev] Merge branch 'be-bi-master'. Tested, works.

parents 20dc4ac3 cbdabb7f
*.bak *.bak
*.pyc *.pyc
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.asm64 /Hdl/Simulation/*Project/modelsim/project/*
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.rw64 !/Hdl/Simulation/*Project/modelsim/project/*.mpf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.asm64 /Hdl/Synthesis/*/QuartusPrj/*
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.rw64 !/Hdl/Synthesis/*/QuartusPrj/*.qpf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.asm64 !/Hdl/Synthesis/*/QuartusPrj/*.qsf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.rw64 /Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.asm64 /Doc/AlteraDocuments/EMIF_Altera.pdf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.rw64 /Doc/AlteraDocuments/an520.pdf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.asm64 /Doc/AlteraDocuments/arriav_handbook.pdf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.rw64 /Doc/AlteraDocuments/ddr3AlteraDesign.pdf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.asm64 /Doc/Datasheets/8Gb_DDR3L.pdf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.rw64 /Doc/VfcHd_UserGuides/BI-VFC-HD-V2_0.pdf
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.asm64 /Hw/Assembly data/
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.rw64 /Hw/EDA-03133-V2-0_project.Annotation
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.asm64 /Hw/EDA-03133-V2-0_project.PrjPCB
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.rw64 /Hw/EDA-03133-V2-0_project.PrjPCBStructure
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.asm64 /Hw/Manufacturing/EDA-03133-V2_mfg.cam
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.rw64 /Hw/PCB-Layout/
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.asm64 /Hw/Schematics/
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
Doc/AlteraDocuments/EMIF_Altera.pdf
Doc/AlteraDocuments/an520.pdf
Doc/AlteraDocuments/arriav_handbook.pdf
Doc/AlteraDocuments/ddr3AlteraDesign.pdf
Doc/Datasheets/8Gb_DDR3L.pdf
Hw/Assembly data/
Hw/EDA-03133-V2-0_project.Annotation
Hw/EDA-03133-V2-0_project.PrjPCB
Hw/EDA-03133-V2-0_project.PrjPCBStructure
Hw/Manufacturing/EDA-03133-V2_mfg.cam
Hw/PCB-Layout/
Hw/Schematics/
Hdl/Simulation/BasicVmeAccesses/modelsim/project/BasicVmeAccesses.cr.mti
...@@ -63,6 +63,7 @@ initial begin ...@@ -63,6 +63,7 @@ initial begin
@(posedge Clk125MHz_kq); @(posedge Clk125MHz_kq);
ControlReg1_q = 1'b1; ControlReg1_q = 1'b1;
$display($time, " -> Trigger"); $display($time, " -> Trigger");
repeat(10000)@(posedge Clk125MHz_kq);
#50000 #50000
$display($time, " -> Simulation Stop"); $display($time, " -> Simulation Stop");
$stop; $stop;
......
`timescale 1ns/100ps `timescale 1ns/100ps
module VfcHdApplication module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'hb2, #(parameter g_ApplicationVersion_b8 = 8'hC5,
g_ApplicationReleaseDay_b8 = 8'h28, g_ApplicationReleaseDay_b8 = 8'h17,
g_ApplicationReleaseMonth_b8 = 8'h04, g_ApplicationReleaseMonth_b8 = 8'h07,
g_ApplicationReleaseYear_b8 = 8'h16) g_ApplicationReleaseYear_b8 = 8'h16)
( (
//@@@@@@@@@@@@@@@@@@@@@@@@@ //@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections //External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@ //@@@@@@@@@@@@@@@@@@@@@@@@@
/* -----\/----- EXCLUDED -----\/----- input BstSfpRx_i, // Comment: Differential signal
input BstSfpRx_i, //Differential output BstSfpTx_o, // Comment: Differential signal
output BstSfpTx_o, //Differential input EthSfpRx_i, // Comment: Differential signal
input EthSfpRx_i, //Differential output EthSfpTx_o, // Comment: Differential signal
output EthSfpTx_o, //Differential // SFP Gbit:
//SFP Gbit input [ 4:1] AppSfpRx_ib4, // Comment: Differential signal
input [4:1] AppSfpRx_ib4, //Differential output [ 4:1] AppSfpTx_ob4, // Comment: Differential signal
output [4:1] AppSfpTx_ob4, //Differential // DDR3 SO-DIMM:
//DDR3 SO-DIMM output [ 2:0] DdrBa_ob3,
output [2:0] DdrBa_ob3, output [ 7:0] DdrDm_ob8,
output [7:0] DdrDm_ob8, inout [ 7:0] DdrDqs_iob8, // Comment: Differential signal
inout [7:0] DdrDqs_iob8, //differential signals inout [63:0] DdrDq_iob64,
inout [63:0] DdrDq_iob64,
output [15:0] DdrA_ob16, output [15:0] DdrA_ob16,
output [1:0] DdrCk_okb2, //differential signals output [ 1:0] DdrCk_okb2, // Comment: Differential signal
output [1:0] DdrCkE_ohb2, output [ 1:0] DdrCkE_ohb2,
output DdrReset_orn, output DdrReset_orn,
output DdrRas_on, output DdrRas_on,
output DdrCas_on, output DdrCas_on,
output DdrWe_on, output DdrWe_on,
output [1:0] DdrCs_onb2, output [ 1:0] DdrCs_onb2,
output [1:0] DdrOdt_ob2, output [ 1:0] DdrOdt_ob2,
input DdrTempEvent_in, input DdrTempEvent_in,
output DdrI2cScl_ok, output DdrI2cScl_ok,
inout DdrI2cSda_io, inout DdrI2cSda_io,
//TestIo // TestIo:
inout TestIo1_io, inout TestIo1_io,
inout TestIo2_io, inout TestIo2_io,
//FMC connector // FMC connector:
inout [33:0]FmcLaP_iob34, output VfmcEnableN_oen,
inout [33:0]FmcLaN_iob34, inout [33:0] FmcLaP_iob34,
inout [23:0]FmcHaP_iob24, inout [33:0] FmcLaN_iob34,
inout [23:0]FmcHaN_iob24, inout [23:0] FmcHaP_iob24,
inout [21:0]FmcHbP_iob22, inout [23:0] FmcHaN_iob24,
inout [21:0]FmcHbN_iob22, inout [21:0] FmcHbP_iob22,
input FmcPrsntM2C_in, inout [21:0] FmcHbN_iob22,
output FmcTck_ok, input FmcPrsntM2C_in,
output FmcTms_o, output FmcTck_ok,
output FmcTdi_o, output FmcTms_o,
input FmcTdo_i, output FmcTdi_o,
output FmcTrstL_orn, input FmcTdo_i,
inout FmcScl_iok, output FmcTrstL_orn,
inout FmcSda_io, inout FmcScl_iok,
input FmcPgM2C_in, inout FmcSda_io,
output FmcPgC2M_on, input FmcPgM2C_in,
input FmcClk0M2CCmos_ik, output FmcPgC2M_on,
input FmcClk1M2CCmos_ik, input FmcClk0M2CCmos_ik,
inout FmcClk2Bidir_iok, //differential signal input FmcClk1M2CCmos_ik,
inout FmcClk3Bidir_iok, //differential signal inout FmcClk2Bidir_iok, // Comment: Differential signal
input FmcClkDir_i, inout FmcClk3Bidir_iok, // Comment: Differential signal
output [9:0] FmcDpC2M_ob10, //diff output input FmcClkDir_i,
input [9:0] FmcDpM2C_ib10, output [ 9:0] FmcDpC2M_ob10, // Comment: Differential signal
input FmcGbtClk0M2CLeft_ik, //differential signal input [ 9:0] FmcDpM2C_ib10,
input FmcGbtClk1M2CLeft_ik, //differential signal input FmcGbtClk0M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk0M2CRight_ik, //differential signal input FmcGbtClk1M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk1M2CRight_ik, //differential signal input FmcGbtClk0M2CRight_ik, // Comment: Differential signal
-----/\----- EXCLUDED -----/\----- */ input FmcGbtClk1M2CRight_ik, // Comment: Differential signal
//Clock sources and control // Clock sources and control:
output OeSi57x_oe, output OeSi57x_oe,
/* -----\/----- EXCLUDED -----\/----- input Si57xClk_ik,
input Si57xClk_ik, output ClkFb_ok,
output ClkFb_ok, input ClkFb_ik,
input ClkFb_ik, input Clk20VCOx_ik,
input Clk20VCOx_ik, output PllDac20Sync_o,
output PllDac20Sync_o, output PllDac25Sync_o,
output PllDac25Sync_o, output PllDacSclk_ok,
output PllDacSclk_ok, output PllDacDin_o,
output PllDacDin_o, output PllRefScl_ok,
inout PllRefSda_io, inout PllRefSda_io,
output PllRefScl_ok, input PllRefInt_i,
inout PllRefInt_i, output PllSourceMuxOut_ok,
output PllSourceMuxOut_ok, input PllRefClkOut_ik, // Comment: Differential reference for the Gbit lines
input PllRefClkOut_ik, //Differential reference for the Gbit lines input GbitTrxClkRefR_ik, // Comment: Differential reference for the Gbit lines ~125MHz
-----/\----- EXCLUDED -----/\----- */ // SW1:
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines ~125MHz input [ 1:0] Switch_ib2,
/* -----\/----- EXCLUDED -----\/----- // P2 RTM:
//SW1 inout [19:0] P2DataP_iob20, //Comment: The 0 is a clock capable input
input [1:0] Switch_ib2, inout [19:0] P2DataN_iob20,
//P2 RTM // P0 Timing:
inout [19:0] P2DataP_iob20, //the 0 is a clock capable input input [ 7:0] P0HwHighByte_ib8,
inout [19:0] P2DataN_iob20, input [ 7:0] P0HwLowByte_ib8,
//P0 Timing output DaisyChain1Cntrl_o,
input [7:0] P0HwHighByte_ib8, output DaisyChain2Cntrl_o,
input [7:0] P0HwLowByte_ib8, input VmeP0BunchClk_ik,
output DaisyChain1Cntrl_o, input VmeP0Tclk_ik,
output DaisyChain2Cntrl_o, // GPIO:
input VmeP0BunchClk_ik, inout [ 4:1] GpIo_iob4,
input VmeP0Tclk_ik, // Specials:
//GPIO input PushButtonN_in,
inout [4:1] GpIo_iob4,
//Specials
input PushButtonN_in,
-----/\----- EXCLUDED -----/\----- */
//@@@@@@@@@@@@@@@@@@@@@@@@@ //@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface //System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@ //@@@@@@@@@@@@@@@@@@@@@@@@@
//Reset // Reset:
input Reset_irqp, //Reset Synchronous with the WbClk_ik input Reset_irqp, // Comment: Reset Synchronous with the WbClk_ik
/* -----\/----- EXCLUDED -----\/----- output ResetRequest_oqp, // Comment: Request to issue a reset
output ResetRequest_oqp, //Request to issue a reset // WishBone:
-----/\----- EXCLUDED -----/\----- */ output WbClk_ok,
//WishBone input WbSlaveCyc_i,
output WbClk_ok, input WbSlaveStb_i,
input WbSlaveCyc_i, input [24:0] WbSlaveAdr_ib25,
input WbSlaveStb_i, input WbSlaveWr_i,
input [24:0] WbSlaveAdr_ib25, input [31:0] WbSlaveDat_ib32,
input WbSlaveWr_i,
input [31:0] WbSlaveDat_ib32,
output [31:0] WbSlaveDat_ob32, output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o, output WbSlaveAck_o,
/* -----\/----- EXCLUDED -----\/----- output WbMasterCyc_o,
output WbMasterCyc_o, output WbMasterStb_o,
output WbMasterStb_o,
output [24:0] WbMasterAdr_ob25, output [24:0] WbMasterAdr_ob25,
output WbMasterWr_o, output WbMasterWr_o,
output [31:0] WbMasterDat_ob32, output [31:0] WbMasterDat_ob32,
-----/\----- EXCLUDED -----/\----- */ input [31:0] WbMasterDat_ib32,
input [31:0] WbMasterDat_ib32, input WbMasterAck_i,
input WbMasterAck_i, // LED control:
//LED control output [ 1:0] TopLed_ob2,
/* -----\/----- EXCLUDED -----\/----- output [ 3:0] BottomLed_ob4,
output [1:0] TopLed_ob2, // BST input:
output [3:0] BottomLed_ob4, input BstOn_i,
-----/\----- EXCLUDED -----/\----- */ input BstClk_ik, // Comment: 160 MHz
//BST input input BunchClkFlag_i,
input BstOn_i, input TurnClkFlag_i,
input BunchClk_ik, input [ 7:0] BstByteAddress_ib8,
input TurnClk_ip, input [ 7:0] BstByte_ib8,
input [5:0] BstByteAddress_ib5, output BstByteStrobe_i,
input [7:0] BstByte_ib8, output BstByteError_i,
//Interrupt // Interrupt:
/* -----\/----- EXCLUDED -----\/-----
output [23:0] InterruptRequest_opb24, output [23:0] InterruptRequest_opb24,
//Ethernet streamer // Ethernet streamer:
output StreamerClk_ok, output StreamerClk_ok,
output [31:0] StreamerData_ob32, output [31:0] StreamerData_ob32,
output SreamerDav_o, output SreamerDav_o,
output StreamerPckt_o, output StreamerPckt_o,
-----/\----- EXCLUDED -----/\----- */ input StreamerWait_i,
input StreamerWait_i // GPIO direction:
//GPIO direction output GpIo1DirOut_o,
/* -----\/----- EXCLUDED -----\/----- output GpIo2DirOut_o,
output GpIo1DirOut_o, output GpIo34DirOut_o
output GpIo2DirOut_o,
output GpIo34DirOut_o
-----/\----- EXCLUDED -----/\----- */
); );
//**************************** //****************************
//Declarations //Declarations
//**************************** //****************************
wire Clk_k; wire Clk_k;
wire WbStbAppReleaseId, WbAckAppReleaseId; wire WbStbAppReleaseId, WbAckAppReleaseId;
wire [31:0] WbDatAppReleaseId_b32; wire [31:0] WbDatAppReleaseId_b32;
wire WbStbCtrlReg, WbAckCtrlReg; wire WbStbCtrlReg, WbAckCtrlReg;
wire [31:0] WbDatCtrlReg_b32; wire [31:0] WbDatCtrlReg_b32;
wire WbStbStatReg, WbAckStatReg; wire WbStbStatReg, WbAckStatReg;
wire [31:0] WbDatStatReg_b32; wire [31:0] WbDatStatReg_b32;
wire [31:0] Reg0Value_b32; wire [31:0] Reg0Value_b32;
wire [31:0] Reg1Value_b32;
wire [31:0] Reg2Value_b32;
wire [31:0] Reg3Value_b32;
//**************************** //****************************
//Fixed assignments //Fixed assignments
...@@ -185,7 +170,7 @@ assign OeSi57x_oe = 1'b1; ...@@ -185,7 +170,7 @@ assign OeSi57x_oe = 1'b1;
//Clocking //Clocking
//**************************** //****************************
assign Clk_k = GbitTrxClkRefR_ik; //~125MHz assign Clk_k = GbitTrxClkRefR_ik; //~125MHz
assign WbClk_ok = Clk_k; assign WbClk_ok = Clk_k;
//**************************** //****************************
...@@ -193,58 +178,58 @@ assign WbClk_ok = Clk_k; ...@@ -193,58 +178,58 @@ assign WbClk_ok = Clk_k;
//**************************** //****************************
AddrDecoderWBApp i_AddrDecoderWbApp( AddrDecoderWBApp i_AddrDecoderWbApp(
.Clk_ik(Clk_k), .Clk_ik (Clk_k),
.Adr_ib21(WbSlaveAdr_ib25[20:0]), .Adr_ib21 (WbSlaveAdr_ib25[20:0]),
.Stb_i(WbSlaveStb_i), .Stb_i (WbSlaveStb_i),
.Dat_ob32(WbSlaveDat_ob32), .Dat_ob32 (WbSlaveDat_ob32),
.Ack_o(WbSlaveAck_o), .Ack_o (WbSlaveAck_o),
//--
.DatAppReleaseId_ib32(WbDatAppReleaseId_b32), .DatAppReleaseId_ib32 (WbDatAppReleaseId_b32),
.AckAppReleaseId_i(WbAckAppReleaseId), .AckAppReleaseId_i (WbAckAppReleaseId),
.StbAppReleaseId_o(WbStbAppReleaseId), .StbAppReleaseId_o (WbStbAppReleaseId),
//--
.DatCtrlReg_ib32(WbDatCtrlReg_b32), .DatCtrlReg_ib32 (WbDatCtrlReg_b32),
.AckCtrlReg_i(WbAckCtrlReg), .AckCtrlReg_i (WbAckCtrlReg),
.StbCtrlReg_o(WbStbCtrlReg), .StbCtrlReg_o (WbStbCtrlReg),
//--
.DatStatReg_ib32(WbDatStatReg_b32), .DatStatReg_ib32 (WbDatStatReg_b32),
.AckStatReg_i(WbAckStatReg), .AckStatReg_i (WbAckStatReg),
.StbStatReg_o(WbStbStatReg)); .StbStatReg_o (WbStbStatReg));
//**************************** //****************************
//ReleaseID //Release ID
//**************************** //****************************
Generic4InputRegs i_RevisionAndMisc( Generic4InputRegs i_AppReleaseId(
.Rst_irq(Reset_irqp), .Rst_irq (Reset_irqp),
.Clk_ik(Clk_k), .Clk_ik (Clk_k),
.Cyc_i(WbSlaveCyc_i), .Cyc_i (WbSlaveCyc_i),
.Stb_i(WbStbAppReleaseId), .Stb_i (WbStbAppReleaseId),
.Adr_ib2(WbSlaveAdr_ib25[1:0]), .Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32(WbDatAppReleaseId_b32), .Dat_oab32 (WbDatAppReleaseId_b32),
.Ack_oa(WbAckAppReleaseId), .Ack_oa (WbAckAppReleaseId),
.Reg0Value_ib32("VFC "), .Reg0Value_ib32 ("VFC-"),
.Reg1Value_ib32("HD: "), .Reg1Value_ib32 ("HD b"),
.Reg2Value_ib32("base"), .Reg2Value_ib32 ("ase "),
.Reg3Value_ib32({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8})); .Reg3Value_ib32 ({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
//**************************** //****************************
//Example Registers //Example registers
//**************************** //****************************
//Control Register Bank: //Control register bank:
Generic4OutputRegs #( Generic4OutputRegs #(
.Reg0Default (32'hBABEB00B), .Reg0Default (32'hBABEB00B),
.Reg0AutoClrMask (32'hFFFFFFFF), .Reg0AutoClrMask (32'hFFFFFFFF),
.Reg1Default (32'hCAFEAC1D), .Reg1Default (32'h00000000),
.Reg1AutoClrMask (32'hFFFFFFFF), .Reg1AutoClrMask (32'hFFFFFFFF),
.Reg2Default (32'hACDCDEAD), .Reg2Default (32'h00000000),
.Reg2AutoClrMask (32'hFFFFFFFF), .Reg2AutoClrMask (32'hFFFFFFFF),
.Reg3Default (32'hFEEDBEEF), .Reg3Default (32'h00000000),
.Reg3AutoClrMask (32'hFFFFFFFF)) .Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs ( i_ControlRegs (
.Rst_irq (Reset_irqp),
.Clk_ik (Clk_k), .Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i), .Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbCtrlReg), .Stb_i (WbStbCtrlReg),
.We_i (WbSlaveWr_i), .We_i (WbSlaveWr_i),
...@@ -254,23 +239,23 @@ i_ControlRegs ( ...@@ -254,23 +239,23 @@ i_ControlRegs (
.Ack_oa (WbAckCtrlReg), .Ack_oa (WbAckCtrlReg),
//-- //--
.Reg0Value_ob32 (Reg0Value_b32), .Reg0Value_ob32 (Reg0Value_b32),
.Reg1Value_ob32 (Reg1Value_b32), .Reg1Value_ob32 (),
.Reg2Value_ob32 (Reg2Value_b32), .Reg2Value_ob32 (),
.Reg3Value_ob32 (Reg3Value_b32)); .Reg3Value_ob32 ());
//Status Registers Bank: //Status registers bank:
Generic4InputRegs i_StatusRegs ( Generic4InputRegs i_StatusRegs (
.Rst_irq (Reset_irqp), .Clk_ik (Clk_k),
.Cyc_i (WbSlaveCyc_i), .Rst_irq (Reset_irqp),
.Stb_i (WbStbStatReg), .Cyc_i (WbSlaveCyc_i),
.Clk_ik (Clk_k), .Stb_i (WbStbStatReg),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]), .Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatStatReg_b32), .Dat_oab32 (WbDatStatReg_b32),
.Ack_oa (WbAckStatReg), .Ack_oa (WbAckStatReg),
//-- //--
.Reg0Value_ib32 (Reg0Value_b32), .Reg0Value_ib32 (Reg0Value_b32),
.Reg1Value_ib32 (Reg1Value_b32), .Reg1Value_ib32 (32'hCAFEAC1D),
.Reg2Value_ib32 (Reg2Value_b32), .Reg2Value_ib32 (32'hACDCDEAD),
.Reg3Value_ib32 (Reg3Value_b32)); .Reg3Value_ib32 (32'hFEEDBEEF));
endmodule endmodule
\ No newline at end of file
</
`timescale 1ns/100ps
module AddrDecoderWBApp(
input Clk_ik,
input [20:0] Adr_ib21,
input Stb_i,
output reg [31:0] Dat_ob32,
output reg Ack_o,
input [31:0] DatI2cPllRef_ib32,
input AckI2cPllRef_i,
output reg StbI2cPllRef_o,
input [31:0] DatAppReleaseId_ib32,
input AckAppReleaseId_i,
output reg StbAppReleaseId_o,
input [31:0] DatPeriodCounter_ib32,