Commit 9dc0ee45 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev] Merge branch 'be-bi-master'. Tested, works.

parents 20dc4ac3 cbdabb7f
*.bak
*.pyc
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
Doc/AlteraDocuments/EMIF_Altera.pdf
Doc/AlteraDocuments/an520.pdf
Doc/AlteraDocuments/arriav_handbook.pdf
Doc/AlteraDocuments/ddr3AlteraDesign.pdf
Doc/Datasheets/8Gb_DDR3L.pdf
Hw/Assembly data/
Hw/EDA-03133-V2-0_project.Annotation
Hw/EDA-03133-V2-0_project.PrjPCB
Hw/EDA-03133-V2-0_project.PrjPCBStructure
Hw/Manufacturing/EDA-03133-V2_mfg.cam
Hw/PCB-Layout/
Hw/Schematics/
Hdl/Simulation/BasicVmeAccesses/modelsim/project/BasicVmeAccesses.cr.mti
/Hdl/Simulation/*Project/modelsim/project/*
!/Hdl/Simulation/*Project/modelsim/project/*.mpf
/Hdl/Synthesis/*/QuartusPrj/*
!/Hdl/Synthesis/*/QuartusPrj/*.qpf
!/Hdl/Synthesis/*/QuartusPrj/*.qsf
/Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
/Doc/AlteraDocuments/EMIF_Altera.pdf
/Doc/AlteraDocuments/an520.pdf
/Doc/AlteraDocuments/arriav_handbook.pdf
/Doc/AlteraDocuments/ddr3AlteraDesign.pdf
/Doc/Datasheets/8Gb_DDR3L.pdf
/Doc/VfcHd_UserGuides/BI-VFC-HD-V2_0.pdf
/Hw/Assembly data/
/Hw/EDA-03133-V2-0_project.Annotation
/Hw/EDA-03133-V2-0_project.PrjPCB
/Hw/EDA-03133-V2-0_project.PrjPCBStructure
/Hw/Manufacturing/EDA-03133-V2_mfg.cam
/Hw/PCB-Layout/
/Hw/Schematics/
......@@ -63,6 +63,7 @@ initial begin
@(posedge Clk125MHz_kq);
ControlReg1_q = 1'b1;
$display($time, " -> Trigger");
repeat(10000)@(posedge Clk125MHz_kq);
#50000
$display($time, " -> Simulation Stop");
$stop;
......
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'hb2,
g_ApplicationReleaseDay_b8 = 8'h28,
g_ApplicationReleaseMonth_b8 = 8'h04,
#(parameter g_ApplicationVersion_b8 = 8'hC5,
g_ApplicationReleaseDay_b8 = 8'h17,
g_ApplicationReleaseMonth_b8 = 8'h07,
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
/* -----\/----- EXCLUDED -----\/-----
input BstSfpRx_i, //Differential
output BstSfpTx_o, //Differential
input EthSfpRx_i, //Differential
output EthSfpTx_o, //Differential
//SFP Gbit
input [4:1] AppSfpRx_ib4, //Differential
output [4:1] AppSfpTx_ob4, //Differential
//DDR3 SO-DIMM
output [2:0] DdrBa_ob3,
output [7:0] DdrDm_ob8,
inout [7:0] DdrDqs_iob8, //differential signals
input BstSfpRx_i, // Comment: Differential signal
output BstSfpTx_o, // Comment: Differential signal
input EthSfpRx_i, // Comment: Differential signal
output EthSfpTx_o, // Comment: Differential signal
// SFP Gbit:
input [ 4:1] AppSfpRx_ib4, // Comment: Differential signal
output [ 4:1] AppSfpTx_ob4, // Comment: Differential signal
// DDR3 SO-DIMM:
output [ 2:0] DdrBa_ob3,
output [ 7:0] DdrDm_ob8,
inout [ 7:0] DdrDqs_iob8, // Comment: Differential signal
inout [63:0] DdrDq_iob64,
output [15:0] DdrA_ob16,
output [1:0] DdrCk_okb2, //differential signals
output [1:0] DdrCkE_ohb2,
output [ 1:0] DdrCk_okb2, // Comment: Differential signal
output [ 1:0] DdrCkE_ohb2,
output DdrReset_orn,
output DdrRas_on,
output DdrCas_on,
output DdrWe_on,
output [1:0] DdrCs_onb2,
output [1:0] DdrOdt_ob2,
output [ 1:0] DdrCs_onb2,
output [ 1:0] DdrOdt_ob2,
input DdrTempEvent_in,
output DdrI2cScl_ok,
inout DdrI2cSda_io,
//TestIo
// TestIo:
inout TestIo1_io,
inout TestIo2_io,
//FMC connector
inout [33:0]FmcLaP_iob34,
inout [33:0]FmcLaN_iob34,
inout [23:0]FmcHaP_iob24,
inout [23:0]FmcHaN_iob24,
inout [21:0]FmcHbP_iob22,
inout [21:0]FmcHbN_iob22,
// FMC connector:
output VfmcEnableN_oen,
inout [33:0] FmcLaP_iob34,
inout [33:0] FmcLaN_iob34,
inout [23:0] FmcHaP_iob24,
inout [23:0] FmcHaN_iob24,
inout [21:0] FmcHbP_iob22,
inout [21:0] FmcHbN_iob22,
input FmcPrsntM2C_in,
output FmcTck_ok,
output FmcTms_o,
......@@ -56,19 +56,17 @@ module VfcHdApplication
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
inout FmcClk2Bidir_iok, //differential signal
inout FmcClk3Bidir_iok, //differential signal
inout FmcClk2Bidir_iok, // Comment: Differential signal
inout FmcClk3Bidir_iok, // Comment: Differential signal
input FmcClkDir_i,
output [9:0] FmcDpC2M_ob10, //diff output
input [9:0] FmcDpM2C_ib10,
input FmcGbtClk0M2CLeft_ik, //differential signal
input FmcGbtClk1M2CLeft_ik, //differential signal
input FmcGbtClk0M2CRight_ik, //differential signal
input FmcGbtClk1M2CRight_ik, //differential signal
-----/\----- EXCLUDED -----/\----- */
//Clock sources and control
output [ 9:0] FmcDpC2M_ob10, // Comment: Differential signal
input [ 9:0] FmcDpM2C_ib10,
input FmcGbtClk0M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk1M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk0M2CRight_ik, // Comment: Differential signal
input FmcGbtClk1M2CRight_ik, // Comment: Differential signal
// Clock sources and control:
output OeSi57x_oe,
/* -----\/----- EXCLUDED -----\/-----
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
......@@ -77,40 +75,35 @@ module VfcHdApplication
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
inout PllRefSda_io,
output PllRefScl_ok,
inout PllRefInt_i,
inout PllRefSda_io,
input PllRefInt_i,
output PllSourceMuxOut_ok,
input PllRefClkOut_ik, //Differential reference for the Gbit lines
-----/\----- EXCLUDED -----/\----- */
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines ~125MHz
/* -----\/----- EXCLUDED -----\/-----
//SW1
input [1:0] Switch_ib2,
//P2 RTM
inout [19:0] P2DataP_iob20, //the 0 is a clock capable input
input PllRefClkOut_ik, // Comment: Differential reference for the Gbit lines
input GbitTrxClkRefR_ik, // Comment: Differential reference for the Gbit lines ~125MHz
// SW1:
input [ 1:0] Switch_ib2,
// P2 RTM:
inout [19:0] P2DataP_iob20, //Comment: The 0 is a clock capable input
inout [19:0] P2DataN_iob20,
//P0 Timing
input [7:0] P0HwHighByte_ib8,
input [7:0] P0HwLowByte_ib8,
// P0 Timing:
input [ 7:0] P0HwHighByte_ib8,
input [ 7:0] P0HwLowByte_ib8,
output DaisyChain1Cntrl_o,
output DaisyChain2Cntrl_o,
input VmeP0BunchClk_ik,
input VmeP0Tclk_ik,
//GPIO
inout [4:1] GpIo_iob4,
//Specials
// GPIO:
inout [ 4:1] GpIo_iob4,
// Specials:
input PushButtonN_in,
-----/\----- EXCLUDED -----/\----- */
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
//Reset
input Reset_irqp, //Reset Synchronous with the WbClk_ik
/* -----\/----- EXCLUDED -----\/-----
output ResetRequest_oqp, //Request to issue a reset
-----/\----- EXCLUDED -----/\----- */
//WishBone
// Reset:
input Reset_irqp, // Comment: Reset Synchronous with the WbClk_ik
output ResetRequest_oqp, // Comment: Request to issue a reset
// WishBone:
output WbClk_ok,
input WbSlaveCyc_i,
input WbSlaveStb_i,
......@@ -119,42 +112,37 @@ module VfcHdApplication
input [31:0] WbSlaveDat_ib32,
output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o,
/* -----\/----- EXCLUDED -----\/-----
output WbMasterCyc_o,
output WbMasterStb_o,
output [24:0] WbMasterAdr_ob25,
output WbMasterWr_o,
output [31:0] WbMasterDat_ob32,
-----/\----- EXCLUDED -----/\----- */
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
//LED control
/* -----\/----- EXCLUDED -----\/-----
output [1:0] TopLed_ob2,
output [3:0] BottomLed_ob4,
-----/\----- EXCLUDED -----/\----- */
//BST input
// LED control:
output [ 1:0] TopLed_ob2,
output [ 3:0] BottomLed_ob4,
// BST input:
input BstOn_i,
input BunchClk_ik,
input TurnClk_ip,
input [5:0] BstByteAddress_ib5,
input [7:0] BstByte_ib8,
//Interrupt
/* -----\/----- EXCLUDED -----\/-----
input BstClk_ik, // Comment: 160 MHz
input BunchClkFlag_i,
input TurnClkFlag_i,
input [ 7:0] BstByteAddress_ib8,
input [ 7:0] BstByte_ib8,
output BstByteStrobe_i,
output BstByteError_i,
// Interrupt:
output [23:0] InterruptRequest_opb24,
//Ethernet streamer
// Ethernet streamer:
output StreamerClk_ok,
output [31:0] StreamerData_ob32,
output SreamerDav_o,
output StreamerPckt_o,
-----/\----- EXCLUDED -----/\----- */
input StreamerWait_i
//GPIO direction
/* -----\/----- EXCLUDED -----\/-----
input StreamerWait_i,
// GPIO direction:
output GpIo1DirOut_o,
output GpIo2DirOut_o,
output GpIo34DirOut_o
-----/\----- EXCLUDED -----/\----- */
);
//****************************
......@@ -171,9 +159,6 @@ wire WbStbStatReg, WbAckStatReg;
wire [31:0] WbDatStatReg_b32;
wire [31:0] Reg0Value_b32;
wire [31:0] Reg1Value_b32;
wire [31:0] Reg2Value_b32;
wire [31:0] Reg3Value_b32;
//****************************
//Fixed assignments
......@@ -193,58 +178,58 @@ assign WbClk_ok = Clk_k;
//****************************
AddrDecoderWBApp i_AddrDecoderWbApp(
.Clk_ik(Clk_k),
.Adr_ib21(WbSlaveAdr_ib25[20:0]),
.Stb_i(WbSlaveStb_i),
.Dat_ob32(WbSlaveDat_ob32),
.Ack_o(WbSlaveAck_o),
.DatAppReleaseId_ib32(WbDatAppReleaseId_b32),
.AckAppReleaseId_i(WbAckAppReleaseId),
.StbAppReleaseId_o(WbStbAppReleaseId),
.DatCtrlReg_ib32(WbDatCtrlReg_b32),
.AckCtrlReg_i(WbAckCtrlReg),
.StbCtrlReg_o(WbStbCtrlReg),
.DatStatReg_ib32(WbDatStatReg_b32),
.AckStatReg_i(WbAckStatReg),
.StbStatReg_o(WbStbStatReg));
.Clk_ik (Clk_k),
.Adr_ib21 (WbSlaveAdr_ib25[20:0]),
.Stb_i (WbSlaveStb_i),
.Dat_ob32 (WbSlaveDat_ob32),
.Ack_o (WbSlaveAck_o),
//--
.DatAppReleaseId_ib32 (WbDatAppReleaseId_b32),
.AckAppReleaseId_i (WbAckAppReleaseId),
.StbAppReleaseId_o (WbStbAppReleaseId),
//--
.DatCtrlReg_ib32 (WbDatCtrlReg_b32),
.AckCtrlReg_i (WbAckCtrlReg),
.StbCtrlReg_o (WbStbCtrlReg),
//--
.DatStatReg_ib32 (WbDatStatReg_b32),
.AckStatReg_i (WbAckStatReg),
.StbStatReg_o (WbStbStatReg));
//****************************
//ReleaseID
//Release ID
//****************************
Generic4InputRegs i_RevisionAndMisc(
.Rst_irq(Reset_irqp),
.Clk_ik(Clk_k),
.Cyc_i(WbSlaveCyc_i),
.Stb_i(WbStbAppReleaseId),
.Adr_ib2(WbSlaveAdr_ib25[1:0]),
.Dat_oab32(WbDatAppReleaseId_b32),
.Ack_oa(WbAckAppReleaseId),
.Reg0Value_ib32("VFC "),
.Reg1Value_ib32("HD: "),
.Reg2Value_ib32("base"),
.Reg3Value_ib32({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
Generic4InputRegs i_AppReleaseId(
.Rst_irq (Reset_irqp),
.Clk_ik (Clk_k),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbAppReleaseId),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatAppReleaseId_b32),
.Ack_oa (WbAckAppReleaseId),
.Reg0Value_ib32 ("VFC-"),
.Reg1Value_ib32 ("HD b"),
.Reg2Value_ib32 ("ase "),
.Reg3Value_ib32 ({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
//****************************
//Example Registers
//Example registers
//****************************
//Control Register Bank:
//Control register bank:
Generic4OutputRegs #(
.Reg0Default (32'hBABEB00B),
.Reg0AutoClrMask (32'hFFFFFFFF),
.Reg1Default (32'hCAFEAC1D),
.Reg1Default (32'h00000000),
.Reg1AutoClrMask (32'hFFFFFFFF),
.Reg2Default (32'hACDCDEAD),
.Reg2Default (32'h00000000),
.Reg2AutoClrMask (32'hFFFFFFFF),
.Reg3Default (32'hFEEDBEEF),
.Reg3Default (32'h00000000),
.Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs (
.Rst_irq (Reset_irqp),
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbCtrlReg),
.We_i (WbSlaveWr_i),
......@@ -254,23 +239,23 @@ i_ControlRegs (
.Ack_oa (WbAckCtrlReg),
//--
.Reg0Value_ob32 (Reg0Value_b32),
.Reg1Value_ob32 (Reg1Value_b32),
.Reg2Value_ob32 (Reg2Value_b32),
.Reg3Value_ob32 (Reg3Value_b32));
.Reg1Value_ob32 (),
.Reg2Value_ob32 (),
.Reg3Value_ob32 ());
//Status Registers Bank:
//Status registers bank:
Generic4InputRegs i_StatusRegs (
.Clk_ik (Clk_k),
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbStatReg),
.Clk_ik (Clk_k),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatStatReg_b32),
.Ack_oa (WbAckStatReg),
//--
.Reg0Value_ib32 (Reg0Value_b32),
.Reg1Value_ib32 (Reg1Value_b32),
.Reg2Value_ib32 (Reg2Value_b32),
.Reg3Value_ib32 (Reg3Value_b32));
.Reg1Value_ib32 (32'hCAFEAC1D),
.Reg2Value_ib32 (32'hACDCDEAD),
.Reg3Value_ib32 (32'hFEEDBEEF));
endmodule
\ No newline at end of file
`timescale 1ns/100ps
module AddrDecoderWBApp(
input Clk_ik,
input [20:0] Adr_ib21,
input Stb_i,
output reg [31:0] Dat_ob32,
output reg Ack_o,
input [31:0] DatI2cPllRef_ib32,
input AckI2cPllRef_i,
output reg StbI2cPllRef_o,
input [31:0] DatAppReleaseId_ib32,
input AckAppReleaseId_i,
output reg StbAppReleaseId_o,
input [31:0] DatPeriodCounter_ib32,
input AckPeriodCounter_i,
output reg StbPeriodCounter_o,
input [31:0] DatSpiMaster_ib32,
input AckSpiMaster_i,
output reg StbSpiMaster_o,
input [31:0] DatFmcTest_ib32,
input AckFmcTest_i,
output reg StbFmcTest_o,
input [31:0] DatMgtTest_ib32,
input AckMgtTest_i,
output reg StbMgtTest_o,
input [31:0] DatGpIoControl_ib32,
input AckGpIoControl_i,
output reg StbGpIoControl_o
);
localparam dly = 1;
reg [7:0] SelectedModule_b8;
localparam c_SelNothing = 8'h0,
c_SelI2cPllRef = 8'd1,
c_SelPeriodCounter = 8'd2,
c_SelSpiMaster = 8'd3,
c_SelFmcTest = 8'd4,
c_SelMgtTest = 8'd5,
c_SelGpIoControl = 8'd6,
c_SelAppRevisionId = 8'd7;
always @*
casez(Adr_ib21)
21'b0_0000_0000_0000_0000_00??: SelectedModule_b8 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0000_01??: SelectedModule_b8 = c_SelPeriodCounter; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0000_1???: SelectedModule_b8 = c_SelSpiMaster; // FROM 00_0008 TO 00_000F (WB) == FROM 00_0020 TO 00_003C (VME) <- 8 regs ( 32B)
21'b0_0000_0000_0000_0001_00??: SelectedModule_b8 = c_SelGpIoControl; // FROM 00_0010 TO 00_0013 (WB) == FROM 00_0040 TO 00_004C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0001_01??: SelectedModule_b8 = c_SelI2cPllRef; // FROM 00_0014 TO 00_0017 (WB) == FROM 00_0050 TO 00_005C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_001?_????: SelectedModule_b8 = c_SelFmcTest; // FROM 00_0020 TO 00_003F (WB) == FROM 00_0080 TO 00_00FC (VME) <- 32 regs (128B)
21'b0_0000_0000_0000_1???_????: SelectedModule_b8 = c_SelMgtTest; // FROM 00_0080 TO 00_00FF (WB) == FROM 00_0200 TO 00_03FC (VME) <- 128 regs (512B)
default: SelectedModule_b8 = c_SelNothing;
endcase
always @(posedge Clk_ik) begin
Ack_o <= #dly 1'b0;
Dat_ob32 <= #dly 32'h0;
StbI2cPllRef_o <= #dly 1'b0;
StbPeriodCounter_o <= #dly 1'b0;
StbSpiMaster_o <= #dly 1'b0;
StbMgtTest_o <= #dly 1'b0;
StbFmcTest_o <= #dly 1'b0;
StbGpIoControl_o <= #dly 1'b0;
StbAppReleaseId_o <= #dly 1'b0;
case(SelectedModule_b8)
c_SelAppRevisionId: begin
StbAppReleaseId_o <= #dly Stb_i;
Dat_ob32 <= #dly DatAppReleaseId_ib32;
Ack_o <= #dly AckAppReleaseId_i;
end
c_SelI2cPllRef: begin
StbI2cPllRef_o <= #dly Stb_i;
Dat_ob32 <= #dly DatI2cPllRef_ib32;
Ack_o <= #dly AckI2cPllRef_i;
end
c_SelPeriodCounter: begin
StbPeriodCounter_o <= #dly Stb_i;
Dat_ob32 <= #dly DatPeriodCounter_ib32;
Ack_o <= #dly AckPeriodCounter_i;
end
c_SelSpiMaster: begin
StbSpiMaster_o <= #dly Stb_i;
Dat_ob32 <= #dly DatSpiMaster_ib32;
Ack_o <= #dly AckSpiMaster_i;
end
c_SelFmcTest: begin
StbFmcTest_o <= #dly Stb_i;
Dat_ob32 <= #dly DatFmcTest_ib32;
Ack_o <= #dly AckFmcTest_i;
end
c_SelMgtTest: begin
StbMgtTest_o <= #dly Stb_i;
Dat_ob32 <= #dly DatMgtTest_ib32;
Ack_o <= #dly AckMgtTest_i;
end
c_SelGpIoControl: begin
StbGpIoControl_o <= #dly Stb_i;
Dat_ob32 <= #dly DatGpIoControl_ib32;
Ack_o <= #dly AckGpIoControl_i;
end
endcase
end
endmodule
`timescale 1ns/100ps
//Manoel Barros Marin, BE-BI-QP (CERN) - 04/06/15
module user_io_checker # (
//***********
//Parameters:
//***********
parameter g_BusWidth = 80,
g_ReadDly = 30, //10cycles@125MHz = 240ns
g_TestDly = 10) (
//*****
//I/Os:
//*****
input Reset_ir,