Commit a214d8fa authored by Andrea Boccardi's avatar Andrea Boccardi
Browse files

Merge branch 'master' of ssh://gitlab.cern.ch:7999/bi/VFC-HD

Conflicts:
	.gitignore
	Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
parents 6243bf89 69018158
`timescale 1ns/100ps
module AddrDecoderWBApp(
input Clk_ik,
input [20:0] Adr_ib21,
input Stb_i,
output reg [31:0] Dat_ob32,
output reg Ack_o,
input [31:0] DatAppReleaseId_ib32,
input AckAppReleaseId_i,
output reg StbAppReleaseId_o,
input [31:0] DatCtrlReg_ib32,
input AckCtrlReg_i,
output reg StbCtrlReg_o,
input [31:0] DatStatReg_ib32,
input AckStatReg_i,
output reg StbStatReg_o
);
localparam dly = 1;
reg [1:0] SelectedModule_b2;
localparam c_SelNothing = 2'd0,
c_SelAppRevisionId = 2'd1,
c_SelCtrlReg = 2'd2,
c_SelStatReg = 2'd3;
always @*
casez(Adr_ib21)
21'b0_0000_0000_0000_0000_00??: SelectedModule_b2 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_01??: SelectedModule_b2 = c_SelCtrlReg; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_10??: SelectedModule_b2 = c_SelStatReg; // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
default: SelectedModule_b2 = c_SelNothing;
endcase
always @(posedge Clk_ik) begin
Ack_o <= #dly 1'b0;
Dat_ob32 <= #dly 32'h0;
StbAppReleaseId_o <= #dly 1'b0;
StbCtrlReg_o <= #dly 1'b0;
StbStatReg_o <= #dly 1'b0;
case(SelectedModule_b2)
c_SelAppRevisionId: begin
StbAppReleaseId_o <= #dly Stb_i;
Dat_ob32 <= #dly DatAppReleaseId_ib32;
Ack_o <= #dly AckAppReleaseId_i;
end
c_SelCtrlReg: begin
StbCtrlReg_o <= #dly Stb_i;
Dat_ob32 <= #dly DatCtrlReg_ib32;
Ack_o <= #dly AckCtrlReg_i;
end
c_SelStatReg: begin
StbStatReg_o <= #dly Stb_i;
Dat_ob32 <= #dly DatStatReg_ib32;
Ack_o <= #dly AckStatReg_i;
end
endcase
end
endmodule
\ No newline at end of file
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'hb1,
g_ApplicationReleaseDay_b8 = 8'h01,
g_ApplicationReleaseMonth_b8 = 8'h03,
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
input BstSfpRx_i, //Differential
output BstSfpTx_o, //Differential
input EthSfpRx_i, //Differential
output EthSfpTx_o, //Differential
//SFP Gbit
input [4:1] AppSfpRx_ib4, //Differential
output [4:1] AppSfpTx_ob4, //Differential
//DDR3 SO-DIMM
output [2:0] DdrBa_ob3,
output [7:0] DdrDm_ob8,
inout [7:0] DdrDqs_iob8, //differential signals
inout [63:0] DdrDq_iob64,
output [15:0] DdrA_ob16,
output [1:0] DdrCk_okb2, //differential signals
output [1:0] DdrCkE_ohb2,
output DdrReset_orn,
output DdrRas_on,
output DdrCas_on,
output DdrWe_on,
output [1:0] DdrCs_onb2,
output [1:0] DdrOdt_ob2,
input DdrTempEvent_in,
output DdrI2cScl_ok,
inout DdrI2cSda_io,
//TestIo
inout TestIo1_io,
inout TestIo2_io,
//FMC connector
inout [33:0]FmcLaP_iob34,
inout [33:0]FmcLaN_iob34,
inout [23:0]FmcHaP_iob24,
inout [23:0]FmcHaN_iob24,
inout [21:0]FmcHbP_iob22,
inout [21:0]FmcHbN_iob22,
input FmcPrsntM2C_in,
output FmcTck_ok,
output FmcTms_o,
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,
output FmcScl_ok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
input FmcClk2Bidir_ik, //differential signal
input FmcClk3Bidir_ik, //differential signal
input FmcClkDir_i,
output [9:0] FmcDpC2M_ob10, //diff output
input [9:0] FmcDpM2C_ib10,
input FmcGbtClk0M2CLeft_ik, //differential signal
input FmcGbtClk1M2CLeft_ik, //differential signal
input FmcGbtClk0M2CRight_ik, //differential signal
input FmcGbtClk1M2CRight_ik, //differential signal
//Clock sources and control
output OeSi57x_oe,
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
inout PllRefSda_io,
output PllRefScl_ok,
inout PllRefInt_i,
output PllSourceMuxOut_ok,
input PllRefClkOut_ik, //Differential reference for the Gbit lines
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines ~125MHz
//SW1
input [1:0] Switch_ib2,
//P2 RTM
inout [19:0] P2DataP_iob20, //the 0 is a clock capable input
inout [19:0] P2DataN_iob20,
//P0 Timing
input [7:0] P0HwHighByte_ib8,
input [7:0] P0HwLowByte_ib8,
output DaisyChain1Cntrl_o,
output DaisyChain2Cntrl_o,
input VmeP0BunchClk_ik,
input VmeP0Tclk_ik,
//GPIO
inout [4:1] GpIo_iob4,
//Specials
input PushButtonN_in,
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
//Reset
input Reset_irqp, //Reset Synchronous with the WbClk_ik
output ResetRequest_oqp, //Request to issue a reset
//WishBone
output WbClk_ok,
input WbSlaveCyc_i,
input WbSlaveStb_i,
input [24:0] WbSlaveAdr_ib25,
input WbSlaveWr_i,
input [31:0] WbSlaveDat_ib32,
output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o,
output WbMasterCyc_o,
output WbMasterStb_o,
output [24:0] WbMasterAdr_ob25,
output WbMasterWr_o,
output [31:0] WbMasterDat_ob32,
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
//LED control
output [1:0] TopLed_ob2,
output [3:0] BottomLed_ob4,
//BST input
input BstOn_i,
input BunchClk_ik,
input TurnClk_ip,
input [5:0] BstByteAddress_ib5,
input [7:0] BstByte_ib8,
//Interrupt
output [23:0] InterruptRequest_opb24,
//Ethernet streamer
output StreamerClk_ok,
output [31:0] StreamerData_ob32,
output SreamerDav_o,
output StreamerPckt_o,
input StreamerWait_i,
//GPIO direction
output GpIo1DirOut_o,
output GpIo2DirOut_o,
output GpIo34DirOut_o
);
//****************************
//Declarations
//****************************
wire Clk_k;
wire WbStbAppReleaseId, WbAckAppReleaseId;
wire [31:0] WbDatAppReleaseId_b32;
wire WbStbCtrlReg, WbAckCtrlReg;
wire [31:0] WbDatCtrlReg_b32;
wire WbStbStatReg, WbAckStatReg;
wire [31:0] WbDatStatReg_b32;
wire [31:0] Reg0Value_b32;
wire [31:0] Reg1Value_b32;
wire [31:0] Reg2Value_b32;
wire [31:0] Reg3Value_b32;
//****************************
//Fixed assignments
//****************************
assign OeSi57x_oe = 1'b1;
//****************************
//Clocking
//****************************
assign Clk_k = GbitTrxClkRefR_ik; //~125MHz
assign WbClk_ok = Clk_k;
//****************************
//WB address decoder
//****************************
AddrDecoderWBApp i_AddrDecoderWbApp(
.Clk_ik(Clk_k),
.Adr_ib21(WbSlaveAdr_ib25[20:0]),
.Stb_i(WbSlaveStb_i),
.Dat_ob32(WbSlaveDat_ob32),
.Ack_o(WbSlaveAck_o),
.DatAppReleaseId_ib32(WbDatAppReleaseId_b32),
.AckAppReleaseId_i(WbAckAppReleaseId),
.StbAppReleaseId_o(WbStbAppReleaseId),
.DatCtrlReg_ib32(WbDatCtrlReg_b32),
.AckCtrlReg_i(WbAckCtrlReg),
.StbCtrlReg_o(WbStbCtrlReg),
.DatStatReg_ib32(WbDatStatReg_b32),
.AckStatReg_i(WbAckStatReg),
.StbStatReg_o(WbStbStatReg));
//****************************
//ReleaseID
//****************************
Generic4InputRegs i_RevisionAndMisc(
.Rst_irq(Reset_irqp),
.Clk_ik(Clk_k),
.Cyc_i(WbSlaveCyc_i),
.Stb_i(WbStbAppReleaseId),
.Adr_ib2(WbSlaveAdr_ib25[1:0]),
.Dat_oab32(WbDatAppReleaseId_b32),
.Ack_oa(WbAckAppReleaseId),
.Reg0Value_ib32("VFC "),
.Reg1Value_ib32("HD: "),
.Reg2Value_ib32("base"),
.Reg3Value_ib32({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
//****************************
//Example Registers
//****************************
//Control Register Bank:
Generic4OutputRegs #(
.Reg0Default (32'hBABEB00B),
.Reg0AutoClrMask (32'hFFFFFFFF),
.Reg1Default (32'hCAFEAC1D),
.Reg1AutoClrMask (32'hFFFFFFFF),
.Reg2Default (32'hACDCDEAD),
.Reg2AutoClrMask (32'hFFFFFFFF),
.Reg3Default (32'hFEEDBEEF),
.Reg3AutoClrMask (32'hFFFFFFFF))
i_ControlRegs (
.Rst_irq (Reset_irqp),
.Clk_ik (Clk_k),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbCtrlReg),
.We_i (WbSlaveWr_i),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_oab32 (WbDatCtrlReg_b32),
.Ack_oa (WbAckCtrlReg),
//--
.Reg0Value_ob32 (Reg0Value_b32),
.Reg1Value_ob32 (Reg1Value_b32),
.Reg2Value_ob32 (Reg2Value_b32),
.Reg3Value_ob32 (Reg3Value_b32));
//Status Registers Bank:
Generic4InputRegs i_StatusRegs (
.Rst_irq (Reset_irqp),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbStatReg),
.Clk_ik (Clk_k),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatStatReg_b32),
.Ack_oa (WbAckStatReg),
//--
.Reg0Value_ib32 (Reg0Value_b32),
.Reg1Value_ib32 (Reg1Value_b32),
.Reg2Value_ib32 (Reg2Value_b32),
.Reg3Value_ib32 (Reg3Value_b32));
endmodule
\ No newline at end of file
......@@ -31,11 +31,10 @@ module prbs_gen_40b # (
//*************
//Declarations:
//*************
genvar i;
reg LFb;
reg [30:0] Lsr_qb31; // prbs-31
reg [39:0] prbs_qb40;
reg [ 5:0] i;
//***********
//User Logic:
......@@ -45,41 +44,38 @@ module prbs_gen_40b # (
if (Reset_ir) begin
LFb <= #1 1'b0;
Lsr_qb31 <= #1 g_PrbsSeed;
i <= #1 1'b0;
prbs_qb40 <= #1 40'b0;
Dv_o <= #1 1'b0;
TxData_ob40 <= #1 40'b0;
end else begin
repeat (40) begin
for (i=0;i<40;i++) begin
prbs_qb40[i] = Lsr_qb31[30];
LFb = Lsr_qb31[30]^Lsr_qb31[27]; // See Xilinx XAPP210
Lsr_qb31 = {Lsr_qb31[29:0],LFb};
i = i+1;
end
i <= #1 1'b0;
if (RxDataAligned_i) begin
Dv_o <= #1 1'b1;
TxData_ob40 <= #1 prbs_qb40;
if (SingleErrorInject_i) begin
TxData_ob40[0] <= #1 ~prbs_qb40[0];
TxData_ob40[0] <= #1 ~prbs_qb40[0];
end else if (MultiErrorInject_i) begin
TxData_ob40[ 0] <= #1 ~prbs_qb40[ 0];
TxData_ob40[ 1] <= #1 ~prbs_qb40[ 1];
TxData_ob40[ 2] <= #1 ~prbs_qb40[ 2];
TxData_ob40[ 3] <= #1 ~prbs_qb40[ 3];
TxData_ob40[ 4] <= #1 ~prbs_qb40[ 4];
TxData_ob40[ 5] <= #1 ~prbs_qb40[ 5];
TxData_ob40[ 6] <= #1 ~prbs_qb40[ 6];
TxData_ob40[ 7] <= #1 ~prbs_qb40[ 7];
TxData_ob40[ 0] <= #1 ~prbs_qb40[ 0];
TxData_ob40[ 1] <= #1 ~prbs_qb40[ 1];
TxData_ob40[ 2] <= #1 ~prbs_qb40[ 2];
TxData_ob40[ 3] <= #1 ~prbs_qb40[ 3];
TxData_ob40[ 4] <= #1 ~prbs_qb40[ 4];
TxData_ob40[ 5] <= #1 ~prbs_qb40[ 5];
TxData_ob40[ 6] <= #1 ~prbs_qb40[ 6];
TxData_ob40[ 7] <= #1 ~prbs_qb40[ 7];
//---
TxData_ob40[24] <= #1 ~prbs_qb40[24];
TxData_ob40[25] <= #1 ~prbs_qb40[25];
TxData_ob40[26] <= #1 ~prbs_qb40[26];
TxData_ob40[27] <= #1 ~prbs_qb40[27];
TxData_ob40[28] <= #1 ~prbs_qb40[28];
TxData_ob40[29] <= #1 ~prbs_qb40[29];
TxData_ob40[30] <= #1 ~prbs_qb40[30];
TxData_ob40[31] <= #1 ~prbs_qb40[31];
TxData_ob40[24] <= #1 ~prbs_qb40[24];
TxData_ob40[25] <= #1 ~prbs_qb40[25];
TxData_ob40[26] <= #1 ~prbs_qb40[26];
TxData_ob40[27] <= #1 ~prbs_qb40[27];
TxData_ob40[28] <= #1 ~prbs_qb40[28];
TxData_ob40[29] <= #1 ~prbs_qb40[29];
TxData_ob40[30] <= #1 ~prbs_qb40[30];
TxData_ob40[31] <= #1 ~prbs_qb40[31];
end
end else begin
Dv_o <= #1 1'b0;
......
......@@ -11,7 +11,7 @@ functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus II License Agreement,
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
......
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_TOOL_NAME "altera_xcvr_native_av"
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_TOOL_VERSION "15.0"
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_TOOL_VERSION "15.1"
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "gx_native_x3" -name MISC_FILE [file join $::quartus(qip_path) "gx_native_x3.cmp"]
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_TARGETED_DEVICE_FAMILY "Arria V"
......@@ -11,14 +11,14 @@ set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_CO
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_COMPONENT_VERSION "MTUuMA=="
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_COMPONENT_VERSION "MTUuMQ=="
set_global_assignment -entity "gx_native_x3" -library "gx_native_x3" -name IP_COMPONENT_DESCRIPTION "QXJyaWEgViBUcmFuc2NlaXZlciBOYXRpdmUgUEhZLg=="
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_NAME "YWx0ZXJhX3hjdnJfbmF0aXZlX2F2"
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_DISPLAY_NAME "QXJyaWEgViBUcmFuc2NlaXZlciBOYXRpdmUgUEhZ"
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_INTERNAL "On"
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_VERSION "MTUuMA=="
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_VERSION "MTUuMQ=="
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_DESCRIPTION "QXJyaWEgViBUcmFuc2NlaXZlciBOYXRpdmUgUEhZLg=="
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::QXJyaWEgVg==::ZGV2aWNlX2ZhbWlseQ=="
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX3NwZWVkZ3JhZGU=::ZmFzdGVzdA==::RGV2aWNlIHNwZWVkZ3JhZGU="
......@@ -173,5 +173,5 @@ set_global_assignment -library "gx_native_x3" -name SYSTEMVERILOG_FILE [file joi
set_global_assignment -library "gx_native_x3" -name SOURCE_FILE [file join $::quartus(qip_path) "gx_native_x3/plain_files.txt"]
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_TOOL_NAME "altera_xcvr_native_av"
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_TOOL_VERSION "15.0"
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_TOOL_VERSION "15.1"
set_global_assignment -entity "altera_xcvr_native_av" -library "gx_native_x3" -name IP_TOOL_ENV "mwpim"
set_global_assignment -entity "gx_native_x3" -library "lib_gx_native_x3" -name IP_TOOL_NAME "altera_xcvr_native_av"
set_global_assignment -entity "gx_native_x3" -library "lib_gx_native_x3" -name IP_TOOL_VERSION "15.0"
set_global_assignment -entity "gx_native_x3" -library "lib_gx_native_x3" -name IP_TOOL_VERSION "15.1"
set_global_assignment -entity "gx_native_x3" -library "lib_gx_native_x3" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lib_gx_native_x3" -name SPD_FILE [file join $::quartus(sip_path) "gx_native_x3.spd"]
......
// megafunction wizard: %Arria V Transceiver Native PHY v15.0%
// megafunction wizard: %Arria V Transceiver Native PHY v15.1%
// GENERATION: XML
// gx_native_x3.v
// Generated using ACDS version 15.0 145
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module gx_native_x3 (
......@@ -166,7 +166,7 @@ endmodule
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2015 Altera Corporation
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
......@@ -186,7 +186,7 @@ endmodule
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_xcvr_native_av" version="15.0" >
// Retrieval info: <instance entity-name="altera_xcvr_native_av" version="15.1" >
// Retrieval info: <generic name="device_family" value="Arria V" />
// Retrieval info: <generic name="show_advanced_features" value="0" />
// Retrieval info: <generic name="device_speedgrade" value="fastest" />
......
# (C) 2001-2015 Altera Corporation. All rights reserved.
# (C) 2001-2016 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
......@@ -12,10 +12,49 @@
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 15.0 145 win32 2015.05.12.17:41:01
# ACDS 15.1 185 win32 2016.02.29.12:27:53
# ----------------------------------------
# Auto-generated simulation script rivierapro_setup.tcl
# ----------------------------------------
# This script can be used to simulate the following IP:
# gx_native_x3
# To create a top-level simulation script which compiles other
# IP, and manages other system issues, copy the following template
# and adapt it to your needs:
#
# # Start of template
# # If the copied and modified template file is "aldec.do", run it as:
# # vsim -c -do aldec.do
# #
# # Source the generated sim script
# source rivierapro_setup.tcl
# # Compile eda/sim_lib contents first
# dev_com
# # Override the top-level name (so that elab is useful)
# set TOP_LEVEL_NAME top
# # Compile the standalone IP.
# com
# # Compile the user top-level
# vlog -sv2k5 ../../top.sv
# # Elaborate the design.
# elab
# # Run the simulation
# run
# # Report success to the shell
# exit -code 0
# # End of template
# ----------------------------------------
# If gx_native_x3 is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# Auto-generated simulation script
# ----------------------------------------
# Initialize variables
......@@ -34,7 +73,14 @@ if ![info exists QSYS_SIMDIR] {
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/altera/15.0/quartus/"
set QUARTUS_INSTALL_DIR "C:/altera/15.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
......@@ -91,65 +137,65 @@ vmap gx_native_x3 ./libraries/gx_native_x3
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/arriav_atoms_ncrypt.v" -work arriav_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/arriav_hmi_atoms_ncrypt.v" -work arriav_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/arriav_atoms.v" -work arriav_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/arriav_hssi_atoms_ncrypt.v" -work arriav_hssi_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/arriav_hssi_atoms.v" -work arriav_hssi_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/arriav_pcie_hip_atoms_ncrypt.v" -work arriav_pcie_hip_ver
vlog -v2k5 "$QUARTUS_INSTALL_DIR/eda/sim_lib/arriav_pcie_hip_atoms.v" -work arriav_pcie_hip_ver
eval vlog -v2k5 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog -v2k5 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver