Commit aaff76e8 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev] one final clean-up of VFC-HD base project before integration of Btrain application

parent 00e9bb9e
......@@ -38,7 +38,7 @@ always @*
default: SelectedModule_b2 = c_SelNothing;
endcase
always @(posedge Clk_ik) begin
always @* begin
Ack_o <= #dly 1'b0;
Dat_ob32 <= #dly 32'h0;
StbAppReleaseId_o <= #dly 1'b0;
......@@ -60,7 +60,8 @@ always @(posedge Clk_ik) begin
Dat_ob32 <= #dly DatStatReg_ib32;
Ack_o <= #dly AckStatReg_i;
end
default: ;
endcase
end
endmodule
\ No newline at end of file
endmodule
......@@ -9,35 +9,9 @@ module VfcHdApplication
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
//@@@@@@@@@@@@@@@@@@@@@@@@@
input BstSfpRx_i, // Comment: Differential signal
output BstSfpTx_o, // Comment: Differential signal
input EthSfpRx_i, // Comment: Differential signal
output EthSfpTx_o, // Comment: Differential signal
// SFP Gbit:
input [ 4:1] AppSfpRx_ib4, // Comment: Differential signal
output [ 4:1] AppSfpTx_ob4, // Comment: Differential signal
// DDR3 SO-DIMM:
output [ 2:0] DdrBa_ob3,
output [ 7:0] DdrDm_ob8,
inout [ 7:0] DdrDqs_iob8, // Comment: Differential signal
inout [63:0] DdrDq_iob64,
output [15:0] DdrA_ob16,
output [ 1:0] DdrCk_okb2, // Comment: Differential signal
output [ 1:0] DdrCkE_ohb2,
output DdrReset_orn,
output DdrRas_on,
output DdrCas_on,
output DdrWe_on,
output [ 1:0] DdrCs_onb2,
output [ 1:0] DdrOdt_ob2,
input DdrTempEvent_in,
output DdrI2cScl_ok,
inout DdrI2cSda_io,
// TestIo:
inout TestIo1_io,
inout TestIo2_io,
// FMC connector:
output VfmcEnableN_oen,
/* -----\/----- EXCLUDED -----\/-----
inout [33:0] FmcLaP_iob34,
inout [33:0] FmcLaN_iob34,
inout [23:0] FmcHaP_iob24,
......@@ -65,38 +39,13 @@ module VfcHdApplication
input FmcGbtClk1M2CLeft_ik, // Comment: Differential signal
input FmcGbtClk0M2CRight_ik, // Comment: Differential signal
input FmcGbtClk1M2CRight_ik, // Comment: Differential signal
-----/\----- EXCLUDED -----/\----- */
// Clock sources and control:
output OeSi57x_oe,
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
output PllRefScl_ok,
inout PllRefSda_io,
input PllRefInt_i,
output PllSourceMuxOut_ok,
input PllRefClkOut_ik, // Comment: Differential reference for the Gbit lines
input GbitTrxClkRefR_ik, // Comment: Differential reference for the Gbit lines ~125MHz
// SW1:
input [ 1:0] Switch_ib2,
// P2 RTM:
inout [19:0] P2DataP_iob20, //Comment: The 0 is a clock capable input
inout [19:0] P2DataN_iob20,
// P0 Timing:
input [ 7:0] P0HwHighByte_ib8,
input [ 7:0] P0HwLowByte_ib8,
output DaisyChain1Cntrl_o,
output DaisyChain2Cntrl_o,
input VmeP0BunchClk_ik,
input VmeP0Tclk_ik,
// GPIO:
inout [ 4:1] GpIo_iob4,
// Specials:
input PushButtonN_in,
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
......@@ -112,33 +61,8 @@ module VfcHdApplication
input [31:0] WbSlaveDat_ib32,
output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o,
output WbMasterCyc_o,
output WbMasterStb_o,
output [24:0] WbMasterAdr_ob25,
output WbMasterWr_o,
output [31:0] WbMasterDat_ob32,
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
// LED control:
output [ 1:0] TopLed_ob2,
output [ 3:0] BottomLed_ob4,
// BST input:
input BstOn_i,
input BstClk_ik, // Comment: 160 MHz
input BunchClkFlag_i, // Comment: 40 MHz
input TurnClkFlag_i, // Comment: 11 kHz (LHC) | 44Khz (SPS)
input [ 7:0] BstByteAddress_ib8,
input [ 7:0] BstByte_ib8,
output BstByteStrobe_i,
output BstByteError_i,
// Interrupt:
output [23:0] InterruptRequest_opb24,
// Ethernet streamer:
output StreamerClk_ok,
output [31:0] StreamerData_ob32,
output SreamerDav_o,
output StreamerPckt_o,
input StreamerWait_i,
// GPIO direction:
output GpIo1DirOut_o,
output GpIo2DirOut_o,
......@@ -160,11 +84,30 @@ wire [31:0] WbDatStatReg_b32;
wire [31:0] Reg0Value_b32;
wire GpIo1Dir, GpIo2Dir,GpIo34Dir;
//****************************
//Fixed assignments
//****************************
assign OeSi57x_oe = 1'b1;
assign InterruptRequest_opb24 = 24'b0;
assign ResetRequest_oqp = 1'b0;
assign GpIo1Dir = 1'b0;
assign GpIo2Dir = 1'b0;
assign GpIo34Dir = 1'b0;
assign GpIo1DirOut_o = GpIo1Dir;
assign GpIo2DirOut_o = GpIo2Dir;
assign GpIo34DirOut_o = GpIo34Dir;
assign GpIo_iob4[4] = GpIo34Dir ? 1'b0 : 1'bz;
assign GpIo_iob4[3] = GpIo34Dir ? 1'b0 : 1'bz;
assign GpIo_iob4[2] = GpIo2Dir ? 1'b0 : 1'bz;
assign GpIo_iob4[1] = GpIo1Dir ? 1'b0 : 1'bz;
assign VfmcEnableN_oen = 1'b0;
//****************************
//Clocking
......@@ -258,4 +201,4 @@ Generic4InputRegs i_StatusRegs (
.Reg2Value_ib32 (32'hACDCDEAD),
.Reg3Value_ib32 (32'hFEEDBEEF));
endmodule
\ No newline at end of file
endmodule
......@@ -200,10 +200,10 @@ initial begin // MBM
wr_rst = 1'b0; // MBM
rd_rst_r = 1'b0; // MBM
wr_rst_r = 1'b0; // MBM
rd_clr = 1'b0; // MBM
wr_clr = 1'b0; // MBM
rd_clr_r = 1'b0; // MBM
wr_clr_r = 1'b0; // MBM
rd_clr = 1'b1; // MBM
wr_clr = 1'b1; // MBM
rd_clr_r = 1'b1; // MBM
wr_clr_r = 1'b1; // MBM
wr_level = 2'b0; // MBM
rd_level = 2'b0; // MBM
wp_bin_xr = {aw{1'b0}}; // MBM
......
......@@ -95,6 +95,7 @@ always @* begin
Dat_ob32 <= #dly DatWrpcSlaveBus_ib32;
Ack_o <= #dly AckWrpcSlaveBus_i;
end
default: ;
endcase
end
......
......@@ -12,8 +12,8 @@ module VfcHdSystem
// VME interface:
input VmeAs_in,
input [ 5:0] VmeAm_ib6,
inout [31:1] VmeA_iob31,
inout VmeLWord_ion,
input [31:1] VmeA_ib31,
input VmeLWord_in,
output VmeAOe_oen,
output VmeADir_o,
input [ 1:0] VmeDs_inb2,
......@@ -29,13 +29,11 @@ module VfcHdSystem
input VmeSysClk_ik,
input VmeSysReset_irn,
// System SFPs Gbit lanes:
// input BstSfpRx_i, // Comment: Differential
// output BstSfpTx_o, // Comment: Differential
input EthSfpRx_i, // Comment: Differential
output EthSfpTx_o, // Comment: Differential
// I2C Mux and IO expanders:
inout I2cMuxSda_io,
output I2cMuxScl_ok,
inout I2cMuxScl_iok,
input I2CMuxIntN0_in,
input I2CMuxIntN1_in,
input I2CIoExpIntApp12_in,
......@@ -53,16 +51,15 @@ module VfcHdSystem
output VAdcSclk_ok,
// Clock sources and control:
input GbitTrxClkRefR_ik, // Comment: Differential reference for the Gbit lines
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
// Fmc Voltage control:
output VadjCs_o,
output VadjSclk_ok,
output VadjDin_o,
output VfmcEnableN_oen,
// SW1:
input [ 4:0] NoGa_ib5,
input UseGa_i,
......@@ -73,7 +70,6 @@ module VfcHdSystem
output WrPromScl_ok,
// Specials:
inout TempIdDq_ioz,
output ResetFpgaConfigN_orn,
//@@@@@@@@@@@@@@@@@@@@@@@@@
//System-Application interface
//@@@@@@@@@@@@@@@@@@@@@@@@@
......@@ -89,16 +85,6 @@ module VfcHdSystem
output reg [31:0] WbMasterDat_ob32,
input [31:0] WbMasterDat_ib32,
input WbMasterAck_i,
input WbSlaveCyc_i,
input WbSlaveStb_i,
input [24:0] WbSlaveAdr_ib25,
input WbSlaveWr_i,
input [31:0] WbSlaveDat_ib32,
output [31:0] WbSlaveDat_ob32,
output WbSlaveAck_o,
// LED control:
input [ 1:0] TopLed_ib2,
input [ 3:0] BottomLed_ib4,
// BST output:
output BstOn_o,
output BstClk_ok,
......@@ -110,12 +96,6 @@ module VfcHdSystem
output BstByteError_o,
// Interrupt:
input [23:0] InterruptRequest_ipb24,
// Ethernet streamer:
input StreamerClk_ik,
input [31:0] StreamerData_ib32,
input SreamerDav_i,
input StreamerPckt_i,
output StreamerWait_o,
// GPIO direction:
input GpIo1DirOut_i,
input GpIo2DirOut_i,
......@@ -132,7 +112,7 @@ module VfcHdSystem
wire VmeAccess, VmeDtAck_n;
wire [ 7:1] VmeIrq_nb7;
reg [ 1:0] ResetWb_xd2 = 2'b11; // Comment: Initialised to 2'b11 for Power-On Reset
//reg [ 1:0] ResetWb_xd2 = 2'b11; // Comment: Initialised to 2'b11 for Power-On Reset
wire WbCyc, WbStb, WbWe, WbAck;
wire [21:0] WbAdr_b22;
wire [31:0] WbDatMiSo_b32, WbDatMoSi_b32;
......@@ -140,7 +120,7 @@ wire IntEnable, IntModeRoRa, IntSourceToRead, NewIntRequest;
wire [ 2:0] IntLevel_b3;
wire [ 7:0] IntVector_b8;
wire [31:0] IntRequestBus_ab32;
reg [ 1:0] VmeSysReset_d2 = 2'b11;
//reg [ 1:0] VmeSysReset_d2 = 2'b11;
wire WbAckIntManager, WbStbIntManager;
wire [31:0] WbDatMiSoIntManager_b32;
wire WbAckSpiMaster, WbStbSpiMaster;
......@@ -222,8 +202,8 @@ i_VmeInterfaceWb (
.VmeAm_ib6 (VmeAm_ib6),
.VmeWr_in (VmeWrite_in),
.VmeDtAck_on (VmeDtAck_n),
.VmeLWord_in (VmeLWord_ion),
.VmeA_ib31 (VmeA_iob31),
.VmeLWord_in (VmeLWord_in),
.VmeA_ib31 (VmeA_ib31),
.VmeD_iob32 (VmeD_iob32),
.VmeIack_in (VmeIack_in),
.VmeIackIn_in (VmeIackIn_in),
......@@ -316,7 +296,7 @@ BstDecoder i_BstDecoder (
.CdrLol_i (1'b0), // Note!! To be modified
.SfpLos_i (1'b0), // Note!! To be modified
.SfpPrsnt_i (1'b1), // Note!! To be modified
.BstByteAddr_ob8 (BstByteAddr_ob8),
.BstByteAddr_ob8 (BstByteAddress_ob8),
.BstByte_ob8 (BstByte_ob8),
.BstByteStrobe_o (BstByteStrobe_o),
.BstByteError_o (BstByteError_o),
......@@ -337,7 +317,9 @@ SpiMasterWb i_SpiMaster (
.Adr_ib3 (WbAdr_b22[2:0]),
.Dat_ib32 (WbDatMoSi_b32),
.Dat_oab32 (WbDatSpiMaster_b32),
.Ack_oa (WbAckSpiMaster),
.Ack_oa (WbAckSpiMaster),
.WaitingNewData_o(),
.ModuleIdle_o(),
.SClk_o (SpiClk_k),
.MoSi_o (SpiMoSi),
.MiSo_ib32 (SpiMiSo_b32),
......@@ -404,7 +386,7 @@ i_I2cIoExpAndMux (
.Dat_ib32 (WbDatMoSi_b32),
.Dat_oab32 (WbDatI2cIoExpAndMux_b32),
.Ack_oa (WbAckI2cIoExpAndMux),
.Scl_ioz (I2cMuxScl_ok),
.Scl_ioz (I2cMuxScl_iok),
.Sda_ioz (I2cMuxSda_io));
//*****************************
......@@ -446,6 +428,36 @@ i_I2cIoExpAndMux (
.wb_err_o (),
.wb_rty_o (),
.wb_stall_o (),
.wrf_src_adr_o (),
.wrf_src_dat_o (),
.wrf_src_cyc_o (),
.wrf_src_stb_o (),
.wrf_src_we_o (),
.wrf_src_sel_o (),
.wrf_src_ack_i (1'b0),
.wrf_src_stall_i (1'b0),
.wrf_src_err_i (1'b0),
.wrf_src_rty_i (1'b0),
.wrf_snk_adr_i (1'b0),
.wrf_snk_dat_i (1'b0),
.wrf_snk_cyc_i (1'b0),
.wrf_snk_stb_i (1'b0),
.wrf_snk_we_i (1'b0),
.wrf_snk_sel_i (1'b0),
.wrf_snk_ack_o (),
.wrf_snk_stall_o (),
.wrf_snk_err_o (),
.wrf_snk_rty_o (),
.wrs_tx_data_i (1'b0),
.wrs_tx_valid_i (1'b0),
.wrs_tx_dreq_o (),
.wrs_tx_last_i (1'b0),
.wrs_tx_flush_i (1'b0),
.wrs_rx_first_o (),
.wrs_rx_last_o (),
.wrs_rx_data_o (),
.wrs_rx_valid_o (),
.wrs_rx_dreq_i (1'b0),
.tm_time_valid_o (WrpcTmTimeValid_o),
.led_link_o (WrpcLedLink_o),
.led_act_o (WrpcLedAct_o)
......
......@@ -100,7 +100,9 @@ generic_fifo_dc_gray #(.dw(32), .aw(g_FifoAddressWidth))
.dout(IntSourceFifoOut_b32),
.re(IntSourceFifoRead),
.full(IntSourceFifoFull),
.empty(IntSourceFifoEmpty));
.empty(IntSourceFifoEmpty),
.wr_level(),
.rd_level());
assign IntSourceToRead_o = ~IntSourceFifoEmpty;
......@@ -119,4 +121,4 @@ always @(posedge Clk_ik) begin
endcase
end
endmodule
\ No newline at end of file
endmodule
......@@ -5,8 +5,8 @@ module VfcHdTop
//VME interface
input VmeAs_in,
input [5:0] VmeAm_ib6,
inout [31:1] VmeA_iob31,
inout VmeLWord_ion,
input [31:1] VmeA_ib31,
input VmeLWord_in,
output VmeAOe_oen,
output VmeADir_o,
input [1:0] VmeDs_inb2,
......@@ -22,49 +22,11 @@ module VfcHdTop
input VmeSysClk_ik,
input VmeSysReset_irn,
//SFP Gbit
input [4:1] AppSfpRx_ib4, //Differential
output [4:1] AppSfpTx_ob4, //Differential
input BstSfpRx_i, //Differential
output BstSfpTx_o, //Differential
input EthSfpRx_i, //Differential
output EthSfpTx_o, //Differential
//DDR3
output [15:0] Ddr3AA_ob16,
output [2:0] Ddr3ABa_ob3,
output Ddr3ACk_ok, //differential signals
output [1:0] Ddr3ACkE_oeb2,
output [1:0] Ddr3ACs_onb2,
output Ddr3ALdm_o,
output Ddr3AUdm_o,
output [1:0] Ddr3AOdt_ob2,
output Ddr3ARas_on,
output Ddr3ACas_on,
output Ddr3AWe_on,
output Ddr3AReset_orn,
inout [15:0] Ddr3ADq_iob16,
inout Ddr3ALdqs_io, //differential signals
inout Ddr3AUdqs_io, //differential signals
output [15:0] Ddr3BA_ob16,
output [2:0] Ddr3BBa_ob3,
output Ddr3BCk_ok, //differential signals
output [1:0] Ddr3BCkE_oeb2,
output [1:0] Ddr3BCs_onb2,
output Ddr3BLdm_o,
output Ddr3BUdm_o,
output [1:0] Ddr3BOdt_ob2,
output Ddr3BRas_on,
output Ddr3BCas_on,
output Ddr3BWe_on,
output Ddr3BReset_orn,
inout [15:0] Ddr3BDq_iob16,
inout Ddr3BLdqs_io, //differential signals
inout Ddr3BUdqs_io, //differential signals
//TestIo
inout TestIo1_io,
inout TestIo2_io,
//I2C Mux and IO expanders
inout I2cMuxSda_io,
output I2cMuxScl_ok,
inout I2cMuxScl_iok,
input I2CMuxIntN0_in,
input I2CMuxIntN1_in,
input I2CIoExpIntApp12_in,
......@@ -81,6 +43,7 @@ module VfcHdTop
output VAdcCs_o,
output VAdcSclk_ok,
//FMC connector
/* -----\/----- EXCLUDED -----\/-----
inout [33:0]FmcLaP_iob34,
inout [33:0]FmcLaN_iob34,
inout [23:0]FmcHaP_iob24,
......@@ -108,21 +71,13 @@ module VfcHdTop
input FmcGbtClk1M2CLeft_ik, //differential signal
input FmcGbtClk0M2CRight_ik, //differential signal
input FmcGbtClk1M2CRight_ik, //differential signal
-----/\----- EXCLUDED -----/\----- */
//Clock sources and control
output OeSi57x_oe,
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
inout PllRefSda_io,
output PllRefScl_ok,
inout PllRefInt_i,
output PllSourceMuxOut_ok,
input PllRefClkOut_ik, //Differential reference for the Gbit lines
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines
//Fmc Voltage control
output VadjCs_o,
......@@ -135,25 +90,13 @@ module VfcHdTop
input [1:0] Switch_ib2,
//Pcb Revision resistor network
input [7:0] PcbRev_ib7,
//P2 RTM
inout [19:0] P2DataP_iob20, //the 0 is a clock capable input
inout [19:0] P2DataN_iob20,
//P0 Timing
input [7:0] P0HwHighByte_ib8,
input [7:0] P0HwLowByte_ib8,
output DaisyChain1Cntrl_o,
output DaisyChain2Cntrl_o,
input VmeP0BunchClk_ik,
input VmeP0Tclk_ik,
//WR PROM
inout WrPromSda_io,
output WrPromScl_ok,
//GPIO
inout [4:1] GpIo_iob4,
//Miscellaneous:
input PushButtonN_in,
inout TempIdDq_ioz,
output ResetFpgaConfigN_orn
inout TempIdDq_ioz
);
//@@@@@@@@@@@@@@@@@@@
......@@ -167,15 +110,11 @@ wire [31:0] Wb1DatMosi_b32, Wb1DatMiso_b32;
wire Wb2Cyc, Wb2Stb, Wb2Wr, Wb2Ack;
wire [24:0] Wb2Adr_b25;
wire [31:0] Wb2DatMosi_b32, Wb2DatMiso_b32;
wire [1:0] TopLed_b2;
wire [3:0] BottomLed_b4;
wire BstOn, BstClk_k, BunchClkFlag, TurnClkFlag;
wire [7:0] BstByteAddress_b5;
wire [7:0] BstByteAddress_b8;
wire [7:0] BstByte_b8;
wire BstByteStrobe, BstByteError;
wire [23:0] InterruptRequest_pb24;
wire StreamerClk_k, SreamerDav, StreamerPckt, StreamerWait;
wire [31:0] StreamerData_b32;
wire GpIo1DirOut, GpIo2DirOut, GpIo34DirOut;
wire Reset_rqp, ResetRequest_qp;
......@@ -189,8 +128,8 @@ VfcHdSystem i_VfcHdSystem(
// VME interface
.VmeAs_in(VmeAs_in),
.VmeAm_ib6(VmeAm_ib6),
.VmeA_iob31(VmeA_iob31),
.VmeLWord_ion(VmeLWord_ion),
.VmeA_ib31(VmeA_ib31),
.VmeLWord_in(VmeLWord_in),
.VmeAOe_oen(VmeAOe_oen),
.VmeADir_o(VmeADir_o),
.VmeDs_inb2(VmeDs_inb2),
......@@ -205,12 +144,10 @@ VfcHdSystem i_VfcHdSystem(
.VmeIackOut_on(VmeIackOut_on),
.VmeSysClk_ik(VmeSysClk_ik),
.VmeSysReset_irn(VmeSysReset_irn),
// .BstSfpRx_i(BstSfpRx_i),
// .BstSfpTx_o(BstSfpTx_o),
.EthSfpRx_i(EthSfpRx_i),
.EthSfpTx_o(EthSfpTx_o),
.I2cMuxSda_io(I2cMuxSda_io),
.I2cMuxScl_ok(I2cMuxScl_ok),
.I2cMuxScl_iok(I2cMuxScl_iok),
.I2CMuxIntN0_in(I2CMuxIntN0_in),
.I2CMuxIntN1_in(I2CMuxIntN1_in),
.I2CIoExpIntApp12_in(I2CIoExpIntApp12_in),
......@@ -239,7 +176,6 @@ VfcHdSystem i_VfcHdSystem(
.WrPromSda_io(WrPromSda_io),
.WrPromScl_ok(WrPromScl_ok),
.TempIdDq_ioz(TempIdDq_ioz),
.ResetFpgaConfigN_orn(ResetFpgaConfigN_orn),
//CONNECTIONS SYSTAM<->APPLICATION
.Reset_orqp(Reset_rqp),
.ResetRequest_iqp(ResetRequest_qp),
......@@ -251,15 +187,6 @@ VfcHdSystem i_VfcHdSystem(
.WbMasterDat_ob32(Wb1DatMosi_b32),
.WbMasterDat_ib32(Wb1DatMiso_b32),
.WbMasterAck_i(Wb1Ack),
.WbSlaveCyc_i(Wb2Cyc),
.WbSlaveStb_i(Wb2Stb),
.WbSlaveAdr_ib25(Wb2Adr_b25),
.WbSlaveWr_i(Wb2Wr),
.WbSlaveDat_ib32(Wb2DatMosi_b32),
.WbSlaveDat_ob32(Wb2DatMiso_b32),
.WbSlaveAck_o(Wb2Ack),
.TopLed_ib2(TopLed_b2),
.BottomLed_ib4(BottomLed_b4),
.BstOn_o(BstOn),
.BstClk_ok(BstClk_k),
.BunchClkFlag_o(BunchClkFlag),
......@@ -269,11 +196,6 @@ VfcHdSystem i_VfcHdSystem(
.BstByteStrobe_o(BstByteStrobe),
.BstByteError_o(BstByteError),
.InterruptRequest_ipb24(InterruptRequest_pb24),
.StreamerClk_ik(StreamerClk_k),
.StreamerData_ib32(StreamerData_b32),
.SreamerDav_i(SreamerDav),
.StreamerPckt_i(StreamerPckt),
.StreamerWait_o(StreamerWait),
.GpIo1DirOut_i(GpIo1DirOut),
.GpIo2DirOut_i(GpIo2DirOut),
.GpIo34DirOut_i(GpIo34DirOut),
......@@ -289,32 +211,8 @@ VfcHdSystem i_VfcHdSystem(
VfcHdApplication i_VfcHdApplication
(
//DIRECT CONNECTIONS TO THE FPGA IOs
.BstSfpRx_i(BstSfpRx_i),
.BstSfpTx_o(BstSfpTx_o),
//.EthSfpRx_i(EthSfpRx_i),
//.EthSfpTx_o(EthSfpTx_o),
//---
.AppSfpRx_ib4(AppSfpRx_ib4),
.AppSfpTx_ob4(AppSfpTx_ob4),
/* .DdrBa_ob3(DdrBa_ob3),
.DdrDm_ob8(DdrDm_ob8),
.DdrDqs_iob8(DdrDqs_iob8),
.DdrDq_iob64(DdrDq_iob64),
.DdrA_ob16(DdrA_ob16),
.DdrCk_okb2(DdrCk_okb2),
.DdrCkE_ohb2(DdrCkE_ohb2),
.DdrReset_orn(DdrReset_orn),
.DdrRas_on(DdrRas_on),
.DdrCas_on(DdrCas_on),
.DdrWe_on(DdrWe_on),
.DdrCs_onb2(DdrCs_onb2),
.DdrOdt_ob2(DdrOdt_ob2),
.DdrTempEvent_in(DdrTempEvent_in),
.DdrI2cScl_ok(DdrI2cScl_ok),
.DdrI2cSda_io(DdrI2cSda_io), */
.TestIo1_io(TestIo1_io),
.TestIo2_io(TestIo2_io),
.VfmcEnableN_oen(VfmcEnableN_oen),
/* -----\/----- EXCLUDED -----\/-----
.FmcLaP_iob34(FmcLaP_iob34),
.FmcLaN_iob34(FmcLaN_iob34),
.FmcHaP_iob24(FmcHaP_iob24),
......@@ -342,32 +240,10 @@ VfcHdApplication i_VfcHdApplication
.FmcGbtClk1M2CLeft_ik(FmcGbtClk1M2CLeft_ik),