Commit abc2d57e authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev]: Connect OneWire to WR PTP core.

The connection is multiplexed with the existing OneWire master. WR PTP core has priority. In order to achieve this, the existing OneWire master interface was slightly modified to provide separately the OneWire inputs and DriverEnable signals.
parent 58d6f405
......@@ -11,8 +11,8 @@ module UniqueIdReader
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output Ack_oa,
inout OneWireBus_io);
input OneWireBus_i,
output OneWireBusDriver_o);
localparam dly = 1;
......@@ -58,13 +58,13 @@ reg [5:0] OneWireBusSynch_c6 = 0;
reg PresentFlag_q;
always @(posedge Clk_ik)
if (OneWireBus_io==OneWireBusSynch_q) OneWireBusSynch_c6 <= #dly 'h0;
if (OneWireBus_i==OneWireBusSynch_q) OneWireBusSynch_c6 <= #dly 'h0;
else OneWireBusSynch_c6 <= #dly OneWireBusSynch_c6 + 1'b1;
always @(posedge Clk_ik)
if (&OneWireBusSynch_c6)OneWireBusSynch_q <= #dly OneWireBus_io;
if (&OneWireBusSynch_c6)OneWireBusSynch_q <= #dly OneWireBus_i;
assign OneWireBus_io = OeBusDriver ? 1'b0 : 1'bz;
assign OneWireBusDriver_o = OeBusDriver;
always @(posedge Clk_ik)
if (Rst_irq) CommandReg_b32 <= #dly 'h0000_abcd;
......@@ -206,7 +206,7 @@ always @(posedge Clk_ik)
endcase
always @* case (Adr_ib2)
c_StatusRegAddress_b2: Dat_oab32 = {PresentFlag_q, OeBusDriver, OneWireBusSynch_q, OneWireBus_io, State_q, UsCounter_c9[7:0], ShReg_b16};
c_StatusRegAddress_b2: Dat_oab32 = {PresentFlag_q, OeBusDriver, OneWireBusSynch_q, OneWireBus_i, State_q, UsCounter_c9[7:0], ShReg_b16};
c_CommandRegAddress_b2: Dat_oab32 = CommandReg_b32;
default: Dat_oab32 = 32'hdeadbeef;
endcase
......
......@@ -159,9 +159,11 @@ reg [ 1:0] WbAckAppSlaveBus_xd2;
wire [ 4:0] VmeGa_b5; // Comment: Need to be accessed from the I2C exp
wire VmeGap_n; // Comment: Need to be accessed from the I2C exp
//reg Reset_rq;
wire WbStbWrpcSlaveBus;
wire TempIdDqIn, TempIdDqDriver;
wire WrOwrIn, WrOwrOutEn;
wire WbStbWrpcSlaveBus;
wire [31:0] WbDatWrpcSlaveBus_b32;
wire WbAckWrpcSlaveBus;
wire WbAckWrpcSlaveBus;
wire [31:0] WbAdr_b32;
//****************************
......@@ -357,16 +359,17 @@ assign VAdcSclk_ok = SpiClk_k;
UniqueIdReader #(
.g_OneUsClkCycles(125))
i_UniqueIdReader (
.Rst_irq (Reset_rq),
.Clk_ik (Clk_k),
.Cyc_i (WbCyc),
.Stb_i (WbStbUniqueIdReader),
.We_i (WbWe),
.Adr_ib2 (WbAdr_b22[1:0]),
.Dat_ib32 (WbDatMoSi_b32),
.Dat_oab32 (WbDatUniqueIdReader_b32),
.Ack_oa (WbAckUniqueIdReader),
.OneWireBus_io (TempIdDq_ioz));
.Rst_irq (Reset_rq),
.Clk_ik (Clk_k),
.Cyc_i (WbCyc),
.Stb_i (WbStbUniqueIdReader),
.We_i (WbWe),
.Adr_ib2 (WbAdr_b22[1:0]),
.Dat_ib32 (WbDatMoSi_b32),
.Dat_oab32 (WbDatUniqueIdReader_b32),
.Ack_oa (WbAckUniqueIdReader),
.OneWireBus_i (TempIdDqIn),
.OneWireBusDriver_o (TempIdDqDriver));
//****************************
//IO EXP and MUX
......@@ -424,6 +427,8 @@ i_I2cIoExpAndMux (
.sfp_rx_i (EthSfpRx_i),
.eeprom_sda_b (WrPromSda_io),
.eeprom_scl_o (WrPromScl_ok),
.onewire_i (WrOwrIn),
.onewire_oen_o (WrOwrOutEn),
.wb_adr_i (WbAdr_b32),
.wb_dat_i (WbDatMoSi_b32),
.wb_dat_o (WbDatWrpcSlaveBus_b32),
......@@ -441,6 +446,12 @@ i_I2cIoExpAndMux (
.led_act_o (WrpcLedAct_o)
);
// Multiplex onewire access between WR PTP core and
// existing OneWire master. WR core has priority.
assign WrOwrIn = TempIdDq_ioz;
assign TempIdDqIn = TempIdDq_ioz;
assign TempIdDq_ioz = WrOwrOutEn ? 1'b0 : (TempIdDqDriver ? 1'b0 : 1'bZ);
assign WbAdr_b32 = {10'h00, WbAdr_b22};
//****************************
......
wr-cores @ fd220473
Subproject commit c7e7ea62a9daa27b57f6fc97ccaacbc0233501cb
Subproject commit fd220473419e2f5b64b1039fb831050692cb77a6
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