Commit bd040521 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev]: Remove 100MHz clock from default sys_pll, the PHY reconf module of...

[WR-dev]: Remove 100MHz clock from default sys_pll, the PHY reconf module of the ArriaV can work with 125MHz as well. Also fix timing constraints after renaming of module instantiations
parent 37654f74
...@@ -116,7 +116,6 @@ architecture struct of WrpcWrapper is ...@@ -116,7 +116,6 @@ architecture struct of WrpcWrapper is
-- PLLs -- PLLs
signal pll_clk_62m5 : std_logic; signal pll_clk_62m5 : std_logic;
signal pll_clk_125m : std_logic; signal pll_clk_125m : std_logic;
signal pll_clk_100m : std_logic;
signal pll_clk_dmtd : std_logic; signal pll_clk_dmtd : std_logic;
signal pll_sys_locked : std_logic; signal pll_sys_locked : std_logic;
signal pll_dmtd_locked : std_logic; signal pll_dmtd_locked : std_logic;
...@@ -167,7 +166,6 @@ begin -- architecture struct ...@@ -167,7 +166,6 @@ begin -- architecture struct
rst => arst_i, rst => arst_i,
outclk_0 => pll_clk_62m5, outclk_0 => pll_clk_62m5,
outclk_1 => pll_clk_125m, outclk_1 => pll_clk_125m,
outclk_2 => pll_clk_100m,
locked => pll_sys_locked); locked => pll_sys_locked);
clk_sys_62m5_o <= pll_clk_62m5; clk_sys_62m5_o <= pll_clk_62m5;
...@@ -237,7 +235,7 @@ begin -- architecture struct ...@@ -237,7 +235,7 @@ begin -- architecture struct
cmp_phy : wr_arria5_phy cmp_phy : wr_arria5_phy
port map ( port map (
clk_reconf_i => pll_clk_100m, clk_reconf_i => pll_clk_125m,
clk_phy_i => pll_clk_125m, clk_phy_i => pll_clk_125m,
locked_o => gxb_locked, locked_o => gxb_locked,
loopen_i => phy_loopen, loopen_i => phy_loopen,
......
wr-cores @ 811b35de
Subproject commit 70fca459aac89daec66f63ce85d75c60abfe6519 Subproject commit 811b35de37a6a3e3564d6a33ef3a02a39c3a31d6
...@@ -78,20 +78,19 @@ derive_clock_uncertainty ...@@ -78,20 +78,19 @@ derive_clock_uncertainty
#************************************************************** #**************************************************************
# splitting of PHY clocks based on pexarria5 project from GSI # splitting of PHY clocks based on pexarria5 project from GSI
set_clock_groups -asynchronous \ set_clock_groups -asynchronous \
-group { GbitTrxClkRefR_ik \ -group { GbitTrxClkRefR_ik \
i_VfcHdSystem|i_WrpcWrapper|cmp_AlteraPllSys|*|general[0]* \ i_VfcHdSystem|i_WrpcWrapper|cmp_pll_sys|*|general[0]* \
i_VfcHdSystem|i_WrpcWrapper|cmp_AlteraPllSys|*|general[1]* } \ i_VfcHdSystem|i_WrpcWrapper|cmp_pll_sys|*|general[1]* } \
-group { i_VfcHdSystem|i_WrpcWrapper|cmp_AlteraPllSys|*|general[2]* } \ -group { Clk20VCOx_ik \
-group { Clk20VCOx_ik \ i_VfcHdSystem|i_WrpcWrapper|cmp_pll_dmtd|* } \
i_VfcHdSystem|i_WrpcWrapper|cmp_AlteraPllDmtd|* } \ -group { i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*.cdr_refclk* \
-group { i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*.cdr_refclk* \ i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*.cmu_pll.* \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*.cmu_pll.* \ i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|av_tx_pma|* \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|av_tx_pma|* \ i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|inst_av_pcs|*|tx* } \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|inst_av_pcs|*|tx* } \ -group { i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|clk90bdes \
-group { i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|clk90bdes \ i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|clk90b \
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|clk90b \ i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|rcvdclkpma }
i_VfcHdSystem|i_WrpcWrapper|cmp_phy|*|rcvdclkpma }
#************************************************************** #**************************************************************
# Set False Path # Set False Path
......
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