Commit bde1f865 authored by Manoel Barros Marin's avatar Manoel Barros Marin
Browse files

- Added old and new Vme Int

parent 01d06d7e
......@@ -63,7 +63,7 @@ wire [31:0] IntSourceFifoOut_b32;
wire IntSourceFifoFull, IntSourceFifoEmpty;
reg IntSourceFifoRead;
reg [31:0] ConfigReg_bq32 = 32'hFF;
reg [31:0] MaskReg_bq32 = 32'hFFFF_FFFF;
reg [31:0] MaskReg_bq32 = 32'hFF;
assign IntLevel_ob3 = ConfigReg_bq32[22:20];
assign IntVector_ob8 = ConfigReg_bq32[19:12];
......
......@@ -7,7 +7,7 @@ module VmeInterfaceWb
(
input Clk_ik,
input Rst_irq,
input [4:0] VmeGa_ib5,
input VmeGap_in,
input VmeAs_in,
......@@ -52,7 +52,7 @@ localparam s_Idle = 3'd0,
s_IntAck = 3'd5,
s_IAckPass = 3'd6;
reg [13:0] WbTimeoutCounter_c14 = 0;
reg [7:0] WbTimeoutCounter_c8 = 0;
reg [7:0] IntToAckCounter_c8 = 0;
reg [9:0] RoraTimeoutCounter_c10 = 10'h3ff;
reg [31:0] InternalDataReg_b31 = 'h0;
......@@ -69,29 +69,28 @@ wire a_VmeAsSynch = VmeAsShReg_b3[1];
reg [2:0] VmeDs0ShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeDs0ShReg_b3 <= #1 {VmeDs0ShReg_b3[1:0], VmeDs_inb2[0]};
wire NegedgeVmeDs0_a = VmeDs0ShReg_b3[2:1]==2'b10;
wire a_VmeDs0Synch = VmeDs0ShReg_b3[1];
reg [2:0] VmeDs1ShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeDs1ShReg_b3 <= #1 {VmeDs1ShReg_b3[1:0], VmeDs_inb2[1]};
wire NegedgeVmeDs1_a = VmeDs1ShReg_b3[2:1]==2'b10;
wire a_VmeDs1Synch = VmeDs1ShReg_b3[1];
reg [2:0] VmeIackInShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeIackInShReg_b3 <= #1 {VmeIackInShReg_b3[1:0], VmeIackIn_in};
wire a_VmeIackInSynch = VmeIackInShReg_b3[1];
reg [2:0] VmeIackShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeIackShReg_b3 <= #1 {VmeIackShReg_b3[1:0], VmeIack_in};
wire a_VmeIackSynch = VmeIackShReg_b3[1];
//#####################################
// Access recognition signals
//#####################################
wire VmeGaPError_a = ^{VmeGa_ib5, ~VmeGap_in};
wire VmeAmValid_a = (VmeAm_ib6==6'h0B) || (VmeAm_ib6==6'h09);
wire VmeValidBaseAddr_a = (~VmeGaPError_a) && (VmeA_ib31[31:g_LowestGaAddressBit]=={ {(26-g_LowestGaAddressBit){1'b0}}, ~VmeGa_ib5});
wire VmeRWAccess_a = ~a_VmeAsSynch && ~a_VmeDs0Synch && ~a_VmeDs1Synch && ~VmeLWord_in && VmeAmValid_a && VmeIack_in && VmeValidBaseAddr_a;
wire VmeIackCycle_a = ~a_VmeAsSynch && ~(a_VmeDs0Synch&&a_VmeDs1Synch) && ~a_VmeIackSynch;
wire VmeGaPError_a = ^{VmeGa_ib5, ~VmeGap_in};
wire VmeAmValid_a = (VmeAm_ib6==6'h0B) || (VmeAm_ib6==6'h09);
wire VmeRWAccess_a = ~a_VmeAsSynch && ~a_VmeDs0Synch && ~a_VmeDs1Synch && ~VmeLWord_in && VmeAmValid_a && VmeIack_in && (~VmeGaPError_a) && (VmeA_ib31[31:g_LowestGaAddressBit]=={ {(26-g_LowestGaAddressBit){1'b0}}, ~VmeGa_ib5});
//wire VmeIackCycle_a = ~a_VmeAsSynch && ~(a_VmeDs0Synch&&a_VmeDs1Synch) && ~a_VmeIackInSynch;
wire VmeIackCycle_a = ~a_VmeAsSynch && ~(a_VmeDs0Synch&&a_VmeDs1Synch) && ~VmeIack_in;
//#####################################
//State Machine
......@@ -108,25 +107,24 @@ always @* begin
if (VmeWr_in) NextState_ab3 = s_RdWaitWbAnswer;
else NextState_ab3 = s_WrCloseVmeCycle;
end else if (VmeIackCycle_a) begin
if (VmeIrq_onb7[VmeA_ib31[3:1]]==1'b1 ) NextState_ab3 = s_IAckPass;
else if (a_VmeIackInSynch==1'b0) begin
if (VmeIrq_onb7[VmeA_ib31[3:1]]==1'b1) NextState_ab3 = s_IAckPass;
else if (a_VmeIackInSynch) begin
if (~IntModeRora_i) NextState_ab3 = s_IntAck;
else if (&RoraTimeoutCounter_c10) NextState_ab3 = s_IntAck;
else NextState_ab3 = s_IAckPass;
end
end
s_RdWaitWbAnswer:
if (WbAck_i || &WbTimeoutCounter_c14) NextState_ab3 = s_RdCloseVmeCycle;
if (WbAck_i || &WbTimeoutCounter_c8) NextState_ab3 = s_RdCloseVmeCycle;
s_RdCloseVmeCycle:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_Idle;
s_WrCloseVmeCycle:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_WrWaitWbAnswer;
s_WrWaitWbAnswer:
if (WbAck_i || &WbTimeoutCounter_c14) NextState_ab3 = s_Idle;
if (WbAck_i || &WbTimeoutCounter_c8) NextState_ab3 = s_Idle;
s_IntAck:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_Idle;
s_IAckPass:
if (a_VmeIackInSynch) NextState_ab3 = s_Idle;
s_IAckPass:
if (VmeIackIn_in) NextState_ab3 = s_Idle;
default: NextState_ab3 = s_Idle;
endcase
end
......@@ -143,6 +141,7 @@ always @(posedge Clk_ik) begin
VmeIackOut_on <= #1 1'b1;
VmeIrq_onb7 <= #1 7'b1111111;
VmeDataBuffsOutEnable_e <= #1 1'b0;
// VmeDataBuffsOutMode_o <= #1 1'b0;
VmeAccess_o <= #1 1'b0;
VmeDtAck_on <= #1 1'b1;
WbCyc_o <= #1 1'b0;
......@@ -154,12 +153,13 @@ always @(posedge Clk_ik) begin
RoraTimeoutCounter_c10 <= #1 10'h3ff;
InternalDataReg_b31 <= #1 'h0;
VmeAddressInternal_b30 <= #1 'h0;
WbTimeoutCounter_c14 <= #1 'h0;
WbTimeoutCounter_c8 <= #1 'h0;
end else begin
//default assignments applyed in all states if not differently specified
VmeIackOut_on <= #1 1'b1;
VmeIrq_onb7 <= #1 7'b1111111;
VmeDataBuffsOutEnable_e <= #1 1'b0;
// VmeDataBuffsOutMode_o <= #1 1'b0;
VmeAccess_o <= #1 1'b0;
VmeDtAck_on <= #1 1'b1;
if (NegedgeVmeAs_a) VmeAddressInternal_b30 <= #1 VmeA_ib31[31:2];
......@@ -178,7 +178,7 @@ always @(posedge Clk_ik) begin
WbCyc_o <= #1 1'b0;
WbStb_o <= #1 1'b0;
WbWe_o <= #1 1'b0;
WbTimeoutCounter_c14 <= #1 'h0;
WbTimeoutCounter_c8 <= #1 'h0;
//state dependent assignments
case(State_qb3)
s_Idle: begin
......@@ -197,23 +197,25 @@ always @(posedge Clk_ik) begin
end
s_RdWaitWbAnswer: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
// VmeDataBuffsOutMode_o <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
WbCyc_o <= #1 1'b1;
WbStb_o <= #1 1'b1;
WbWe_o <= #1 1'b0;
WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
WbTimeoutCounter_c8 <= #1 WbTimeoutCounter_c8 + 1'b1;
if (WbAck_i) InternalDataReg_b31 <= #1 WbDat_ib32;
else if (&WbTimeoutCounter_c14) InternalDataReg_b31 <= #1 32'hFFFF_FFFF;
else if (&WbTimeoutCounter_c8) InternalDataReg_b31 <= #1 32'hFFFF_FFFF;
end
s_RdCloseVmeCycle: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
// VmeDataBuffsOutMode_o <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
VmeDtAck_on <= #1 1'b0;
if (NextState_ab3==s_Idle && VmeAm_ib6==6'h0B) VmeAddressInternal_b30 <= #1 VmeAddressInternal_b30 + 1'b1;
end
s_WrCloseVmeCycle: begin
VmeAccess_o <= #1 1'b1;
if (WbTimeoutCounter_c14==14'h1) begin
if (WbTimeoutCounter_c8==8'h1) begin
VmeDtAck_on <= #1 1'b0; //delaying of 1 cycle extra
WbDat_ob32 <= #1 VmeD_iob32;
WbCyc_o <= #1 1'b1;
......@@ -226,7 +228,7 @@ always @(posedge Clk_ik) begin
WbWe_o <= #1 WbWe_o;
WbStb_o <= #1 WbStb_o;
end
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (~WbAck_i) WbTimeoutCounter_c8 <= #1 WbTimeoutCounter_c8 + 1'b1;
if (NextState_ab3==s_WrWaitWbAnswer && VmeAm_ib6==6'h0B) VmeAddressInternal_b30 <= #1 VmeAddressInternal_b30 + 1'b1;
end
s_WrWaitWbAnswer: begin
......@@ -240,13 +242,14 @@ always @(posedge Clk_ik) begin
WbWe_o <= #1 WbWe_o;
WbStb_o <= #1 WbStb_o;
end
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (~WbAck_i) WbTimeoutCounter_c8 <= #1 WbTimeoutCounter_c8 + 1'b1;
end
s_IntAck: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
// VmeDataBuffsOutMode_o <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (WbTimeoutCounter_c14==14'h7) VmeDtAck_on <= #1 1'b0; //delaying of 2 cycle extra
if (~WbAck_i) WbTimeoutCounter_c8 <= #1 WbTimeoutCounter_c8 + 1'b1;
if (WbTimeoutCounter_c8==8'h7) VmeDtAck_on <= #1 1'b0; //delaying of 2 cycle extra
else VmeDtAck_on <= #1 VmeDtAck_on;
if (NextState_ab3 == s_Idle) begin
if (IntModeRora_i) RoraTimeoutCounter_c10 <= #1 'h0;
......@@ -254,7 +257,7 @@ always @(posedge Clk_ik) begin
end
end
s_IAckPass: begin
VmeIackOut_on <= #1 a_VmeIackInSynch;
VmeIackOut_on <= #1 VmeIackIn_in;
end
default: begin
end
......
/*
The module support 32 interrupt sources. Each source can be masked individually. The Interrupt requests are assumed synchronous to the clock. A new request is registered
each time there is a change of state on its line from 0 to 1.
The interrupt release meachanism can be set dynamically to ROACK or RORA. In this last case the register to read to compleate the release mechanism is the fpga_status_reg.
The interrupts are prioritized by arrival time: a 8 location deep FIFO is used to store them. If 2 or more interrupt requests
are asserted at the same time they are store all asserted in the FIFO at the same location and will appear as multiple bit set in the status register, that is actually a copy of the
FIFO output and is cleared at each readout as at the same time a read request is sent to the FIFO itself.
The module has a configuration register, a status register where the source of the current interrupt can be read, a mask register (a 1 in bin n mask the interrupt source n) and a release ID register
Status register (Addr:0x0) :
bits[31:0] = interrupt source => reading this register also advances the pointer of the interrupt FIFO and therefore it should be read only once per interrupt
Configuration Register (Addr:0x1)
bits[31:24] = 0
bits[23] = 0
bits[22:20] = Interrupt Level
bits[19:12] = Interrupt Vector
bit[11] = IntEnabele => Enables the interrupt handling
bit[10:9] = 0
bit[8] = RoraMode => a 1 set the module into RORA mode (int line released on the readout of the Status register), a 0 in ROAK
bits[7:0] = 0
*/
`timescale 1ns/100ps
module InterruptManagerWb
#(parameter g_FpgaVersion_b8 = 8'hab,
parameter g_ReleaseDay_b8 = 8'h07,
parameter g_ReleaseMonth_b8 = 8'h04,
parameter g_ReleaseYear_b8 = 8'h75,
parameter g_FifoAddressWidth = 3)
(
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output reg Ack_oa,
input [31:0] IntRequestLines_ib32,
output IntEnable_o,
output IntModeRora_o,
output [2:0] IntLevel_ob3,
output [7:0] IntVector_ob8,
output IntSourceToRead_o, //Used for RORA
output reg NewIntRequest_oqp //Used for ROAK
);
localparam c_StatusRegAddr_b2 = 2'b00;
localparam c_ConfigRegAddr_b2 = 2'b01;
localparam c_MaskRegAddr_b2 = 2'b10;
localparam c_FirmwareRelease_b2 = 2'b11;
reg Ack_d = 0;
wire [31:0] IntSourceFifoOut_b32;
wire IntSourceFifoFull, IntSourceFifoEmpty;
reg IntSourceFifoRead;
reg [31:0] ConfigReg_bq32 = 32'hFF;
reg [31:0] MaskReg_bq32 = 32'hFFFF_FFFF;
assign IntLevel_ob3 = ConfigReg_bq32[22:20];
assign IntVector_ob8 = ConfigReg_bq32[19:12];
assign IntEnable_o = ConfigReg_bq32[11];
assign IntModeRora_o = ConfigReg_bq32[8];
wire [31:0] IntRequestMasked_b32 = IntRequestLines_ib32 & ~MaskReg_bq32;
reg [31:0] IntRequestMasked_db32 = 32'hFFFFFFFF;
reg [31:0] IntRequestSource_b32 = 32'h0;
always @(posedge Clk_ik) IntRequestMasked_db32 <= #1 IntRequestMasked_b32;
always @(posedge Clk_ik) IntRequestSource_b32 <= #1 IntRequestMasked_b32 & ~IntRequestMasked_db32;
always @(posedge Clk_ik) NewIntRequest_oqp <= #1 ~IntSourceFifoFull && IntEnable_o && |(IntRequestMasked_b32 & ~IntRequestMasked_db32);
always @(posedge Clk_ik)
if (Rst_irq) ConfigReg_bq32 <= # 1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==c_ConfigRegAddr_b2) ConfigReg_bq32 <= # 1 Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) MaskReg_bq32 <= # 1 32'hffffffff;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==c_MaskRegAddr_b2) MaskReg_bq32 <= # 1 Dat_ib32;
wire IntSourceFifoReset = Rst_irq || ~IntEnable_o;
generic_fifo_dc_gray #(.dw(32), .aw(g_FifoAddressWidth))
i_IntSourceFifo (
.rd_clk(Clk_ik),
.wr_clk(Clk_ik),
.rst(1'b1),
.clr(IntSourceFifoReset),
.din(IntRequestSource_b32),
.we(NewIntRequest_oqp),
.dout(IntSourceFifoOut_b32),
.re(IntSourceFifoRead),
.full(IntSourceFifoFull),
.empty(IntSourceFifoEmpty));
assign IntSourceToRead_o = ~IntSourceFifoEmpty;
always @(posedge Clk_ik) IntSourceFifoRead <= #1 ~IntSourceFifoEmpty && (Adr_ib2==c_StatusRegAddr_b2) && Ack_d && ~Ack_oa;
always @(posedge Clk_ik) begin
Ack_oa <= #1 Stb_i&&Cyc_i;
Ack_d <= #1 Ack_oa;
case(Adr_ib2)
c_StatusRegAddr_b2 : Dat_oab32 <= #1 IntSourceFifoEmpty ? 32'h0000_0000 : IntSourceFifoOut_b32;
c_ConfigRegAddr_b2 : Dat_oab32 <= #1 ConfigReg_bq32;
c_MaskRegAddr_b2 : Dat_oab32 <= #1 MaskReg_bq32;
c_FirmwareRelease_b2 : Dat_oab32 <= #1 {g_FpgaVersion_b8, g_ReleaseDay_b8, g_ReleaseMonth_b8, g_ReleaseYear_b8};
default: Dat_oab32 <= 32'hdead_beef;
endcase
end
endmodule
\ No newline at end of file
`timescale 1ns/1ns
module VmeInterfaceWb
#(
parameter g_LowestGaAddressBit = 24,
parameter g_ClocksIn2us = 80_000)
(
input Clk_ik,
input Rst_irq,
input [4:0] VmeGa_ib5,
input VmeGap_in,
input VmeAs_in,
input [1:0] VmeDs_inb2,
input [5:0] VmeAm_ib6,
input VmeWr_in,
output reg VmeDtAck_on,
input VmeLWord_in,
input [31:1] VmeA_ib31,
inout [31:0] VmeD_iob32,
input VmeIack_in,
input VmeIackIn_in,
output reg VmeIackOut_on,
output reg [7:1] VmeIrq_onb7,
output VmeDataBuffsOutMode_o, // request to set the data buffers direction to Board -> VME
output reg VmeAccess_o, //Output active during Vme Access recognized by the board
input IntEnable_i,
input IntModeRora_i,
input [2:0] IntLevel_ib3,
input [7:0] IntVector_ib8,
input IntSourceToRead_i, //Used for RORA
input NewIntRequest_iqp, //Used for ROAK
output reg WbCyc_o,
output reg WbStb_o,
output reg WbWe_o,
output reg [g_LowestGaAddressBit-3:0] WbAdr_ob,
input [31:0] WbDat_ib32,
output reg [31:0] WbDat_ob32,
input WbAck_i);
reg [2:0] State_qb3, NextState_ab3;
localparam s_Idle = 3'd0,
s_RdWaitWbAnswer = 3'd1,
s_RdCloseVmeCycle = 3'd2,
s_WrCloseVmeCycle = 3'd3,
s_WrWaitWbAnswer = 3'd4,
s_IntAck = 3'd5,
s_IAckPass = 3'd6;
reg [13:0] WbTimeoutCounter_c14 = 0;
reg [7:0] IntToAckCounter_c8 = 0;
reg [9:0] RoraTimeoutCounter_c10 = 10'h3ff;
reg [31:0] InternalDataReg_b31 = 'h0;
reg [31:2] VmeAddressInternal_b30 = 'h0;
//#####################################
// Strobe Signals Synchronization
//#####################################
reg [2:0] VmeAsShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeAsShReg_b3 <= #1 {VmeAsShReg_b3[1:0], VmeAs_in};
wire NegedgeVmeAs_a = VmeAsShReg_b3[2:1]==2'b10;
wire a_VmeAsSynch = VmeAsShReg_b3[1];
reg [2:0] VmeDs0ShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeDs0ShReg_b3 <= #1 {VmeDs0ShReg_b3[1:0], VmeDs_inb2[0]};
wire a_VmeDs0Synch = VmeDs0ShReg_b3[1];
reg [2:0] VmeDs1ShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeDs1ShReg_b3 <= #1 {VmeDs1ShReg_b3[1:0], VmeDs_inb2[1]};
wire a_VmeDs1Synch = VmeDs1ShReg_b3[1];
reg [2:0] VmeIackInShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeIackInShReg_b3 <= #1 {VmeIackInShReg_b3[1:0], VmeIackIn_in};
wire a_VmeIackInSynch = VmeIackInShReg_b3[1];
reg [2:0] VmeIackShReg_b3 = 3'b111;
always @(posedge Clk_ik) VmeIackShReg_b3 <= #1 {VmeIackShReg_b3[1:0], VmeIack_in};
wire a_VmeIackSynch = VmeIackShReg_b3[1];
//#####################################
// Access recognition signals
//#####################################
wire VmeGaPError_a = ^{VmeGa_ib5, ~VmeGap_in};
wire VmeAmValid_a = (VmeAm_ib6==6'h0B) || (VmeAm_ib6==6'h09);
wire VmeValidBaseAddr_a = (~VmeGaPError_a) && (VmeA_ib31[31:g_LowestGaAddressBit]=={ {(26-g_LowestGaAddressBit){1'b0}}, ~VmeGa_ib5});
wire VmeRWAccess_a = ~a_VmeAsSynch && ~a_VmeDs0Synch && ~a_VmeDs1Synch && ~VmeLWord_in && VmeAmValid_a && VmeIack_in && VmeValidBaseAddr_a;
wire VmeIackCycle_a = ~a_VmeAsSynch && ~(a_VmeDs0Synch&&a_VmeDs1Synch) && ~a_VmeIackSynch;
//#####################################
//State Machine
//#####################################
always @(posedge Clk_ik) State_qb3 <= #1 NextState_ab3;
always @* begin
NextState_ab3 = State_qb3;
if (Rst_irq) NextState_ab3 = s_Idle;
else case(State_qb3)
s_Idle:
if (VmeRWAccess_a && ~WbAck_i) begin
if (VmeWr_in) NextState_ab3 = s_RdWaitWbAnswer;
else NextState_ab3 = s_WrCloseVmeCycle;
end else if (VmeIackCycle_a) begin
if (VmeIrq_onb7[VmeA_ib31[3:1]]==1'b1 ) NextState_ab3 = s_IAckPass;
else if (a_VmeIackInSynch==1'b0) begin
if (~IntModeRora_i) NextState_ab3 = s_IntAck;
else if (&RoraTimeoutCounter_c10) NextState_ab3 = s_IntAck;
else NextState_ab3 = s_IAckPass;
end
end
s_RdWaitWbAnswer:
if (WbAck_i || &WbTimeoutCounter_c14) NextState_ab3 = s_RdCloseVmeCycle;
s_RdCloseVmeCycle:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_Idle;
s_WrCloseVmeCycle:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_WrWaitWbAnswer;
s_WrWaitWbAnswer:
if (WbAck_i || &WbTimeoutCounter_c14) NextState_ab3 = s_Idle;
s_IntAck:
if (a_VmeDs0Synch && a_VmeDs1Synch) NextState_ab3 = s_Idle;
s_IAckPass:
if (a_VmeIackInSynch) NextState_ab3 = s_Idle;
default: NextState_ab3 = s_Idle;
endcase
end
reg VmeDataBuffsOutEnable_e = 0;
assign VmeD_iob32 = VmeDataBuffsOutEnable_e ? InternalDataReg_b31 : 32'hZZZZZZZZ;
assign VmeDataBuffsOutMode_o = VmeWr_in;
always @(posedge Clk_ik) begin
//reset conditions/assignments
if (Rst_irq) begin
VmeIackOut_on <= #1 1'b1;
VmeIrq_onb7 <= #1 7'b1111111;
VmeDataBuffsOutEnable_e <= #1 1'b0;
VmeAccess_o <= #1 1'b0;
VmeDtAck_on <= #1 1'b1;
WbCyc_o <= #1 1'b0;
WbStb_o <= #1 1'b0;
WbWe_o <= #1 1'b0;
WbAdr_ob <= #1 'h0;
WbDat_ob32 <= #1 'h0;
IntToAckCounter_c8 <= #1 'h0;
RoraTimeoutCounter_c10 <= #1 10'h3ff;
InternalDataReg_b31 <= #1 'h0;
VmeAddressInternal_b30 <= #1 'h0;
WbTimeoutCounter_c14 <= #1 'h0;
end else begin
//default assignments applyed in all states if not differently specified
VmeIackOut_on <= #1 1'b1;
VmeIrq_onb7 <= #1 7'b1111111;
VmeDataBuffsOutEnable_e <= #1 1'b0;
VmeAccess_o <= #1 1'b0;
VmeDtAck_on <= #1 1'b1;
if (NegedgeVmeAs_a) VmeAddressInternal_b30 <= #1 VmeA_ib31[31:2];
if (IntEnable_i) begin
if (NewIntRequest_iqp) IntToAckCounter_c8 <= #1 IntToAckCounter_c8 + 1'b1;
if (IntModeRora_i) begin
if (IntSourceToRead_i) VmeIrq_onb7[IntLevel_ib3] <= #1 1'b0;
end else begin
if (|IntToAckCounter_c8) VmeIrq_onb7[IntLevel_ib3] <= #1 1'b0;
end
end else begin
IntToAckCounter_c8 <= #1 'h0;
end
if (RoraTimeoutCounter_c10==g_ClocksIn2us) RoraTimeoutCounter_c10 <= #1 10'h3ff;
else if (~&RoraTimeoutCounter_c10) RoraTimeoutCounter_c10 <= #1 RoraTimeoutCounter_c10 + 1'b1;
WbCyc_o <= #1 1'b0;
WbStb_o <= #1 1'b0;
WbWe_o <= #1 1'b0;
WbTimeoutCounter_c14 <= #1 'h0;
//state dependent assignments
case(State_qb3)
s_Idle: begin
if (NextState_ab3 == s_RdWaitWbAnswer) begin
VmeAccess_o <= #1 1'b1;
if (NegedgeVmeAs_a) WbAdr_ob <= #1 VmeA_ib31[g_LowestGaAddressBit-1:2];
else WbAdr_ob <= #1 VmeAddressInternal_b30[g_LowestGaAddressBit-1:2];
end else if (NextState_ab3 == s_WrCloseVmeCycle) begin
VmeAccess_o <= #1 1'b1;
if (NegedgeVmeAs_a) WbAdr_ob <= #1 VmeA_ib31[g_LowestGaAddressBit-1:2];
else WbAdr_ob <= #1 VmeAddressInternal_b30[g_LowestGaAddressBit-1:2];
end else if (NextState_ab3 == s_IntAck) begin
VmeAccess_o <= #1 1'b1;
InternalDataReg_b31 <= #1 {24'h0, IntVector_ib8};
end
end
s_RdWaitWbAnswer: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
WbCyc_o <= #1 1'b1;
WbStb_o <= #1 1'b1;
WbWe_o <= #1 1'b0;
WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (WbAck_i) InternalDataReg_b31 <= #1 WbDat_ib32;
else if (&WbTimeoutCounter_c14) InternalDataReg_b31 <= #1 32'hFFFF_FFFF;
end
s_RdCloseVmeCycle: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
VmeDtAck_on <= #1 1'b0;
if (NextState_ab3==s_Idle && VmeAm_ib6==6'h0B) VmeAddressInternal_b30 <= #1 VmeAddressInternal_b30 + 1'b1;
end
s_WrCloseVmeCycle: begin
VmeAccess_o <= #1 1'b1;
if (WbTimeoutCounter_c14==14'h1) begin
VmeDtAck_on <= #1 1'b0; //delaying of 1 cycle extra
WbDat_ob32 <= #1 VmeD_iob32;
WbCyc_o <= #1 1'b1;
WbWe_o <= #1 1'b1;
WbStb_o <= #1 1'b1;
end else begin
VmeDtAck_on <= #1 VmeDtAck_on;
WbDat_ob32 <= #1 WbDat_ob32;
WbCyc_o <= #1 WbCyc_o;
WbWe_o <= #1 WbWe_o;
WbStb_o <= #1 WbStb_o;
end
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (NextState_ab3==s_WrWaitWbAnswer && VmeAm_ib6==6'h0B) VmeAddressInternal_b30 <= #1 VmeAddressInternal_b30 + 1'b1;
end
s_WrWaitWbAnswer: begin
VmeAccess_o <= #1 1'b0;
if (WbAck_i) begin
WbCyc_o <= #1 1'b0;
WbWe_o <= #1 1'b0;
WbStb_o <= #1 1'b0;
end else begin
WbCyc_o <= #1 WbCyc_o;
WbWe_o <= #1 WbWe_o;
WbStb_o <= #1 WbStb_o;
end
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
end
s_IntAck: begin
VmeDataBuffsOutEnable_e <= #1 1'b1;
VmeAccess_o <= #1 1'b1;
if (~WbAck_i) WbTimeoutCounter_c14 <= #1 WbTimeoutCounter_c14 + 1'b1;
if (WbTimeoutCounter_c14==14'h7) VmeDtAck_on <= #1 1'b0; //delaying of 2 cycle extra
else VmeDtAck_on <= #1 VmeDtAck_on;
if (NextState_ab3 == s_Idle) begin
if (IntModeRora_i) RoraTimeoutCounter_c10 <= #1 'h0;
if (~NewIntRequest_iqp) IntToAckCounter_c8 <= #1 IntToAckCounter_c8 - 1'b1;
end
end
s_IAckPass: begin