Commit be0cf21a authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[Wr-dev] expose WR fabric interface with optional streamers

parent f6d6e323
......@@ -410,7 +410,10 @@ i_I2cIoExpAndMux (
//*****************************
//WR PTP core Wrapper for VFCHD
//*****************************
xwrc_board_vfchd #(.g_simulation(0), .g_dpram_initf("wrc.mif"))
xwrc_board_vfchd #(.g_simulation(0),
.g_fabric_iface("streamers"),
.g_streamer_width(208),
.g_dpram_initf("wrc.mif"))
i_WrpcWrapper
(
.clk_board_125m_i (GbitTrxClkRefR_ik),
......
wr-cores @ 0b9df80e
Subproject commit 1a128dc43d54bacd130b65f5762b81cb756ac4b3
Subproject commit 0b9df80e96dd0b7c22ce84e3b3ba19a034fd03cd
......@@ -1978,6 +1978,19 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id WbClockDomain
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id WbClockDomain
set_global_assignment -name SEARCH_PATH ../../../FpgaModules/SystemSpecific/WhiteRabbit/
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/gc_escape_detector.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/timing/pulse_stamper.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/fabric/xwb_fabric_source.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/fabric/xwb_fabric_sink.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/gc_escape_inserter.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/dropping_buffer.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/wr_transmission_wb.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/xrx_streamer.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/xtx_streamer.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/streamers_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_streamers/xwr_transmission.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gc_sync_register.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/altera/gc_shiftreg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
......
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