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Commit c9963236 authored by Manoel Barros Marin's avatar Manoel Barros Marin
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- Added VFC HD Base Project files

parent 2eda630f
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.gitignore
View file @ c9963236
......@@ -47,9 +47,18 @@ Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/veril
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
Hdl/Synthesis/BoardTest/QuartusPrj/db/
Hdl/Synthesis/BoardTest/QuartusPrj/incremental_db/compiled_partitions/
Hdl/Synthesis/BoardTest/QuartusPrj/incremental_db/
Hdl/Synthesis/BoardTest/QuartusPrj/compiled_partitions/
Hdl/Synthesis/BoardTest/QuartusPrj/output_files
Hdl/Synthesis/BoardTest/QuartusPrj/*.txt
Hdl/Synthesis/BoardTest/QuartusPrj/*.qws
Hdl/Synthesis/BoardTest/QuartusPrj/*.qpf
Hdl/Synthesis/BaseProject/QuartusPrj/db/
Hdl/Synthesis/BaseProject/QuartusPrj/incremental_db/
Hdl/Synthesis/BaseProject/QuartusPrj/compiled_partitions/
Hdl/Synthesis/BaseProject/QuartusPrj/output_files
Hdl/Synthesis/BaseProject/QuartusPrj/*.txt
Hdl/Synthesis/BaseProject/QuartusPrj/*.qws
Hdl/Synthesis/BaseProject/QuartusPrj/*.qpf
*.bak
*.pyc
\ No newline at end of file
Hdl/FpgaModules/ApplicationSpecific/BaseProject/AddrDecoderWbApp.v
View file @ c9963236
......@@ -7,111 +7,60 @@ module AddrDecoderWBApp(
output reg [31:0] Dat_ob32,
output reg Ack_o,
input [31:0] DatI2cPllRef_ib32,
input AckI2cPllRef_i,
output reg StbI2cPllRef_o,
input [31:0] DatAppReleaseId_ib32,
input AckAppReleaseId_i,
output reg StbAppReleaseId_o,
input [31:0] DatPeriodCounter_ib32,
input AckPeriodCounter_i,
output reg StbPeriodCounter_o,
input [31:0] DatSpiMaster_ib32,
input AckSpiMaster_i,
output reg StbSpiMaster_o,
input [31:0] DatFmcTest_ib32,
input AckFmcTest_i,
output reg StbFmcTest_o,
input [31:0] DatCtrlReg_ib32,
input AckCtrlReg_i,
output reg StbCtrlReg_o,
input [31:0] DatMgtTest_ib32,
input AckMgtTest_i,
output reg StbMgtTest_o,
input [31:0] DatGpIoControl_ib32,
input AckGpIoControl_i,
output reg StbGpIoControl_o
input [31:0] DatStatReg_ib32,
input AckStatReg_i,
output reg StbStatReg_o
);
localparam dly = 1;
reg [7:0] SelectedModule_b8;
reg [1:0] SelectedModule_b2;
localparam c_SelNothing = 8'h0,
c_SelI2cPllRef = 8'd1,
c_SelPeriodCounter = 8'd2,
c_SelSpiMaster = 8'd3,
c_SelFmcTest = 8'd4,
c_SelMgtTest = 8'd5,
c_SelGpIoControl = 8'd6,
c_SelAppRevisionId = 8'd7;
localparam c_SelNothing = 2'd0,
c_SelAppRevisionId = 2'd1,
c_SelCtrlReg = 2'd2,
c_SelStatReg = 2'd3;
always @*
casez(Adr_ib21)
21'b0_0000_0000_0000_0000_00??: SelectedModule_b8 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0000_01??: SelectedModule_b8 = c_SelPeriodCounter; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0000_1???: SelectedModule_b8 = c_SelSpiMaster; // FROM 00_0008 TO 00_000F (WB) == FROM 00_0020 TO 00_003C (VME) <- 8 regs ( 32B)
21'b0_0000_0000_0000_0001_00??: SelectedModule_b8 = c_SelGpIoControl; // FROM 00_0010 TO 00_0013 (WB) == FROM 00_0040 TO 00_004C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_0001_01??: SelectedModule_b8 = c_SelI2cPllRef; // FROM 00_0014 TO 00_0017 (WB) == FROM 00_0050 TO 00_005C (VME) <- 4 regs ( 16B)
21'b0_0000_0000_0000_001?_????: SelectedModule_b8 = c_SelFmcTest; // FROM 00_0020 TO 00_003F (WB) == FROM 00_0080 TO 00_00FC (VME) <- 32 regs (128B)
21'b0_0000_0000_0000_1???_????: SelectedModule_b8 = c_SelMgtTest; // FROM 00_0080 TO 00_00FF (WB) == FROM 00_0200 TO 00_03FC (VME) <- 128 regs (512B)
default: SelectedModule_b8 = c_SelNothing;
endcase
21'b0_0000_0000_0000_0000_00??: SelectedModule_b2 = c_SelAppRevisionId; // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_01??: SelectedModule_b2 = c_SelCtrlReg; // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
21'b0_0000_0000_0000_0000_10??: SelectedModule_b2 = c_SelStatReg; // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
default: SelectedModule_b2 = c_SelNothing;
endcase
always @(posedge Clk_ik) begin
Ack_o <= #dly 1'b0;
Dat_ob32 <= #dly 32'h0;
StbI2cPllRef_o <= #dly 1'b0;
StbPeriodCounter_o <= #dly 1'b0;
StbSpiMaster_o <= #dly 1'b0;
StbMgtTest_o <= #dly 1'b0;
StbFmcTest_o <= #dly 1'b0;
StbGpIoControl_o <= #dly 1'b0;
StbAppReleaseId_o <= #dly 1'b0;
case(SelectedModule_b8)
Ack_o <= #dly 1'b0;
Dat_ob32 <= #dly 32'h0;
StbAppReleaseId_o <= #dly 1'b0;
StbCtrlReg_o <= #dly 1'b0;
StbStatReg_o <= #dly 1'b0;
case(SelectedModule_b2)
c_SelAppRevisionId: begin
StbAppReleaseId_o <= #dly Stb_i;
Dat_ob32 <= #dly DatAppReleaseId_ib32;
Ack_o <= #dly AckAppReleaseId_i;
StbAppReleaseId_o <= #dly Stb_i;
Dat_ob32 <= #dly DatAppReleaseId_ib32;
Ack_o <= #dly AckAppReleaseId_i;
end
c_SelI2cPllRef: begin
StbI2cPllRef_o <= #dly Stb_i;
Dat_ob32 <= #dly DatI2cPllRef_ib32;
Ack_o <= #dly AckI2cPllRef_i;
c_SelCtrlReg: begin
StbCtrlReg_o <= #dly Stb_i;
Dat_ob32 <= #dly DatCtrlReg_ib32;
Ack_o <= #dly AckCtrlReg_i;
end
c_SelPeriodCounter: begin
StbPeriodCounter_o <= #dly Stb_i;
Dat_ob32 <= #dly DatPeriodCounter_ib32;
Ack_o <= #dly AckPeriodCounter_i;
end
c_SelSpiMaster: begin
StbSpiMaster_o <= #dly Stb_i;
Dat_ob32 <= #dly DatSpiMaster_ib32;
Ack_o <= #dly AckSpiMaster_i;
end
c_SelFmcTest: begin
StbFmcTest_o <= #dly Stb_i;
Dat_ob32 <= #dly DatFmcTest_ib32;
Ack_o <= #dly AckFmcTest_i;
c_SelStatReg: begin
StbStatReg_o <= #dly Stb_i;
Dat_ob32 <= #dly DatStatReg_ib32;
Ack_o <= #dly AckStatReg_i;
end
c_SelMgtTest: begin
StbMgtTest_o <= #dly Stb_i;
Dat_ob32 <= #dly DatMgtTest_ib32;
Ack_o <= #dly AckMgtTest_i;
end
c_SelGpIoControl: begin
StbGpIoControl_o <= #dly Stb_i;
Dat_ob32 <= #dly DatGpIoControl_ib32;
Ack_o <= #dly AckGpIoControl_i;
end
endcase
end
endmodule
endmodule
\ No newline at end of file
Hdl/FpgaModules/ApplicationSpecific/BaseProject/VfcHdApplication.v
View file @ c9963236
`timescale 1ns/100ps
module VfcHdApplication
#(parameter g_ApplicationVersion_b8 = 8'ha3,
g_ApplicationReleaseDay_b8 = 8'h18,
g_ApplicationReleaseMonth_b8 = 8'h06,
g_ApplicationReleaseYear_b8 = 8'h15)
#(parameter g_ApplicationVersion_b8 = 8'hb1,
g_ApplicationReleaseDay_b8 = 8'h01,
g_ApplicationReleaseMonth_b8 = 8'h03,
g_ApplicationReleaseYear_b8 = 8'h16)
(
//@@@@@@@@@@@@@@@@@@@@@@@@@
//External connections
......@@ -145,37 +145,19 @@ module VfcHdApplication
//Declarations
//****************************
wire SpiClk_k, SpiMoSi;
wire [31:0] SpiSs_nb32;
reg [2:0] Clk125Divider_c3 = 0;
wire [31:0] PeriodClk20VCO_b32, PeriodClk125VCO_b32;
wire DavPeriodClk20, DavPeriodClk125;
wire WbStbSpiMaster, WbAckSpiMaster;
wire [31:0] WbDatSpiMaster_b32;
wire WbStbI2cPllRef, WbAckI2cPllRef;
wire [31:0] WbDatI2cPllRef_b32;
wire Clk_k;
wire WbStbAppReleaseId, WbAckAppReleaseId;
wire [31:0] WbDatAppReleaseId_b32;
wire WbStbPeriodCounter, WbAckPeriodCounter;
wire [31:0] WbDatPeriodCounter_b32;
reg [2:0] FmcRClkDivider_c3;
wire [31:0] PeriodFmcRClk_b32, PCFmcRClkSynchFifoDout_b32;
wire PCFmcRClkDav;
wire [1:0] PCFmcRClkSynchFifoELvl_b2;
reg [2:0] FmcLClkDivider_c3;
wire [31:0] PeriodFmcLClk_b32, PCFmcLClkSynchFifoDout_b32;
wire PCFmcLClkDav;
wire [1:0] PCFmcLClkSynchFifoELvl_b2;
reg [2:0] PllRefClkDivider_c3;
wire [31:0] PeriodPllRefClk_b32, PCPllRefClkSynchFifoDout_b32;
wire PCPllRefClkDav;
wire [1:0] PCPllRefClkSynchFifoELvl_b2;
wire WbStbFmcTest, WbAckFmcTest;
wire [31:0] WbDatFmcTest_b32;
wire WbStbMgtTest, WbAckMgtTest;
wire [31:0] WbDatMgtTest_b32;
wire WbStbGpIoControl, WbAckGpIoControl;
wire [31:0] WbDatGpIoControl_b32;
wire WbStbCtrlReg, WbAckCtrlReg;
wire [31:0] WbDatCtrlReg_b32;
wire WbStbStatReg, WbAckStatReg;
wire [31:0] WbDatStatReg_b32;
wire [31:0] Reg0Value_b32;
wire [31:0] Reg1Value_b32;
wire [31:0] Reg2Value_b32;
wire [31:0] Reg3Value_b32;
//****************************
//Fixed assignments
......@@ -187,7 +169,7 @@ assign OeSi57x_oe = 1'b1;
//Clocking
//****************************
wire Clk_k = GbitTrxClkRefR_ik; //~125MHz
assign Clk_k = GbitTrxClkRefR_ik; //~125MHz
assign WbClk_ok = Clk_k;
//****************************
......@@ -205,30 +187,13 @@ AddrDecoderWBApp i_AddrDecoderWbApp(
.AckAppReleaseId_i(WbAckAppReleaseId),
.StbAppReleaseId_o(WbStbAppReleaseId),
.DatI2cPllRef_ib32(WbDatI2cPllRef_b32),
.AckI2cPllRef_i(WbAckI2cPllRef),
.StbI2cPllRef_o(WbStbI2cPllRef),
.DatPeriodCounter_ib32(WbDatPeriodCounter_b32),
.AckPeriodCounter_i(WbAckPeriodCounter),
.StbPeriodCounter_o(WbStbPeriodCounter),
.DatSpiMaster_ib32(WbDatSpiMaster_b32),
.AckSpiMaster_i(WbAckSpiMaster),
.StbSpiMaster_o(WbStbSpiMaster),
.DatCtrlReg_ib32(WbDatCtrlReg_b32),
.AckCtrlReg_i(WbAckCtrlReg),
.StbCtrlReg_o(WbStbCtrlReg),
.DatFmcTest_ib32(WbDatFmcTest_b32),
.AckFmcTest_i(WbAckFmcTest),
.StbFmcTest_o(WbStbFmcTest),
.DatMgtTest_ib32(WbDatMgtTest_b32),
.AckMgtTest_i(WbAckMgtTest),
.StbMgtTest_o(WbStbMgtTest),
.DatGpIoControl_ib32(WbDatGpIoControl_b32),
.AckGpIoControl_i(WbAckGpIoControl),
.StbGpIoControl_o(WbStbGpIoControl));
.DatStatReg_ib32(WbDatStatReg_b32),
.AckStatReg_i(WbAckStatReg),
.StbStatReg_o(WbStbStatReg));
//****************************
//ReleaseID
......@@ -244,263 +209,52 @@ Generic4InputRegs i_RevisionAndMisc(
.Ack_oa(WbAckAppReleaseId),
.Reg0Value_ib32("VFC "),
.Reg1Value_ib32("HD: "),
.Reg2Value_ib32("test"),
.Reg3Value_ib32({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
//****************************
//PLL DAC control
//****************************
SpiMasterWB i_SpiMaster(
.Rst_irq(Reset_irqp),
.Clk_ik(Clk_k),
.Cyc_i(WbSlaveCyc_i),
.Stb_i(WbStbSpiMaster),
.We_i(WbSlaveWr_i),
.Adr_ib3(WbSlaveAdr_ib25[2:0]),
.Dat_ib32(WbSlaveDat_ib32),
.Dat_oab32(WbDatSpiMaster_b32),
.Ack_oa(WbAckSpiMaster),
.SClk_o(SpiClk_k),
.MoSi_o(SpiMoSi),
.MiSo_ib32(),
.SS_onb32(SpiSs_nb32));
assign PllDac25Sync_o = SpiSs_nb32[0];
assign PllDacSclk_ok = SpiClk_k;
assign PllDacDin_o = SpiMoSi;
assign PllDac20Sync_o = SpiSs_nb32[1];
assign PllDacSclk_ok = SpiClk_k;
assign PllDacDin_o = SpiMoSi;
//****************************
//PLL ref
//****************************
assign PllSourceMuxOut_ok = Si57xClk_ik;
I2CMaster #(.g_CycleLenght(10'd1000)) //test slower communication: standard is about 256
i_I2cPllRef
(
.Rst_irq(Reset_irqp),
.Clk_ik(Clk_k),
.Cyc_i(WbSlaveCyc_i),
.Stb_i(WbStbI2cPllRef),
.We_i(WbSlaveWr_i),
.Adr_ib2(WbSlaveAdr_ib25[1:0]),
.Dat_ib32(WbSlaveDat_ib32),
.Dat_oab32(WbDatI2cPllRef_b32),
.Ack_oa(WbAckI2cPllRef),
.Scl_ioz(PllRefScl_ok),
.Sda_ioz(PllRefSda_io));
.Reg2Value_ib32("base"),
.Reg3Value_ib32({g_ApplicationVersion_b8, g_ApplicationReleaseDay_b8, g_ApplicationReleaseMonth_b8, g_ApplicationReleaseYear_b8}));
//****************************
//Voltage Controlled osc measurement
//****************************
wire PC20Dav, PC125Dav;
wire [1:0] PC20SynchFifoELvl_b2, PC125SynchFifoELvl_b2;
wire [31:0] PC20SynchFifoDout_b32, PC125SynchFifoDout_b32;
PeriodCounter #(
.g_PeriodRangeTopLog2(3),
.g_OutputBits(32),
.g_NBits(20))
i_PeriodCounter20VcXo(
.Input_a(Clk20VCOx_ik),
.ReferenceClock_ik(Si57xClk_ik),
.Rst_ir(1'b0),
.Output_ob(PeriodClk20VCO_b32),
.NewDataOut_o(PC20Dav));
generic_fifo_dc_gray #(.dw(32), .aw(2))
i_PC20SynchFifo (
.rd_clk(Clk_k),
.wr_clk(Si57xClk_ik),
.rst(1'b1),
.clr(Reset_irqp),
.din(PeriodClk20VCO_b32),
.we(PC20Dav),
.dout(PC20SynchFifoDout_b32),
.re({~PC20SynchFifoELvl_b2[1]}), //keeps a single value in the fifo (2?)
.rd_level(PC20SynchFifoELvl_b2));
always @(posedge GbitTrxClkRefR_ik) Clk125Divider_c3 <= #1 Clk125Divider_c3 + 1'b1;
PeriodCounter #(
.g_PeriodRangeTopLog2(3),
.g_OutputBits(32),
.g_NBits(20))
i_PeriodCounter125Clk(
.Input_a(Clk125Divider_c3[2]),
.ReferenceClock_ik(Si57xClk_ik),
.Rst_ir(1'b0),
.Output_ob(PeriodClk125VCO_b32),
.NewDataOut_o(PC125Dav));
generic_fifo_dc_gray #(.dw(32), .aw(2))
i_PC125SynchFifo (
.rd_clk(Clk_k),
.wr_clk(Si57xClk_ik),
.rst(1'b1),
.clr(Reset_irqp),
.din(PeriodClk125VCO_b32),
.we(PC125Dav),
.dout(PC125SynchFifoDout_b32),
.re({~PC125SynchFifoELvl_b2[1]}), //keeps a single value in the fifo (2?)
.rd_level(PC125SynchFifoELvl_b2));
always @(posedge PllRefClkOut_ik) PllRefClkDivider_c3 <= #1 PllRefClkDivider_c3 + 1'b1;
PeriodCounter #(
.g_PeriodRangeTopLog2(3),
.g_OutputBits(32),
.g_NBits(20))
i_PeriodCounterPllRefClk(
.Input_a(PllRefClkDivider_c3[2]),
.ReferenceClock_ik(Si57xClk_ik),
.Rst_ir(1'b0),
.Output_ob(PeriodPllRefClk_b32),
.NewDataOut_o(PCPllRefClkDav));
generic_fifo_dc_gray #(.dw(32), .aw(2))
i_PCPllRefClkSynchFifo (
.rd_clk(Clk_k),
.wr_clk(Si57xClk_ik),
.rst(1'b1),
.clr(Reset_irqp),
.din(PeriodPllRefClk_b32),
.we(PCPllRefClkDav),
.dout(PCPllRefClkSynchFifoDout_b32),
.re({~PCPllRefClkSynchFifoELvl_b2[1]}), //keeps a single value in the fifo (2?)
.rd_level(PCPllRefClkSynchFifoELvl_b2));
Generic4InputRegs i_PeriodCounterWbInt(
.Rst_irq(Reset_irqp),
.Clk_ik(Clk_k),
.Cyc_i(WbSlaveCyc_i),
.Stb_i(WbStbPeriodCounter),
.Adr_ib2(WbSlaveAdr_ib25[1:0]),
.Dat_oab32(WbDatPeriodCounter_b32),
.Ack_oa(WbAckPeriodCounter),
.Reg0Value_ib32(PC20SynchFifoDout_b32),
.Reg1Value_ib32(PC125SynchFifoDout_b32),
.Reg2Value_ib32(PCPllRefClkSynchFifoDout_b32),
.Reg3Value_ib32());
//Example Registers
//****************************
//GpIoControl
//****************************
wire [4:1] GpioIntVal_b4, GpioLoopBack_b4, GpioDummy_b4, GpioIntOe_b4;
assign GpIo_iob4[4] = (GpioIntOe_b4[4]&&GpioIntOe_b4[3]) ? (GpioLoopBack_b4[4]? GpIo_iob4[2]: GpioIntVal_b4[4]) : 1'bz;
assign GpIo_iob4[3] = (GpioIntOe_b4[4]&&GpioIntOe_b4[3]) ? (GpioLoopBack_b4[3]? GpIo_iob4[1]: GpioIntVal_b4[3]) : 1'bz;
assign GpIo_iob4[2] = GpioIntOe_b4[2] ? (GpioLoopBack_b4[2]? GpIo_iob4[4]: GpioIntVal_b4[2]) : 1'bz;
assign GpIo_iob4[1] = GpioIntOe_b4[1] ? (GpioLoopBack_b4[1]? GpIo_iob4[3]: GpioIntVal_b4[1]) : 1'bz;
wire [31:0] GpIoControl_b32;
assign {GpioIntOe_b4[4], GpioDummy_b4[4], GpioLoopBack_b4[4], GpioIntVal_b4[4]} = GpIoControl_b32[15:12];
assign {GpioIntOe_b4[3], GpioDummy_b4[3], GpioLoopBack_b4[3], GpioIntVal_b4[3]} = GpIoControl_b32[11:8];
assign {GpioIntOe_b4[2], GpioDummy_b4[2], GpioLoopBack_b4[2], GpioIntVal_b4[2]} = GpIoControl_b32[7:4];
assign {GpioIntOe_b4[1], GpioDummy_b4[1], GpioLoopBack_b4[1], GpioIntVal_b4[1]} = GpIoControl_b32[3:0];
Generic4OutputRegs #(
.Reg0Default(32'habcd0000),
.Reg1Default(32'habcd0001),
.Reg2Default(32'habcd0002),
.Reg3Default(32'habcd0003))
i_GpIoControl (
.Rst_irq(Reset_irqp),
.Clk_ik(Clk_k),
.Cyc_i(WbSlaveCyc_i),
.Stb_i(WbStbGpIoControl),
.Adr_ib2(WbSlaveAdr_ib25[1:0]),
.Dat_oab32(WbDatGpIoControl_b32),
.Dat_ib32(WbSlaveDat_ib32),
.We_i(WbSlaveWr_i),
.Ack_oa(WbAckGpIoControl),
.Reg0Value_ob32(GpIoControl_b32),
.Reg1Value_ob32(),
.Reg2Value_ob32(),
.Reg3Value_ob32());
//****************************
//MGT test
//****************************
/*
mgt_test_wrapper i_MgtTest (
.Reset_irqp (Reset_irqp),
//Wishbone interface:
.Clk_ik (Clk_k),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbMgtTest),
.We_i (WbSlaveWr_i),
.Adr_ib7 (WbSlaveAdr_ib25[6:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_ob32 (WbDatMgtTest_b32),
.Ack_o (WbAckMgtTest),
//Left side:
.FmcGbtClk0M2CLeft_ik (FmcGbtClk0M2CLeft_ik),
.GxL01235_TxSerialData_o ({BstSfpTx_o,AppSfpTx_ob4[4],AppSfpTx_ob4[3],AppSfpTx_ob4[2],AppSfpTx_ob4[1]}),
.GxL01235_RxSerialData_i ({BstSfpRx_i,AppSfpRx_ib4[4],AppSfpRx_ib4[3],AppSfpRx_ib4[2],AppSfpRx_ib4[1]}),
.GxL678_TxSerialData_o ({FmcDpC2M_ob10[7],FmcDpC2M_ob10[8],FmcDpC2M_ob10[6]}),
.GxL678_RxSerialData_i ({FmcDpM2C_ib10[7],FmcDpM2C_ib10[8],FmcDpM2C_ib10[6]}),
//Right side:
.FmcGbtClk0M2CRight_ik (FmcGbtClk0M2CRight_ik),
.GxR6891011_TxSerialData_o ({FmcDpC2M_ob10[0],FmcDpC2M_ob10[1],FmcDpC2M_ob10[2],FmcDpC2M_ob10[3],EthSfpTx_o}),
.GxR6891011_RxSerialData_i ({FmcDpM2C_ib10[0],FmcDpM2C_ib10[1],FmcDpM2C_ib10[2],FmcDpM2C_ib10[3],EthSfpRx_i}),
.GxR012_TxSerialData_o ({FmcDpC2M_ob10[4],FmcDpC2M_ob10[9],FmcDpC2M_ob10[5]}),
.GxR012_RxSerialData_i ({FmcDpM2C_ib10[4],FmcDpM2C_ib10[9],FmcDpM2C_ib10[5]}));
*/
//****************************
//FMC User I/O & Ctrl test
//****************************
//Control Register Bank:
Generic4OutputRegs #(
.Reg0Default (32'hBABEB00B),
.Reg0AutoClrMask (32'hF),
.Reg1Default (32'hCAFEAC1D),
.Reg1AutoClrMask (32'hF),
.Reg2Default (32'hACDCDEAD),
.Reg2AutoClrMask (32'hF),
.Reg3Default (32'hFEEDBEEF),
.Reg3AutoClrMask (32'hF))
i_ControlRegs (
.Rst_irq (Reset_irqp),
.Clk_ik (Clk_k),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbCtrlReg),
.We_i (WbSlaveWr_i),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_oab32 (WbDatCtrlReg_b32),
.Ack_oa (WbAckCtrlReg),
//--
.Reg0Value_ob32 (Reg0Value_b32),
.Reg1Value_ob32 (Reg1Value_b32),
.Reg2Value_ob32 (Reg2Value_b32),
.Reg3Value_ob32 (Reg3Value_b32));
fmc_test_wrapper i_FmcTest(
.Reset_irqp (Reset_irqp),
//Wishbone interface:
.Clk_ik (Clk_k),
.Cyc_i (WbSlaveCyc_i),
.Stb_i (WbStbFmcTest),
.We_i (WbSlaveWr_i),
.Adr_ib5 (WbSlaveAdr_ib25[4:0]),
.Dat_ib32 (WbSlaveDat_ib32),
.Dat_ob32 (WbDatFmcTest_b32),
.Ack_o (WbAckFmcTest),
//FMC interface:
.FmcLaP_iob34 (FmcLaP_iob34),
.FmcLaN_iob34 (FmcLaN_iob34),
.FmcHaP_iob24 (FmcHaP_iob24),
.FmcHaN_iob24 (FmcHaN_iob24),
.FmcHbP_iob22 (FmcHbP_iob22),
.FmcHbN_iob22 (FmcHbN_iob22),
.FmcPrsntM2C_in (FmcPrsntM2C_in),
.FmcTck_ok (FmcTck_ok),
.FmcTms_o (FmcTms_o),
.FmcTdi_o (FmcTdi_o),
.FmcTdo_i (FmcTdo_i),
.FmcTrstL_orn (FmcTrstL_orn),
.FmcScl_ok (FmcScl_ok),
.FmcSda_io (FmcSda_io),
.FmcPgM2C_in (FmcPgM2C_in),
.FmcPgC2M_on (FmcPgC2M_on),
.FmcClkDir_i (FmcClkDir_i),
.FmcClk0M2CCmos_ik (FmcClk0M2CCmos_ik),
.FmcClk1M2CCmos_ik (FmcClk1M2CCmos_ik),
.FmcClk2Bidir_ik (FmcClk2Bidir_ik),
.FmcClk3Bidir_ik (FmcClk3Bidir_ik),
.FmcGbtClk0M2CLeft_ik (FmcGbtClk0M2CLeft_ik),
.FmcGbtClk1M2CLeft_ik (FmcGbtClk1M2CLeft_ik),
.FmcGbtClk0M2CRight_ik(FmcGbtClk0M2CRight_ik),
.FmcGbtClk1M2CRight_ik(FmcGbtClk1M2CRight_ik));
//Status Registers Bank:
Generic4InputRegs i_Status (
.Rst_irq (Reset_irqp),
.Cyc_i (Clk_k),
.Stb_i (WbSlaveCyc_i),
.Clk_ik (WbStbStatReg),
.Adr_ib2 (WbSlaveAdr_ib25[1:0]),
.Dat_oab32 (WbDatStatReg_b32),
.Ack_oa (WbAckStatReg),
//--
.Reg0Value_ib32 (Reg0Value_b32),
.Reg1Value_ib32 (Reg1Value_b32),
.Reg2Value_ib32 (Reg2Value_b32),
.Reg3Value_ib32 (Reg3Value_b32));